Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44709075	1			T1	18579		T2	8767		T3	91808
triple_byte_access	2566182	1			T1	368		T2	171		T3	1785
halfword_access	3853431	1			T1	561		T2	243		T3	2794
byte_access	5142511	1			T1	794		T2	367		T3	3658
zero_access	1293259	1			T1	198		T2	94		T3	904

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28727346

1

T1

10237

T2

4760

T3

50640

auto[1]

28837112

1

T1

10263

T2

4882

T3

50309

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22302671	1			T1	9280		T2	4304		T3	45961
auto[0]	triple_byte_access	1280744	1			T1	177		T2	89		T3	917
auto[0]	halfword_access	1922912	1			T1	281		T2	122		T3	1450
auto[0]	byte_access	2570128	1			T1	404		T2	193		T3	1843
auto[0]	zero_access	650891	1			T1	95		T2	52		T3	469
auto[1]	word_access	22406404	1			T1	9299		T2	4463		T3	45847
auto[1]	triple_byte_access	1285438	1			T1	191		T2	82		T3	868
auto[1]	halfword_access	1930519	1			T1	280		T2	121		T3	1344
auto[1]	byte_access	2572383	1			T1	390		T2	174		T3	1815
auto[1]	zero_access	642368	1			T1	103		T2	42		T3	435