Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	146175940	1			T1	3686		T2	19536		T4	227876
instr_valid_dis	112948493	1			T1	3686		T2	19536		T4	227876
instr_en	22050099	1			T5	205954		T11	83042		T12	42

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10950474	1			T5	20496		T11	97258		T18	21426
sram_ifetch_valid_disable	111019406	1			T1	3686		T2	19536		T4	227876
sram_ifetch_enable	24206060	1			T5	164430		T11	47818		T18	104274

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	146175940	1			T1	3686		T2	19536		T4	227876
hw_debug_en_valid_off	114202384	1			T1	3686		T2	19536		T4	227876
hw_debug_en_on	21191949	1			T5	118174		T11	91678		T18	54266

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111019406	1			T1	3686		T2	19536		T4	227876
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	98436320	1			T1	3686		T2	19536		T4	227876
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8184644	1			T5	104606		T11	49646		T12	42
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5020915	1			T5	20000		T11	61558		T59	52344
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2209260	1			T11	61558		T59	52344		T68	71800
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1947429	1			T21	27522		T139	15210		T140	422120
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4124009	1			T5	496		T11	15700		T18	21426
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1954871	1			T11	12920		T18	21426		T59	28434
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1544352	1			T5	496		T11	2780		T62	33928
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7669214	1			T5	38606		T11	52910		T59	67922
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3157728	1			T5	23992		T59	67922		T68	58028
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3182104	1			T5	2372		T11	20354		T21	27230

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9829002	1			T5	100852		T11	10616		T19	15996
lc_exec_en	9398726	1			T5	79072		T11	23068		T18	32840
valid_exec_dis	108366349	1			T1	3686		T2	19536		T4	227876
invalid_exec_dis	35156534	1			T5	184926		T11	145076		T18	125700