Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.93 99.16 94.27 99.72 100.00 95.95 99.12 97.26


Total tests in report: 1018
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.65 89.65 97.12 97.12 83.89 83.89 92.65 92.65 90.48 90.48 90.58 90.58 94.25 94.25 78.61 78.61 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.87137703
92.55 2.90 98.31 1.19 86.37 2.49 94.66 2.01 100.00 9.52 93.24 2.66 94.84 0.59 80.44 1.83 /workspace/coverage/default/13.sram_ctrl_lc_escalation.1765303764
93.77 1.22 98.56 0.25 86.37 0.00 97.09 2.43 100.00 0.00 93.72 0.48 95.43 0.59 85.19 4.75 /workspace/coverage/default/18.sram_ctrl_executable.2170208517
94.71 0.95 98.73 0.17 86.97 0.59 97.30 0.21 100.00 0.00 94.44 0.72 95.43 0.00 90.13 4.94 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2232798013
95.42 0.71 98.90 0.17 88.63 1.66 97.43 0.14 100.00 0.00 95.41 0.97 96.17 0.74 91.41 1.28 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1836164480
96.12 0.70 99.07 0.17 90.40 1.78 98.13 0.69 100.00 0.00 96.14 0.72 96.76 0.59 92.32 0.91 /workspace/coverage/default/3.sram_ctrl_sec_cm.845447587
96.49 0.38 99.07 0.00 90.40 0.00 98.23 0.10 100.00 0.00 96.14 0.00 96.90 0.15 94.70 2.38 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1054816769
96.68 0.19 99.07 0.00 90.64 0.24 98.23 0.00 100.00 0.00 96.14 0.00 97.64 0.74 95.06 0.37 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2027663967
96.85 0.17 99.07 0.00 90.64 0.00 98.47 0.24 100.00 0.00 96.14 0.00 97.64 0.00 95.98 0.91 /workspace/coverage/default/1.sram_ctrl_stress_all.500625474
96.98 0.13 99.15 0.08 90.64 0.00 99.31 0.83 100.00 0.00 96.14 0.00 97.64 0.00 95.98 0.00 /workspace/coverage/default/14.sram_ctrl_ram_cfg.3350307677
97.11 0.13 99.15 0.00 90.64 0.00 99.31 0.00 100.00 0.00 96.14 0.00 98.53 0.88 95.98 0.00 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1620072208
97.20 0.09 99.15 0.00 90.64 0.00 99.38 0.07 100.00 0.00 96.14 0.00 99.12 0.59 95.98 0.00 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.649281454
97.28 0.08 99.15 0.00 91.00 0.36 99.58 0.21 100.00 0.00 96.14 0.00 99.12 0.00 95.98 0.00 /workspace/coverage/default/39.sram_ctrl_alert_test.2162031728
97.36 0.08 99.15 0.00 91.00 0.00 99.58 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.53 0.55 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.283213034
97.42 0.06 99.15 0.00 91.00 0.00 99.65 0.07 100.00 0.00 96.14 0.00 99.12 0.00 96.89 0.37 /workspace/coverage/default/40.sram_ctrl_stress_all.2711692406
97.47 0.05 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.26 0.37 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1732554255
97.48 0.01 99.15 0.00 91.00 0.00 99.72 0.07 100.00 0.00 96.14 0.00 99.12 0.00 97.26 0.00 /workspace/coverage/default/0.sram_ctrl_sec_cm.2519501248

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2712318470
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2202730574
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1965472779
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2774792628
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1877999776
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3452147337
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2478761179
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2140424711
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3592695619
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2906176031
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3861481934
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4235737315
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.188288472
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2644930878
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3449776279
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3180964119
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1277106892
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3311636058
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3585557684
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2505137564
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2097188310
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.518884555
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.773028100
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2633383786
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.538388105
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.556012744
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.313629912
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3483016277
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2741050922
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.384623383
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3773752515
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3789308778
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2021445313
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1521708571
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1077984775
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1462637667
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2462960774
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2353307471
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3691763399
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2537975444
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2712507879
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.319053567
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4163867843
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3485503632
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3476370688
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2429054290
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.230725848
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3776794401
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2135326060
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3430158494
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3552952996
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1280304855
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3084002302
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4080901480
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.836794094
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.380442761
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.592355970
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3257615942
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4039657506
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2711472197
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2383838883
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1536876326
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3077499785
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2273810729
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2185172557
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.893667482
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.829715773
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4097294016
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.248495719
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1999080441
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1980490496
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.341428415
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3466663545
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2413010294
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4274881685
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2440537110
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1567524290
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1687811205
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2278506117
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3838346348
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4101106768
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3474469121
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2803488108
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3283653371
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2884942743
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2967490871
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2573540322
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.342872055
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2420236181
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.853204499
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.619390881
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2879253280
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2617173149
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.375420503
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2030540600
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1307566408
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3793118283
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1023980173
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3063990604
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3902634594
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1439383734
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1125423842
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2527049155
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2463641994
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1683680629
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.767847669
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3363001816
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3695208603
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2469730959
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.193399139
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3531963867
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.428067346
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2014349341
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2457735251
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1590739797
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1770793255
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.914358278
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3931662050
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2067199110
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2940725461
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2055431289
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1773534693
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.720774800
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.318713257
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3239556189
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2386634817
/workspace/coverage/default/0.sram_ctrl_alert_test.3860181045
/workspace/coverage/default/0.sram_ctrl_bijection.1546583235
/workspace/coverage/default/0.sram_ctrl_executable.1267434825
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2544052692
/workspace/coverage/default/0.sram_ctrl_max_throughput.4187433946
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3294726393
/workspace/coverage/default/0.sram_ctrl_mem_walk.468476999
/workspace/coverage/default/0.sram_ctrl_multiple_keys.285770878
/workspace/coverage/default/0.sram_ctrl_partial_access.103245585
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2224733975
/workspace/coverage/default/0.sram_ctrl_ram_cfg.647541798
/workspace/coverage/default/0.sram_ctrl_regwen.1309835433
/workspace/coverage/default/0.sram_ctrl_smoke.3704613138
/workspace/coverage/default/0.sram_ctrl_stress_all.2333096046
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2074380285
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3337686973
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3584203592
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1203367424
/workspace/coverage/default/1.sram_ctrl_alert_test.3341718965
/workspace/coverage/default/1.sram_ctrl_bijection.131122148
/workspace/coverage/default/1.sram_ctrl_executable.1035705645
/workspace/coverage/default/1.sram_ctrl_lc_escalation.269199891
/workspace/coverage/default/1.sram_ctrl_max_throughput.1701238958
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1530915581
/workspace/coverage/default/1.sram_ctrl_mem_walk.2277558467
/workspace/coverage/default/1.sram_ctrl_multiple_keys.549119594
/workspace/coverage/default/1.sram_ctrl_partial_access.3239090991
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1054817564
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1311649922
/workspace/coverage/default/1.sram_ctrl_regwen.310738226
/workspace/coverage/default/1.sram_ctrl_sec_cm.1237613179
/workspace/coverage/default/1.sram_ctrl_smoke.3426707610
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1032031512
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1126094493
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1396786060
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2324418675
/workspace/coverage/default/10.sram_ctrl_alert_test.2955620749
/workspace/coverage/default/10.sram_ctrl_bijection.1574817043
/workspace/coverage/default/10.sram_ctrl_executable.954307081
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3213206922
/workspace/coverage/default/10.sram_ctrl_max_throughput.1560714898
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.4030972929
/workspace/coverage/default/10.sram_ctrl_mem_walk.3266038715
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2461147599
/workspace/coverage/default/10.sram_ctrl_partial_access.3636848966
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2289827911
/workspace/coverage/default/10.sram_ctrl_ram_cfg.493223827
/workspace/coverage/default/10.sram_ctrl_regwen.3264224538
/workspace/coverage/default/10.sram_ctrl_smoke.78199926
/workspace/coverage/default/10.sram_ctrl_stress_all.1027816277
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3374682811
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.4055390343
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2315512034
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2873547940
/workspace/coverage/default/11.sram_ctrl_alert_test.3489909600
/workspace/coverage/default/11.sram_ctrl_bijection.2141512251
/workspace/coverage/default/11.sram_ctrl_executable.1577403515
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2443452538
/workspace/coverage/default/11.sram_ctrl_max_throughput.3706163205
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.973010870
/workspace/coverage/default/11.sram_ctrl_mem_walk.1030172721
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1203268975
/workspace/coverage/default/11.sram_ctrl_partial_access.1859047019
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2007194204
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2979684620
/workspace/coverage/default/11.sram_ctrl_regwen.4281632316
/workspace/coverage/default/11.sram_ctrl_smoke.36097104
/workspace/coverage/default/11.sram_ctrl_stress_all.2686254757
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3065991396
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2132899766
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2725071703
/workspace/coverage/default/12.sram_ctrl_alert_test.2515958308
/workspace/coverage/default/12.sram_ctrl_bijection.1004543029
/workspace/coverage/default/12.sram_ctrl_executable.2915821273
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3142856105
/workspace/coverage/default/12.sram_ctrl_max_throughput.1412247009
/workspace/coverage/default/12.sram_ctrl_mem_walk.3849743902
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2161987547
/workspace/coverage/default/12.sram_ctrl_partial_access.2089152891
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.310258550
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3741976516
/workspace/coverage/default/12.sram_ctrl_regwen.3182830797
/workspace/coverage/default/12.sram_ctrl_smoke.3389485604
/workspace/coverage/default/12.sram_ctrl_stress_all.1468228654
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3957521096
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2805277798
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3845301171
/workspace/coverage/default/13.sram_ctrl_alert_test.1565886923
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/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2186778402
/workspace/coverage/default/44.sram_ctrl_alert_test.189068848
/workspace/coverage/default/44.sram_ctrl_bijection.919894152
/workspace/coverage/default/44.sram_ctrl_executable.574958775
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1875005142
/workspace/coverage/default/44.sram_ctrl_max_throughput.650173169
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1149473097
/workspace/coverage/default/44.sram_ctrl_mem_walk.309495349
/workspace/coverage/default/44.sram_ctrl_multiple_keys.15127421
/workspace/coverage/default/44.sram_ctrl_partial_access.3417957621
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2613742448
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1379983581
/workspace/coverage/default/44.sram_ctrl_regwen.3950776598
/workspace/coverage/default/44.sram_ctrl_smoke.2388020500
/workspace/coverage/default/44.sram_ctrl_stress_all.1644387093
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2775435313
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.592565600
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.787423773
/workspace/coverage/default/45.sram_ctrl_alert_test.2265779191
/workspace/coverage/default/45.sram_ctrl_bijection.3235762444
/workspace/coverage/default/45.sram_ctrl_executable.2373646671
/workspace/coverage/default/45.sram_ctrl_lc_escalation.42265833
/workspace/coverage/default/45.sram_ctrl_max_throughput.3497850037
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.4041390165
/workspace/coverage/default/45.sram_ctrl_mem_walk.1625352855
/workspace/coverage/default/45.sram_ctrl_multiple_keys.4176972675
/workspace/coverage/default/45.sram_ctrl_partial_access.2252490091
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.24061530
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1242419787
/workspace/coverage/default/45.sram_ctrl_regwen.3908479391
/workspace/coverage/default/45.sram_ctrl_smoke.1213458722
/workspace/coverage/default/45.sram_ctrl_stress_all.2647678471
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.526117919
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.4277014810
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3550682649
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.907492244
/workspace/coverage/default/46.sram_ctrl_alert_test.3978968353
/workspace/coverage/default/46.sram_ctrl_bijection.783462258
/workspace/coverage/default/46.sram_ctrl_executable.2222874078
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3156203526
/workspace/coverage/default/46.sram_ctrl_max_throughput.224146342
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.240170344
/workspace/coverage/default/46.sram_ctrl_mem_walk.2748071881
/workspace/coverage/default/46.sram_ctrl_multiple_keys.793519013
/workspace/coverage/default/46.sram_ctrl_partial_access.3343664568
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.925626387
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3370599416
/workspace/coverage/default/46.sram_ctrl_regwen.2845551531
/workspace/coverage/default/46.sram_ctrl_smoke.1939284909
/workspace/coverage/default/46.sram_ctrl_stress_all.526086751
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4032415107
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1633104956
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4049203716
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.396902519
/workspace/coverage/default/47.sram_ctrl_alert_test.3900824090
/workspace/coverage/default/47.sram_ctrl_bijection.4235829903
/workspace/coverage/default/47.sram_ctrl_executable.991870274
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3836476349
/workspace/coverage/default/47.sram_ctrl_max_throughput.2292892574
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.4031160354
/workspace/coverage/default/47.sram_ctrl_mem_walk.1081374524
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3625760763
/workspace/coverage/default/47.sram_ctrl_partial_access.3085376859
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2175674664
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1918928807
/workspace/coverage/default/47.sram_ctrl_regwen.1311688350
/workspace/coverage/default/47.sram_ctrl_smoke.1541884243
/workspace/coverage/default/47.sram_ctrl_stress_all.886300154
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3012630940
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1614862104
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3268634909
/workspace/coverage/default/48.sram_ctrl_alert_test.1733870378
/workspace/coverage/default/48.sram_ctrl_bijection.2009474687
/workspace/coverage/default/48.sram_ctrl_executable.397388929
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1281159499
/workspace/coverage/default/48.sram_ctrl_max_throughput.2020739781
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2610879207
/workspace/coverage/default/48.sram_ctrl_mem_walk.1808983575
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3399176420
/workspace/coverage/default/48.sram_ctrl_partial_access.422238208
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1029659549
/workspace/coverage/default/48.sram_ctrl_ram_cfg.260900792
/workspace/coverage/default/48.sram_ctrl_regwen.741101576
/workspace/coverage/default/48.sram_ctrl_smoke.3376692930
/workspace/coverage/default/48.sram_ctrl_stress_all.425726770
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3572981290
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3857083379
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3317030559
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.4245611189
/workspace/coverage/default/49.sram_ctrl_alert_test.2664181132
/workspace/coverage/default/49.sram_ctrl_bijection.797100038
/workspace/coverage/default/49.sram_ctrl_executable.3391159960
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2751129860
/workspace/coverage/default/49.sram_ctrl_max_throughput.902878702
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.81477122
/workspace/coverage/default/49.sram_ctrl_mem_walk.1787317665
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3727241530
/workspace/coverage/default/49.sram_ctrl_partial_access.2611541729
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1218396747
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1228803756
/workspace/coverage/default/49.sram_ctrl_regwen.4055907858
/workspace/coverage/default/49.sram_ctrl_smoke.3276871151
/workspace/coverage/default/49.sram_ctrl_stress_all.3290643627
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.337045749
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1156626620
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2880068150
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.773599695
/workspace/coverage/default/5.sram_ctrl_alert_test.3195820872
/workspace/coverage/default/5.sram_ctrl_bijection.3198942925
/workspace/coverage/default/5.sram_ctrl_executable.2876356671
/workspace/coverage/default/5.sram_ctrl_lc_escalation.877954396
/workspace/coverage/default/5.sram_ctrl_max_throughput.3245672537
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3853696806
/workspace/coverage/default/5.sram_ctrl_mem_walk.1581996954
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1079272378
/workspace/coverage/default/5.sram_ctrl_partial_access.578498561
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1064874710
/workspace/coverage/default/5.sram_ctrl_ram_cfg.4136514336
/workspace/coverage/default/5.sram_ctrl_regwen.3876576895
/workspace/coverage/default/5.sram_ctrl_smoke.1370909788
/workspace/coverage/default/5.sram_ctrl_stress_all.1520216987
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2288483256
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.883251381
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3797096904
/workspace/coverage/default/6.sram_ctrl_alert_test.3727400476
/workspace/coverage/default/6.sram_ctrl_bijection.3271768897
/workspace/coverage/default/6.sram_ctrl_executable.3235367209
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2015898157
/workspace/coverage/default/6.sram_ctrl_max_throughput.2874743115
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1957328792
/workspace/coverage/default/6.sram_ctrl_mem_walk.3150362297
/workspace/coverage/default/6.sram_ctrl_multiple_keys.922229103
/workspace/coverage/default/6.sram_ctrl_partial_access.3561358042
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2597404894
/workspace/coverage/default/6.sram_ctrl_regwen.499618365
/workspace/coverage/default/6.sram_ctrl_smoke.2109112857
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1702678877
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2607641529
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.503074314
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3473594163
/workspace/coverage/default/7.sram_ctrl_alert_test.707218662
/workspace/coverage/default/7.sram_ctrl_bijection.1133352366
/workspace/coverage/default/7.sram_ctrl_executable.1043722524
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3452855434
/workspace/coverage/default/7.sram_ctrl_max_throughput.1082859255
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.372733009
/workspace/coverage/default/7.sram_ctrl_mem_walk.847007372
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4193183779
/workspace/coverage/default/7.sram_ctrl_partial_access.3250770141
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.562428096
/workspace/coverage/default/7.sram_ctrl_ram_cfg.113881836
/workspace/coverage/default/7.sram_ctrl_regwen.2596805639
/workspace/coverage/default/7.sram_ctrl_smoke.1509158402
/workspace/coverage/default/7.sram_ctrl_stress_all.3989641679
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1927957919
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3692303617
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1843252449
/workspace/coverage/default/8.sram_ctrl_alert_test.3693847562
/workspace/coverage/default/8.sram_ctrl_bijection.1901318243
/workspace/coverage/default/8.sram_ctrl_executable.992203834
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1493887414
/workspace/coverage/default/8.sram_ctrl_max_throughput.2403242215
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.554815050
/workspace/coverage/default/8.sram_ctrl_mem_walk.1303865589
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3963024522
/workspace/coverage/default/8.sram_ctrl_partial_access.2393897764
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1900395177
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3531578297
/workspace/coverage/default/8.sram_ctrl_regwen.3544119136
/workspace/coverage/default/8.sram_ctrl_smoke.2386262475
/workspace/coverage/default/8.sram_ctrl_stress_all.298479733
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2629135230
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1168666752
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1037460134
/workspace/coverage/default/9.sram_ctrl_alert_test.2462879894
/workspace/coverage/default/9.sram_ctrl_bijection.3979176626
/workspace/coverage/default/9.sram_ctrl_executable.3131074680
/workspace/coverage/default/9.sram_ctrl_lc_escalation.4134650445
/workspace/coverage/default/9.sram_ctrl_max_throughput.1053607855
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3204616010
/workspace/coverage/default/9.sram_ctrl_mem_walk.3925211518
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1715333222
/workspace/coverage/default/9.sram_ctrl_partial_access.2955625469
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3730182960
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3661523854
/workspace/coverage/default/9.sram_ctrl_regwen.2124238467
/workspace/coverage/default/9.sram_ctrl_smoke.1867802918
/workspace/coverage/default/9.sram_ctrl_stress_all.1887554040
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2569194742
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4000720722



Total test records in report: 1018
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/17.sram_ctrl_lc_escalation.2622336220 Jul 29 07:37:36 PM PDT 24 Jul 29 07:37:40 PM PDT 24 572938432 ps
T2 /workspace/coverage/default/2.sram_ctrl_max_throughput.980167488 Jul 29 07:36:47 PM PDT 24 Jul 29 07:38:41 PM PDT 24 278226187 ps
T3 /workspace/coverage/default/8.sram_ctrl_ram_cfg.3531578297 Jul 29 07:37:13 PM PDT 24 Jul 29 07:37:14 PM PDT 24 30391845 ps
T4 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.454504476 Jul 29 07:39:06 PM PDT 24 Jul 29 07:41:25 PM PDT 24 1427549491 ps
T5 /workspace/coverage/default/18.sram_ctrl_executable.2170208517 Jul 29 07:37:36 PM PDT 24 Jul 29 08:00:06 PM PDT 24 69563692405 ps
T8 /workspace/coverage/default/33.sram_ctrl_mem_walk.1278521116 Jul 29 07:38:34 PM PDT 24 Jul 29 07:38:44 PM PDT 24 2578163500 ps
T9 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1633104956 Jul 29 07:39:35 PM PDT 24 Jul 29 07:42:54 PM PDT 24 3452502393 ps
T10 /workspace/coverage/default/3.sram_ctrl_alert_test.1016777416 Jul 29 07:37:01 PM PDT 24 Jul 29 07:37:02 PM PDT 24 16752178 ps
T11 /workspace/coverage/default/5.sram_ctrl_executable.2876356671 Jul 29 07:37:00 PM PDT 24 Jul 29 07:48:56 PM PDT 24 35079486359 ps
T12 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.87137703 Jul 29 07:37:01 PM PDT 24 Jul 29 07:41:22 PM PDT 24 2983119145 ps
T35 /workspace/coverage/default/15.sram_ctrl_smoke.3118367827 Jul 29 07:37:13 PM PDT 24 Jul 29 07:38:18 PM PDT 24 289937860 ps
T36 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.81477122 Jul 29 07:39:58 PM PDT 24 Jul 29 07:40:02 PM PDT 24 211821642 ps
T37 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1396786060 Jul 29 07:36:47 PM PDT 24 Jul 29 07:36:54 PM PDT 24 206985883 ps
T46 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1967572814 Jul 29 07:37:41 PM PDT 24 Jul 29 07:37:43 PM PDT 24 278763461 ps
T49 /workspace/coverage/default/30.sram_ctrl_partial_access.482757030 Jul 29 07:38:15 PM PDT 24 Jul 29 07:38:27 PM PDT 24 1582304918 ps
T18 /workspace/coverage/default/35.sram_ctrl_regwen.2556671977 Jul 29 07:38:39 PM PDT 24 Jul 29 07:46:14 PM PDT 24 8166675139 ps
T6 /workspace/coverage/default/13.sram_ctrl_lc_escalation.1765303764 Jul 29 07:37:09 PM PDT 24 Jul 29 07:37:14 PM PDT 24 509786804 ps
T54 /workspace/coverage/default/42.sram_ctrl_max_throughput.2128671951 Jul 29 07:39:06 PM PDT 24 Jul 29 07:41:29 PM PDT 24 272699542 ps
T55 /workspace/coverage/default/32.sram_ctrl_max_throughput.4136306264 Jul 29 07:38:21 PM PDT 24 Jul 29 07:38:35 PM PDT 24 226340524 ps
T82 /workspace/coverage/default/13.sram_ctrl_smoke.2221395730 Jul 29 07:37:15 PM PDT 24 Jul 29 07:37:50 PM PDT 24 1273560438 ps
T19 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1357946709 Jul 29 07:37:45 PM PDT 24 Jul 29 07:47:09 PM PDT 24 6409758008 ps
T59 /workspace/coverage/default/25.sram_ctrl_regwen.1679324068 Jul 29 07:37:55 PM PDT 24 Jul 29 07:55:08 PM PDT 24 50454752684 ps
T79 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3957521096 Jul 29 07:37:06 PM PDT 24 Jul 29 07:42:37 PM PDT 24 14165006868 ps
T148 /workspace/coverage/default/18.sram_ctrl_max_throughput.3400996479 Jul 29 07:37:28 PM PDT 24 Jul 29 07:37:30 PM PDT 24 48637777 ps
T22 /workspace/coverage/default/32.sram_ctrl_ram_cfg.1763996729 Jul 29 07:38:23 PM PDT 24 Jul 29 07:38:24 PM PDT 24 39768385 ps
T107 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1054816769 Jul 29 07:36:50 PM PDT 24 Jul 29 07:43:25 PM PDT 24 17152293910 ps
T149 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1840288278 Jul 29 07:37:14 PM PDT 24 Jul 29 07:37:21 PM PDT 24 192316521 ps
T47 /workspace/coverage/default/31.sram_ctrl_mem_walk.3009745496 Jul 29 07:38:24 PM PDT 24 Jul 29 07:38:31 PM PDT 24 4494138685 ps
T150 /workspace/coverage/default/22.sram_ctrl_max_throughput.4009170955 Jul 29 07:37:39 PM PDT 24 Jul 29 07:39:14 PM PDT 24 237016068 ps
T21 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3374682811 Jul 29 07:36:49 PM PDT 24 Jul 29 07:45:40 PM PDT 24 4045787714 ps
T147 /workspace/coverage/default/28.sram_ctrl_max_throughput.758277571 Jul 29 07:37:56 PM PDT 24 Jul 29 07:39:18 PM PDT 24 442984171 ps
T80 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.4003953019 Jul 29 07:38:23 PM PDT 24 Jul 29 07:38:26 PM PDT 24 250937778 ps
T81 /workspace/coverage/default/19.sram_ctrl_smoke.1880249808 Jul 29 07:37:40 PM PDT 24 Jul 29 07:37:42 PM PDT 24 104199274 ps
T108 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3607526475 Jul 29 07:38:34 PM PDT 24 Jul 29 07:42:00 PM PDT 24 15280671807 ps
T151 /workspace/coverage/default/34.sram_ctrl_multiple_keys.4283764701 Jul 29 07:38:30 PM PDT 24 Jul 29 07:45:28 PM PDT 24 9944020671 ps
T23 /workspace/coverage/default/38.sram_ctrl_ram_cfg.1022921703 Jul 29 07:38:50 PM PDT 24 Jul 29 07:38:50 PM PDT 24 181796233 ps
T152 /workspace/coverage/default/28.sram_ctrl_ram_cfg.2174427126 Jul 29 07:37:52 PM PDT 24 Jul 29 07:37:53 PM PDT 24 41999537 ps
T153 /workspace/coverage/default/33.sram_ctrl_partial_access.2012649359 Jul 29 07:38:31 PM PDT 24 Jul 29 07:38:44 PM PDT 24 10492792655 ps
T109 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2681063756 Jul 29 07:37:42 PM PDT 24 Jul 29 07:43:49 PM PDT 24 8308464536 ps
T7 /workspace/coverage/default/41.sram_ctrl_lc_escalation.3402980889 Jul 29 07:39:05 PM PDT 24 Jul 29 07:39:11 PM PDT 24 529786758 ps
T154 /workspace/coverage/default/10.sram_ctrl_partial_access.3636848966 Jul 29 07:37:06 PM PDT 24 Jul 29 07:39:32 PM PDT 24 420079496 ps
T138 /workspace/coverage/default/27.sram_ctrl_executable.2343802962 Jul 29 07:37:52 PM PDT 24 Jul 29 07:39:34 PM PDT 24 1599265833 ps
T61 /workspace/coverage/default/46.sram_ctrl_lc_escalation.3156203526 Jul 29 07:39:37 PM PDT 24 Jul 29 07:39:43 PM PDT 24 1787866362 ps
T155 /workspace/coverage/default/22.sram_ctrl_executable.949156412 Jul 29 07:37:43 PM PDT 24 Jul 29 07:38:56 PM PDT 24 1527895035 ps
T38 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1231473458 Jul 29 07:38:36 PM PDT 24 Jul 29 08:01:32 PM PDT 24 78286731100 ps
T45 /workspace/coverage/default/11.sram_ctrl_mem_walk.1030172721 Jul 29 07:37:09 PM PDT 24 Jul 29 07:37:20 PM PDT 24 3369837316 ps
T62 /workspace/coverage/default/6.sram_ctrl_regwen.499618365 Jul 29 07:37:00 PM PDT 24 Jul 29 07:43:36 PM PDT 24 10941842975 ps
T144 /workspace/coverage/default/14.sram_ctrl_ram_cfg.3350307677 Jul 29 07:37:14 PM PDT 24 Jul 29 07:37:15 PM PDT 24 43952538 ps
T156 /workspace/coverage/default/21.sram_ctrl_mem_walk.517391678 Jul 29 07:37:38 PM PDT 24 Jul 29 07:37:42 PM PDT 24 357476914 ps
T110 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1397465487 Jul 29 07:37:43 PM PDT 24 Jul 29 07:44:30 PM PDT 24 15635666212 ps
T43 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1836164480 Jul 29 07:36:50 PM PDT 24 Jul 29 07:36:55 PM PDT 24 961476184 ps
T119 /workspace/coverage/default/29.sram_ctrl_partial_access.595106107 Jul 29 07:38:15 PM PDT 24 Jul 29 07:38:19 PM PDT 24 1590920773 ps
T120 /workspace/coverage/default/18.sram_ctrl_bijection.2474306465 Jul 29 07:37:26 PM PDT 24 Jul 29 07:38:46 PM PDT 24 3735106180 ps
T13 /workspace/coverage/default/38.sram_ctrl_alert_test.2540096927 Jul 29 07:38:48 PM PDT 24 Jul 29 07:38:49 PM PDT 24 21669565 ps
T121 /workspace/coverage/default/6.sram_ctrl_max_throughput.2874743115 Jul 29 07:37:07 PM PDT 24 Jul 29 07:39:03 PM PDT 24 131570717 ps
T14 /workspace/coverage/default/43.sram_ctrl_alert_test.817792593 Jul 29 07:39:26 PM PDT 24 Jul 29 07:39:27 PM PDT 24 136829456 ps
T44 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1620072208 Jul 29 07:37:05 PM PDT 24 Jul 29 07:37:08 PM PDT 24 125037215 ps
T48 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2088043979 Jul 29 07:37:46 PM PDT 24 Jul 29 07:37:51 PM PDT 24 369007691 ps
T122 /workspace/coverage/default/16.sram_ctrl_ram_cfg.2685454903 Jul 29 07:37:36 PM PDT 24 Jul 29 07:37:37 PM PDT 24 57451624 ps
T50 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.4179447410 Jul 29 07:37:49 PM PDT 24 Jul 29 07:37:53 PM PDT 24 113236517 ps
T39 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.773599695 Jul 29 07:36:49 PM PDT 24 Jul 29 07:52:36 PM PDT 24 14366140118 ps
T157 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1126094493 Jul 29 07:36:46 PM PDT 24 Jul 29 07:42:29 PM PDT 24 13983321100 ps
T158 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.144790066 Jul 29 07:37:13 PM PDT 24 Jul 29 07:37:53 PM PDT 24 213401075 ps
T159 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.501306956 Jul 29 07:38:40 PM PDT 24 Jul 29 07:40:50 PM PDT 24 6704548476 ps
T160 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3474085571 Jul 29 07:37:30 PM PDT 24 Jul 29 07:46:03 PM PDT 24 15375222968 ps
T68 /workspace/coverage/default/49.sram_ctrl_regwen.4055907858 Jul 29 07:39:58 PM PDT 24 Jul 29 07:55:38 PM PDT 24 170135838377 ps
T161 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2332401555 Jul 29 07:38:22 PM PDT 24 Jul 29 07:39:38 PM PDT 24 128490710 ps
T20 /workspace/coverage/default/36.sram_ctrl_lc_escalation.2447545684 Jul 29 07:38:34 PM PDT 24 Jul 29 07:38:42 PM PDT 24 1967465234 ps
T162 /workspace/coverage/default/30.sram_ctrl_multiple_keys.94219208 Jul 29 07:38:15 PM PDT 24 Jul 29 07:58:19 PM PDT 24 41339868848 ps
T163 /workspace/coverage/default/35.sram_ctrl_executable.2886414415 Jul 29 07:38:36 PM PDT 24 Jul 29 07:55:26 PM PDT 24 5738777195 ps
T164 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3665433527 Jul 29 07:37:45 PM PDT 24 Jul 29 07:43:40 PM PDT 24 9471713868 ps
T40 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3900463990 Jul 29 07:36:59 PM PDT 24 Jul 29 07:47:09 PM PDT 24 14326496831 ps
T165 /workspace/coverage/default/46.sram_ctrl_partial_access.3343664568 Jul 29 07:39:37 PM PDT 24 Jul 29 07:39:38 PM PDT 24 167071176 ps
T166 /workspace/coverage/default/25.sram_ctrl_ram_cfg.3920867779 Jul 29 07:37:43 PM PDT 24 Jul 29 07:37:43 PM PDT 24 30230653 ps
T142 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2629135230 Jul 29 07:36:55 PM PDT 24 Jul 29 07:39:15 PM PDT 24 5641323363 ps
T141 /workspace/coverage/default/26.sram_ctrl_executable.1074417422 Jul 29 07:37:48 PM PDT 24 Jul 29 07:53:13 PM PDT 24 11461881296 ps
T146 /workspace/coverage/default/16.sram_ctrl_executable.2642385805 Jul 29 07:37:21 PM PDT 24 Jul 29 07:40:58 PM PDT 24 8157634999 ps
T167 /workspace/coverage/default/12.sram_ctrl_bijection.1004543029 Jul 29 07:37:02 PM PDT 24 Jul 29 07:37:52 PM PDT 24 8745841597 ps
T89 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3268634909 Jul 29 07:39:46 PM PDT 24 Jul 29 07:47:02 PM PDT 24 4225957217 ps
T145 /workspace/coverage/default/45.sram_ctrl_executable.2373646671 Jul 29 07:39:36 PM PDT 24 Jul 29 07:46:55 PM PDT 24 2234728205 ps
T143 /workspace/coverage/default/36.sram_ctrl_bijection.3837051111 Jul 29 07:38:37 PM PDT 24 Jul 29 07:39:54 PM PDT 24 9951945117 ps
T90 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2418678549 Jul 29 07:39:03 PM PDT 24 Jul 29 07:39:06 PM PDT 24 387909371 ps
T51 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3204616010 Jul 29 07:37:07 PM PDT 24 Jul 29 07:37:13 PM PDT 24 218942728 ps
T168 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.4041390165 Jul 29 07:39:36 PM PDT 24 Jul 29 07:39:39 PM PDT 24 454414766 ps
T169 /workspace/coverage/default/0.sram_ctrl_partial_access.103245585 Jul 29 07:36:47 PM PDT 24 Jul 29 07:37:56 PM PDT 24 1113065905 ps
T69 /workspace/coverage/default/24.sram_ctrl_regwen.3650069136 Jul 29 07:37:43 PM PDT 24 Jul 29 07:54:41 PM PDT 24 4795658748 ps
T170 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2186778402 Jul 29 07:39:27 PM PDT 24 Jul 29 07:52:09 PM PDT 24 12958981549 ps
T136 /workspace/coverage/default/13.sram_ctrl_executable.2175650977 Jul 29 07:37:09 PM PDT 24 Jul 29 07:51:11 PM PDT 24 14598746641 ps
T171 /workspace/coverage/default/46.sram_ctrl_ram_cfg.3370599416 Jul 29 07:39:38 PM PDT 24 Jul 29 07:39:39 PM PDT 24 32186306 ps
T172 /workspace/coverage/default/16.sram_ctrl_mem_walk.1656420522 Jul 29 07:37:31 PM PDT 24 Jul 29 07:37:37 PM PDT 24 370919263 ps
T173 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1457318935 Jul 29 07:37:43 PM PDT 24 Jul 29 07:41:20 PM PDT 24 8799962406 ps
T174 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1156626620 Jul 29 07:39:58 PM PDT 24 Jul 29 07:43:48 PM PDT 24 2332072056 ps
T52 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.745538445 Jul 29 07:38:48 PM PDT 24 Jul 29 07:39:36 PM PDT 24 5508848127 ps
T175 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3730182960 Jul 29 07:37:04 PM PDT 24 Jul 29 07:44:35 PM PDT 24 6463396026 ps
T176 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1218396747 Jul 29 07:39:58 PM PDT 24 Jul 29 07:49:25 PM PDT 24 59380949538 ps
T53 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.760466090 Jul 29 07:37:39 PM PDT 24 Jul 29 07:37:44 PM PDT 24 185560952 ps
T177 /workspace/coverage/default/11.sram_ctrl_max_throughput.3706163205 Jul 29 07:37:08 PM PDT 24 Jul 29 07:37:20 PM PDT 24 116449594 ps
T178 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2880068150 Jul 29 07:39:57 PM PDT 24 Jul 29 07:42:35 PM PDT 24 157647878 ps
T179 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1307840669 Jul 29 07:37:39 PM PDT 24 Jul 29 07:45:34 PM PDT 24 6305699945 ps
T180 /workspace/coverage/default/14.sram_ctrl_bijection.3977171155 Jul 29 07:37:23 PM PDT 24 Jul 29 07:37:56 PM PDT 24 3936007260 ps
T139 /workspace/coverage/default/43.sram_ctrl_stress_all.3819377302 Jul 29 07:39:26 PM PDT 24 Jul 29 08:17:42 PM PDT 24 11558764383 ps
T181 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.4052836341 Jul 29 07:37:49 PM PDT 24 Jul 29 07:40:19 PM PDT 24 5898661470 ps
T182 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1653379583 Jul 29 07:37:53 PM PDT 24 Jul 29 07:44:16 PM PDT 24 5332555052 ps
T183 /workspace/coverage/default/28.sram_ctrl_partial_access.2048006127 Jul 29 07:37:53 PM PDT 24 Jul 29 07:37:57 PM PDT 24 454137641 ps
T184 /workspace/coverage/default/39.sram_ctrl_executable.4129772050 Jul 29 07:38:53 PM PDT 24 Jul 29 07:51:29 PM PDT 24 10610773933 ps
T185 /workspace/coverage/default/10.sram_ctrl_smoke.78199926 Jul 29 07:37:01 PM PDT 24 Jul 29 07:37:09 PM PDT 24 66243290 ps
T186 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2610879207 Jul 29 07:39:58 PM PDT 24 Jul 29 07:40:01 PM PDT 24 1272427578 ps
T63 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1711176376 Jul 29 07:37:36 PM PDT 24 Jul 29 07:40:17 PM PDT 24 4076805585 ps
T187 /workspace/coverage/default/1.sram_ctrl_stress_all.500625474 Jul 29 07:36:44 PM PDT 24 Jul 29 08:00:46 PM PDT 24 7143713363 ps
T188 /workspace/coverage/default/8.sram_ctrl_bijection.1901318243 Jul 29 07:37:03 PM PDT 24 Jul 29 07:38:11 PM PDT 24 2150058500 ps
T189 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2175674664 Jul 29 07:39:47 PM PDT 24 Jul 29 07:47:02 PM PDT 24 5835238290 ps
T190 /workspace/coverage/default/3.sram_ctrl_lc_escalation.1337869074 Jul 29 07:36:54 PM PDT 24 Jul 29 07:37:04 PM PDT 24 4841181451 ps
T191 /workspace/coverage/default/22.sram_ctrl_bijection.2452815626 Jul 29 07:37:46 PM PDT 24 Jul 29 07:39:22 PM PDT 24 34578711894 ps
T192 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2602965572 Jul 29 07:37:56 PM PDT 24 Jul 29 07:41:34 PM PDT 24 16135607887 ps
T193 /workspace/coverage/default/34.sram_ctrl_executable.1957224319 Jul 29 07:38:32 PM PDT 24 Jul 29 07:59:16 PM PDT 24 3173716442 ps
T194 /workspace/coverage/default/8.sram_ctrl_max_throughput.2403242215 Jul 29 07:37:11 PM PDT 24 Jul 29 07:38:29 PM PDT 24 416347093 ps
T195 /workspace/coverage/default/6.sram_ctrl_smoke.2109112857 Jul 29 07:37:00 PM PDT 24 Jul 29 07:37:41 PM PDT 24 1609925507 ps
T196 /workspace/coverage/default/27.sram_ctrl_alert_test.1614609189 Jul 29 07:37:56 PM PDT 24 Jul 29 07:37:57 PM PDT 24 16520963 ps
T197 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3983711889 Jul 29 07:38:30 PM PDT 24 Jul 29 07:51:20 PM PDT 24 9202172037 ps
T198 /workspace/coverage/default/40.sram_ctrl_partial_access.3659860780 Jul 29 07:39:00 PM PDT 24 Jul 29 07:39:03 PM PDT 24 394925057 ps
T199 /workspace/coverage/default/1.sram_ctrl_partial_access.3239090991 Jul 29 07:36:57 PM PDT 24 Jul 29 07:37:06 PM PDT 24 1640989455 ps
T200 /workspace/coverage/default/10.sram_ctrl_multiple_keys.2461147599 Jul 29 07:37:01 PM PDT 24 Jul 29 07:44:56 PM PDT 24 7552758413 ps
T201 /workspace/coverage/default/1.sram_ctrl_smoke.3426707610 Jul 29 07:36:48 PM PDT 24 Jul 29 07:38:52 PM PDT 24 752148411 ps
T202 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1149473097 Jul 29 07:39:26 PM PDT 24 Jul 29 07:39:29 PM PDT 24 118431756 ps
T203 /workspace/coverage/default/17.sram_ctrl_alert_test.556939988 Jul 29 07:37:35 PM PDT 24 Jul 29 07:37:36 PM PDT 24 60251683 ps
T64 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1702678877 Jul 29 07:36:48 PM PDT 24 Jul 29 07:40:04 PM PDT 24 863645827 ps
T204 /workspace/coverage/default/46.sram_ctrl_smoke.1939284909 Jul 29 07:39:37 PM PDT 24 Jul 29 07:39:54 PM PDT 24 792896827 ps
T205 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1900395177 Jul 29 07:36:58 PM PDT 24 Jul 29 07:39:01 PM PDT 24 6718076398 ps
T206 /workspace/coverage/default/9.sram_ctrl_mem_walk.3925211518 Jul 29 07:36:55 PM PDT 24 Jul 29 07:37:00 PM PDT 24 168359183 ps
T207 /workspace/coverage/default/3.sram_ctrl_ram_cfg.2601121372 Jul 29 07:37:00 PM PDT 24 Jul 29 07:37:00 PM PDT 24 30510600 ps
T208 /workspace/coverage/default/1.sram_ctrl_max_throughput.1701238958 Jul 29 07:36:45 PM PDT 24 Jul 29 07:37:32 PM PDT 24 107020809 ps
T65 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.337045749 Jul 29 07:39:59 PM PDT 24 Jul 29 07:40:28 PM PDT 24 3934121540 ps
T209 /workspace/coverage/default/14.sram_ctrl_multiple_keys.2423747428 Jul 29 07:37:23 PM PDT 24 Jul 29 07:55:44 PM PDT 24 73908057136 ps
T210 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.562428096 Jul 29 07:37:12 PM PDT 24 Jul 29 07:39:41 PM PDT 24 59443493197 ps
T211 /workspace/coverage/default/5.sram_ctrl_lc_escalation.877954396 Jul 29 07:36:48 PM PDT 24 Jul 29 07:36:54 PM PDT 24 4930380981 ps
T212 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2569194742 Jul 29 07:36:54 PM PDT 24 Jul 29 07:38:29 PM PDT 24 4099995375 ps
T213 /workspace/coverage/default/22.sram_ctrl_mem_walk.2614515063 Jul 29 07:37:44 PM PDT 24 Jul 29 07:37:49 PM PDT 24 243982423 ps
T214 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.682715061 Jul 29 07:38:44 PM PDT 24 Jul 29 07:38:50 PM PDT 24 637368742 ps
T215 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2008611902 Jul 29 07:38:53 PM PDT 24 Jul 29 07:38:59 PM PDT 24 172562394 ps
T216 /workspace/coverage/default/20.sram_ctrl_ram_cfg.1448149300 Jul 29 07:37:32 PM PDT 24 Jul 29 07:37:32 PM PDT 24 77116938 ps
T217 /workspace/coverage/default/43.sram_ctrl_max_throughput.1476668613 Jul 29 07:39:16 PM PDT 24 Jul 29 07:39:18 PM PDT 24 46309786 ps
T218 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3309833681 Jul 29 07:39:04 PM PDT 24 Jul 29 07:39:41 PM PDT 24 374247844 ps
T137 /workspace/coverage/default/10.sram_ctrl_executable.954307081 Jul 29 07:37:02 PM PDT 24 Jul 29 07:56:36 PM PDT 24 5223025433 ps
T219 /workspace/coverage/default/39.sram_ctrl_alert_test.2162031728 Jul 29 07:38:52 PM PDT 24 Jul 29 07:38:53 PM PDT 24 14722376 ps
T220 /workspace/coverage/default/26.sram_ctrl_alert_test.1426489602 Jul 29 07:37:55 PM PDT 24 Jul 29 07:37:56 PM PDT 24 40433504 ps
T221 /workspace/coverage/default/7.sram_ctrl_smoke.1509158402 Jul 29 07:37:01 PM PDT 24 Jul 29 07:38:00 PM PDT 24 212375085 ps
T222 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1029659549 Jul 29 07:39:52 PM PDT 24 Jul 29 07:43:47 PM PDT 24 4833243863 ps
T223 /workspace/coverage/default/34.sram_ctrl_max_throughput.3706754425 Jul 29 07:38:34 PM PDT 24 Jul 29 07:40:10 PM PDT 24 785462325 ps
T224 /workspace/coverage/default/27.sram_ctrl_partial_access.1787893505 Jul 29 07:37:53 PM PDT 24 Jul 29 07:38:00 PM PDT 24 1331182120 ps
T225 /workspace/coverage/default/4.sram_ctrl_ram_cfg.2205710047 Jul 29 07:36:59 PM PDT 24 Jul 29 07:37:00 PM PDT 24 32285164 ps
T226 /workspace/coverage/default/19.sram_ctrl_multiple_keys.193586342 Jul 29 07:37:41 PM PDT 24 Jul 29 07:43:25 PM PDT 24 1402976966 ps
T227 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2000985505 Jul 29 07:37:26 PM PDT 24 Jul 29 07:43:46 PM PDT 24 1770327840 ps
T228 /workspace/coverage/default/43.sram_ctrl_partial_access.3143404270 Jul 29 07:39:16 PM PDT 24 Jul 29 07:39:17 PM PDT 24 39455080 ps
T229 /workspace/coverage/default/3.sram_ctrl_max_throughput.4211262321 Jul 29 07:36:46 PM PDT 24 Jul 29 07:36:48 PM PDT 24 43194107 ps
T230 /workspace/coverage/default/47.sram_ctrl_partial_access.3085376859 Jul 29 07:39:48 PM PDT 24 Jul 29 07:42:32 PM PDT 24 750917521 ps
T231 /workspace/coverage/default/35.sram_ctrl_bijection.1004589046 Jul 29 07:38:30 PM PDT 24 Jul 29 07:39:22 PM PDT 24 3185439287 ps
T232 /workspace/coverage/default/48.sram_ctrl_lc_escalation.1281159499 Jul 29 07:39:47 PM PDT 24 Jul 29 07:39:53 PM PDT 24 1509894517 ps
T233 /workspace/coverage/default/49.sram_ctrl_executable.3391159960 Jul 29 07:39:58 PM PDT 24 Jul 29 07:58:03 PM PDT 24 9322159374 ps
T234 /workspace/coverage/default/8.sram_ctrl_stress_all.298479733 Jul 29 07:36:59 PM PDT 24 Jul 29 07:48:48 PM PDT 24 48559819624 ps
T235 /workspace/coverage/default/31.sram_ctrl_ram_cfg.1246799890 Jul 29 07:38:23 PM PDT 24 Jul 29 07:38:24 PM PDT 24 46671160 ps
T236 /workspace/coverage/default/27.sram_ctrl_smoke.2333048637 Jul 29 07:37:56 PM PDT 24 Jul 29 07:38:01 PM PDT 24 410025314 ps
T237 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1635102102 Jul 29 07:36:48 PM PDT 24 Jul 29 07:37:56 PM PDT 24 122650796 ps
T66 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2469838361 Jul 29 07:38:54 PM PDT 24 Jul 29 07:39:22 PM PDT 24 10356898140 ps
T67 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2090305621 Jul 29 07:37:58 PM PDT 24 Jul 29 07:46:03 PM PDT 24 4469104150 ps
T238 /workspace/coverage/default/23.sram_ctrl_alert_test.3473052361 Jul 29 07:37:48 PM PDT 24 Jul 29 07:37:49 PM PDT 24 13318853 ps
T239 /workspace/coverage/default/0.sram_ctrl_max_throughput.4187433946 Jul 29 07:36:48 PM PDT 24 Jul 29 07:37:13 PM PDT 24 377923613 ps
T240 /workspace/coverage/default/21.sram_ctrl_multiple_keys.3005037251 Jul 29 07:37:42 PM PDT 24 Jul 29 07:54:32 PM PDT 24 50884857240 ps
T140 /workspace/coverage/default/40.sram_ctrl_stress_all.2711692406 Jul 29 07:39:00 PM PDT 24 Jul 29 08:48:39 PM PDT 24 53768508313 ps
T241 /workspace/coverage/default/6.sram_ctrl_bijection.3271768897 Jul 29 07:36:55 PM PDT 24 Jul 29 07:37:18 PM PDT 24 571779627 ps
T242 /workspace/coverage/default/35.sram_ctrl_lc_escalation.2411214288 Jul 29 07:38:38 PM PDT 24 Jul 29 07:38:39 PM PDT 24 470471266 ps
T243 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4245611189 Jul 29 07:39:58 PM PDT 24 Jul 29 07:43:34 PM PDT 24 3089268921 ps
T244 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2729273901 Jul 29 07:37:25 PM PDT 24 Jul 29 07:39:00 PM PDT 24 299928414 ps
T245 /workspace/coverage/default/6.sram_ctrl_mem_walk.3150362297 Jul 29 07:36:48 PM PDT 24 Jul 29 07:37:00 PM PDT 24 4673890187 ps
T246 /workspace/coverage/default/21.sram_ctrl_ram_cfg.2206429679 Jul 29 07:37:43 PM PDT 24 Jul 29 07:37:44 PM PDT 24 30850102 ps
T247 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3584203592 Jul 29 07:36:46 PM PDT 24 Jul 29 07:38:25 PM PDT 24 140023756 ps
T248 /workspace/coverage/default/39.sram_ctrl_smoke.2607079651 Jul 29 07:38:50 PM PDT 24 Jul 29 07:39:02 PM PDT 24 523777385 ps
T249 /workspace/coverage/default/38.sram_ctrl_smoke.450265446 Jul 29 07:38:43 PM PDT 24 Jul 29 07:38:48 PM PDT 24 364291510 ps
T250 /workspace/coverage/default/0.sram_ctrl_lc_escalation.2544052692 Jul 29 07:36:43 PM PDT 24 Jul 29 07:36:50 PM PDT 24 528541542 ps
T251 /workspace/coverage/default/29.sram_ctrl_mem_walk.336481562 Jul 29 07:38:13 PM PDT 24 Jul 29 07:38:25 PM PDT 24 2741929413 ps
T252 /workspace/coverage/default/32.sram_ctrl_partial_access.937295312 Jul 29 07:38:23 PM PDT 24 Jul 29 07:38:28 PM PDT 24 1537622856 ps
T253 /workspace/coverage/default/29.sram_ctrl_executable.2783495408 Jul 29 07:38:14 PM PDT 24 Jul 29 07:59:07 PM PDT 24 3092027136 ps
T254 /workspace/coverage/default/44.sram_ctrl_lc_escalation.1875005142 Jul 29 07:39:27 PM PDT 24 Jul 29 07:39:36 PM PDT 24 3243018044 ps
T255 /workspace/coverage/default/16.sram_ctrl_lc_escalation.1230963140 Jul 29 07:37:33 PM PDT 24 Jul 29 07:37:39 PM PDT 24 420446875 ps
T256 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1555183398 Jul 29 07:38:39 PM PDT 24 Jul 29 07:42:03 PM PDT 24 7685040191 ps
T257 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3158697905 Jul 29 07:38:12 PM PDT 24 Jul 29 07:41:23 PM PDT 24 9017101021 ps
T258 /workspace/coverage/default/3.sram_ctrl_partial_access.3507984840 Jul 29 07:37:01 PM PDT 24 Jul 29 07:37:21 PM PDT 24 111357154 ps
T259 /workspace/coverage/default/46.sram_ctrl_mem_walk.2748071881 Jul 29 07:39:37 PM PDT 24 Jul 29 07:39:46 PM PDT 24 547971978 ps
T260 /workspace/coverage/default/21.sram_ctrl_smoke.90856910 Jul 29 07:37:49 PM PDT 24 Jul 29 07:38:00 PM PDT 24 769140157 ps
T261 /workspace/coverage/default/7.sram_ctrl_ram_cfg.113881836 Jul 29 07:36:55 PM PDT 24 Jul 29 07:36:55 PM PDT 24 91684248 ps
T262 /workspace/coverage/default/4.sram_ctrl_regwen.581027376 Jul 29 07:36:48 PM PDT 24 Jul 29 07:51:10 PM PDT 24 13028174884 ps
T263 /workspace/coverage/default/43.sram_ctrl_smoke.3639109241 Jul 29 07:39:14 PM PDT 24 Jul 29 07:39:24 PM PDT 24 1578685576 ps
T264 /workspace/coverage/default/28.sram_ctrl_lc_escalation.4164057803 Jul 29 07:38:00 PM PDT 24 Jul 29 07:38:06 PM PDT 24 550249382 ps
T265 /workspace/coverage/default/17.sram_ctrl_smoke.3794617097 Jul 29 07:37:37 PM PDT 24 Jul 29 07:37:56 PM PDT 24 3811599286 ps
T266 /workspace/coverage/default/12.sram_ctrl_partial_access.2089152891 Jul 29 07:37:14 PM PDT 24 Jul 29 07:39:28 PM PDT 24 651182725 ps
T267 /workspace/coverage/default/44.sram_ctrl_mem_walk.309495349 Jul 29 07:39:27 PM PDT 24 Jul 29 07:39:33 PM PDT 24 949031388 ps
T268 /workspace/coverage/default/18.sram_ctrl_multiple_keys.1234736407 Jul 29 07:37:35 PM PDT 24 Jul 29 07:48:30 PM PDT 24 3480711649 ps
T269 /workspace/coverage/default/48.sram_ctrl_regwen.741101576 Jul 29 07:39:48 PM PDT 24 Jul 29 07:55:47 PM PDT 24 38797250583 ps
T270 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3857083379 Jul 29 07:39:48 PM PDT 24 Jul 29 07:44:04 PM PDT 24 10562345634 ps
T271 /workspace/coverage/default/46.sram_ctrl_regwen.2845551531 Jul 29 07:39:38 PM PDT 24 Jul 29 08:00:49 PM PDT 24 3058884616 ps
T272 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2718523863 Jul 29 07:38:21 PM PDT 24 Jul 29 07:42:15 PM PDT 24 2762521315 ps
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