Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44247457	1			T1	384		T2	9768		T4	103699
triple_byte_access	2510353	1			T1	11		T4	1984		T5	1972
halfword_access	3767694	1			T1	15		T4	3103		T5	3019
byte_access	5033752	1			T1	22		T4	4107		T5	3871
zero_access	1266544	1			T1	2		T4	1045		T5	968

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28357061

1

T1

237

T2

4884

T4

56881

auto[1]

28468739

1

T1

197

T2

4884

T4

57057

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22075898	1			T1	210		T2	4884		T4	51799
auto[0]	triple_byte_access	1251861	1			T1	4		T4	1024		T5	972
auto[0]	halfword_access	1877751	1			T1	9		T4	1558		T5	1514
auto[0]	byte_access	2514670	1			T1	13		T4	2027		T5	1891
auto[0]	zero_access	636881	1			T1	1		T4	473		T5	504
auto[1]	word_access	22171559	1			T1	174		T2	4884		T4	51900
auto[1]	triple_byte_access	1258492	1			T1	7		T4	960		T5	1000
auto[1]	halfword_access	1889943	1			T1	6		T4	1545		T5	1505
auto[1]	byte_access	2519082	1			T1	9		T4	2080		T5	1980
auto[1]	zero_access	629663	1			T1	1		T4	572		T5	464