Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	150336214	1			T1	6142		T2	20092		T3	1472
instr_valid_dis	112177473	1			T1	6142		T2	20092		T3	1472
instr_en	24600697	1			T20	50759		T19	168216		T21	123966

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11912598	1			T27	32924		T26	12834		T20	5834
sram_ifetch_valid_disable	113813685	1			T1	6142		T2	20092		T3	1472
sram_ifetch_enable	24609931	1			T27	46658		T20	18129		T19	362356

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	150336214	1			T1	6142		T2	20092		T3	1472
hw_debug_en_valid_off	114903403	1			T1	6142		T2	20092		T3	1472
hw_debug_en_on	23866229	1			T20	100508		T19	359616		T21	54474

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113813685	1			T1	6142		T2	20092		T3	1472
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97838486	1			T1	6142		T2	20092		T3	1472
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9700335	1			T20	41077		T19	87880		T21	37448
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5311096	1			T27	32924		T26	12834		T20	1178
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2091500	1			T26	12834		T19	10240		T40	93764
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2190578	1			T20	1178		T21	27594		T40	4912
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4086134	1			T20	4656		T19	15118		T21	11902
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1861646	1			T38	60636		T40	27622		T44	11404
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1436534	1			T20	4656		T19	15118		T44	42442
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9998227	1			T20	92004		T19	141672		T38	51024
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3690930	1			T20	4004		T19	129230		T40	171148
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4024482	1			T20	16818		T19	12442		T38	26152

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10335552	1			T20	3848		T19	65218		T21	58924
lc_exec_en	9781868	1			T20	3848		T19	202826		T21	42572
valid_exec_dis	108769465	1			T1	6142		T2	20092		T3	1472
invalid_exec_dis	36522529	1			T27	79582		T26	12834		T20	23963