Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Total tests in report: 1031

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
81.22	81.22	96.02	96.02	81.99	81.99	94.69	94.69	71.43	71.43	87.44	87.44	95.13	95.13	41.86	41.86	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1555058659
87.73	6.50	97.03	1.02	82.46	0.47	96.36	1.66	90.48	19.05	89.13	1.69	95.72	0.59	62.89	21.02	/workspace/coverage/default/2.sram_ctrl_mem_walk.3769703051
92.72	4.99	98.47	1.44	87.20	4.74	97.75	1.39	100.00	9.52	93.48	4.35	95.87	0.15	76.23	13.35	/workspace/coverage/default/13.sram_ctrl_stress_all.3927147082
93.75	1.03	98.64	0.17	88.03	0.83	97.95	0.21	100.00	0.00	94.20	0.72	95.87	0.00	81.54	5.30	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.421119804
94.74	0.99	98.64	0.00	88.15	0.12	97.95	0.00	100.00	0.00	94.44	0.24	95.87	0.00	88.12	6.58	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.804131717
95.45	0.71	98.81	0.17	89.93	1.78	98.72	0.76	100.00	0.00	95.17	0.72	96.46	0.59	89.03	0.91	/workspace/coverage/default/3.sram_ctrl_sec_cm.1984890944
96.09	0.64	99.07	0.25	89.93	0.00	98.75	0.03	100.00	0.00	95.41	0.24	96.76	0.29	92.69	3.66	/workspace/coverage/default/12.sram_ctrl_partial_access.1535218193
96.47	0.38	99.07	0.00	90.52	0.59	98.75	0.00	100.00	0.00	95.65	0.24	96.76	0.00	94.52	1.83	/workspace/coverage/default/0.sram_ctrl_stress_all.2881305014
96.64	0.18	99.07	0.00	90.52	0.00	98.82	0.07	100.00	0.00	95.65	0.00	97.94	1.18	94.52	0.00	/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.747308985
96.80	0.16	99.07	0.00	90.52	0.00	98.82	0.00	100.00	0.00	95.65	0.00	97.94	0.00	95.61	1.10	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1564875126
96.95	0.15	99.07	0.00	90.52	0.00	98.82	0.00	100.00	0.00	95.65	0.00	98.97	1.03	95.61	0.00	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1948761535
97.08	0.13	99.15	0.08	90.52	0.00	99.65	0.83	100.00	0.00	95.65	0.00	98.97	0.00	95.61	0.00	/workspace/coverage/default/14.sram_ctrl_ram_cfg.4260411148
97.18	0.10	99.15	0.00	90.52	0.00	99.65	0.00	100.00	0.00	95.65	0.00	98.97	0.00	96.34	0.73	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1336343795
97.29	0.10	99.15	0.00	90.52	0.00	99.65	0.00	100.00	0.00	95.65	0.00	98.97	0.00	97.07	0.73	/workspace/coverage/default/21.sram_ctrl_stress_all.3015458063
97.37	0.09	99.15	0.00	90.64	0.12	99.65	0.00	100.00	0.00	96.14	0.48	98.97	0.00	97.07	0.00	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2806255142
97.44	0.06	99.15	0.00	91.00	0.36	99.72	0.07	100.00	0.00	96.14	0.00	98.97	0.00	97.07	0.00	/workspace/coverage/default/18.sram_ctrl_alert_test.415556899
97.46	0.03	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	98.97	0.00	97.26	0.18	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.56665386
97.49	0.03	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	98.97	0.00	97.44	0.18	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2556775288
97.51	0.02	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	99.12	0.15	97.44	0.00	/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.333676055

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3030881750
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1735334846
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.683946462
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3843914978
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3570395910
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1898196740
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4122983399
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3027909824
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1854122711
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2326418851
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3093892045
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1666332287
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.660461586
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4174853567
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1853700729
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2291888304
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3149949619
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4279559305
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.187192106
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3196222869
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1496320906
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4157180587
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.494049153
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.550644168
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2364223556
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2880137709
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1267282652
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.495336199
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3355708823
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3965653002
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2721222097
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3469474583
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1591109843
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1000450540
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3016543505
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.850508813
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1287843990
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.265261711
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1319261965
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1161029550
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.314138177
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1482941403
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1376604451
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3027834162
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2787219299
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.543523357
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1198771140
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3977424401
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3448801249
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.23181918
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2468933545
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4063874099
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2106889102
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.946619645
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1774549961
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2675862872
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1878206122
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2104630209
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3295195308
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3177015474
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2821683348
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1503232762
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3993780115
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3269929937
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.821511125
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.808219724
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3225743232
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3245634769
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1369815797
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.533285811
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3883618578
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2445392695
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3195299798
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1665851655
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2263407972
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.785941780
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4059077407
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1399363818
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1945665838
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3056151318
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4220613619
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.900260014
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3747943056
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3998753992
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.340759921
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2828958198
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1579949123
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3368131005
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.701713954
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.688286004
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2781354715
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3184156833
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3654263313
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3030571973
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3100422569
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3024338505
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.695909409
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1318158542
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2447156762
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3636827508
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1135070580
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1387100764
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3379844487
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.569087161
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.352238324
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2215247293
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.253890309
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2042324626
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3005323116
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2495278978
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1722840948
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.39357650
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2383108422
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.246307656
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1229308897
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1943360232
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3066219934
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1232208738
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2007907877
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4203499054
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2271568576
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2176511819
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1105018294
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2549010388
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3252124575
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1717499045
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3492892709
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4089300865
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3883199913
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1119696105
/workspace/coverage/default/0.sram_ctrl_alert_test.1269511737
/workspace/coverage/default/0.sram_ctrl_bijection.2407818228
/workspace/coverage/default/0.sram_ctrl_executable.3629215019
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2790580996
/workspace/coverage/default/0.sram_ctrl_max_throughput.2805630329
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1047706991
/workspace/coverage/default/0.sram_ctrl_mem_walk.894354522
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2386194598
/workspace/coverage/default/0.sram_ctrl_partial_access.115987890
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2877082417
/workspace/coverage/default/0.sram_ctrl_ram_cfg.320223851
/workspace/coverage/default/0.sram_ctrl_regwen.1541685951
/workspace/coverage/default/0.sram_ctrl_sec_cm.1628425277
/workspace/coverage/default/0.sram_ctrl_smoke.776610418
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.503392007
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2587724871
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4288605302
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3035162029
/workspace/coverage/default/1.sram_ctrl_alert_test.2823052149
/workspace/coverage/default/1.sram_ctrl_bijection.541196825
/workspace/coverage/default/1.sram_ctrl_executable.893292216
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3255965992
/workspace/coverage/default/1.sram_ctrl_max_throughput.3277802775
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.35586377
/workspace/coverage/default/1.sram_ctrl_mem_walk.3233168939
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1165491020
/workspace/coverage/default/1.sram_ctrl_partial_access.455794700
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2851465308
/workspace/coverage/default/1.sram_ctrl_ram_cfg.45076787
/workspace/coverage/default/1.sram_ctrl_regwen.3774438968
/workspace/coverage/default/1.sram_ctrl_sec_cm.1481878350
/workspace/coverage/default/1.sram_ctrl_smoke.3620409118
/workspace/coverage/default/1.sram_ctrl_stress_all.1364052
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3120681340
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.840673628
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3629370490
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1136744247
/workspace/coverage/default/10.sram_ctrl_alert_test.2059723722
/workspace/coverage/default/10.sram_ctrl_bijection.3019006373
/workspace/coverage/default/10.sram_ctrl_executable.733968094
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3381398021
/workspace/coverage/default/10.sram_ctrl_max_throughput.3285794938
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2212772946
/workspace/coverage/default/10.sram_ctrl_mem_walk.3751527918
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3805438852
/workspace/coverage/default/10.sram_ctrl_partial_access.774238608
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1968932820
/workspace/coverage/default/10.sram_ctrl_ram_cfg.887947601
/workspace/coverage/default/10.sram_ctrl_regwen.2995781846
/workspace/coverage/default/10.sram_ctrl_smoke.1875977070
/workspace/coverage/default/10.sram_ctrl_stress_all.388963022
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4231344203
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2985233409
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2265567488
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.350858218
/workspace/coverage/default/11.sram_ctrl_alert_test.2798833834
/workspace/coverage/default/11.sram_ctrl_bijection.2095531732
/workspace/coverage/default/11.sram_ctrl_executable.2981472424
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2931671345
/workspace/coverage/default/11.sram_ctrl_max_throughput.103372129
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1512540340
/workspace/coverage/default/11.sram_ctrl_mem_walk.1815857247
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1881174303
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/workspace/coverage/default/42.sram_ctrl_multiple_keys.1088650911
/workspace/coverage/default/42.sram_ctrl_partial_access.2038078010
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1510623429
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1996726122
/workspace/coverage/default/42.sram_ctrl_regwen.3116971245
/workspace/coverage/default/42.sram_ctrl_smoke.4069224316
/workspace/coverage/default/42.sram_ctrl_stress_all.1486547628
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2060243608
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2537744821
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1652186920
/workspace/coverage/default/43.sram_ctrl_alert_test.3492104844
/workspace/coverage/default/43.sram_ctrl_bijection.2344769583
/workspace/coverage/default/43.sram_ctrl_executable.3667014059
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3315728883
/workspace/coverage/default/43.sram_ctrl_max_throughput.3270629610
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1250609042
/workspace/coverage/default/43.sram_ctrl_mem_walk.1531989362
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3494116361
/workspace/coverage/default/43.sram_ctrl_partial_access.3641744515
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2462213139
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3926209759
/workspace/coverage/default/43.sram_ctrl_regwen.1611701917
/workspace/coverage/default/43.sram_ctrl_smoke.3071909493
/workspace/coverage/default/43.sram_ctrl_stress_all.3819387260
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.139394717
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3554197485
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1250437904
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1295992
/workspace/coverage/default/44.sram_ctrl_alert_test.2283111661
/workspace/coverage/default/44.sram_ctrl_bijection.777812938
/workspace/coverage/default/44.sram_ctrl_executable.2257134724
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1715370813
/workspace/coverage/default/44.sram_ctrl_max_throughput.3173256412
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.805229817
/workspace/coverage/default/44.sram_ctrl_mem_walk.256461223
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2741969086
/workspace/coverage/default/44.sram_ctrl_partial_access.3997569840
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1731932643
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1642771906
/workspace/coverage/default/44.sram_ctrl_regwen.590913942
/workspace/coverage/default/44.sram_ctrl_smoke.1467371926
/workspace/coverage/default/44.sram_ctrl_stress_all.3598442947
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2800373073
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4089717294
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3204829869
/workspace/coverage/default/45.sram_ctrl_alert_test.2960969424
/workspace/coverage/default/45.sram_ctrl_bijection.798988588
/workspace/coverage/default/45.sram_ctrl_executable.1674426997
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3974683136
/workspace/coverage/default/45.sram_ctrl_max_throughput.3010261176
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3093743434
/workspace/coverage/default/45.sram_ctrl_mem_walk.152882106
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2264379175
/workspace/coverage/default/45.sram_ctrl_partial_access.1445754899
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1521146245
/workspace/coverage/default/45.sram_ctrl_ram_cfg.255166046
/workspace/coverage/default/45.sram_ctrl_regwen.3022083267
/workspace/coverage/default/45.sram_ctrl_smoke.1190704063
/workspace/coverage/default/45.sram_ctrl_stress_all.593225148
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.131249837
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3434034945
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1536078161
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2066173302
/workspace/coverage/default/46.sram_ctrl_alert_test.567721059
/workspace/coverage/default/46.sram_ctrl_bijection.2509816150
/workspace/coverage/default/46.sram_ctrl_executable.3342046987
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1928759375
/workspace/coverage/default/46.sram_ctrl_max_throughput.3075804112
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.183514901
/workspace/coverage/default/46.sram_ctrl_mem_walk.2214129468
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1357544338
/workspace/coverage/default/46.sram_ctrl_partial_access.1571631032
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3441537586
/workspace/coverage/default/46.sram_ctrl_ram_cfg.595618174
/workspace/coverage/default/46.sram_ctrl_regwen.96022728
/workspace/coverage/default/46.sram_ctrl_smoke.3921306109
/workspace/coverage/default/46.sram_ctrl_stress_all.1578280989
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3005115590
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3899728549
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2319963162
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.952907103
/workspace/coverage/default/47.sram_ctrl_alert_test.3998719470
/workspace/coverage/default/47.sram_ctrl_bijection.2468000174
/workspace/coverage/default/47.sram_ctrl_executable.2247532753
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3842241847
/workspace/coverage/default/47.sram_ctrl_max_throughput.3241531725
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2330720300
/workspace/coverage/default/47.sram_ctrl_mem_walk.64258594
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3476644567
/workspace/coverage/default/47.sram_ctrl_partial_access.1196705688
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.63355407
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2833278619
/workspace/coverage/default/47.sram_ctrl_regwen.1487185062
/workspace/coverage/default/47.sram_ctrl_smoke.3416206480
/workspace/coverage/default/47.sram_ctrl_stress_all.3614810547
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.780316915
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1728689563
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3253739216
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.574920142
/workspace/coverage/default/48.sram_ctrl_alert_test.1006976674
/workspace/coverage/default/48.sram_ctrl_bijection.2222488859
/workspace/coverage/default/48.sram_ctrl_executable.142113006
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2534031837
/workspace/coverage/default/48.sram_ctrl_max_throughput.2254923886
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1205480699
/workspace/coverage/default/48.sram_ctrl_mem_walk.3767106479
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3703014202
/workspace/coverage/default/48.sram_ctrl_partial_access.3991487730
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.556628754
/workspace/coverage/default/48.sram_ctrl_ram_cfg.455828293
/workspace/coverage/default/48.sram_ctrl_regwen.1320845911
/workspace/coverage/default/48.sram_ctrl_smoke.3095267070
/workspace/coverage/default/48.sram_ctrl_stress_all.803192633
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.841539764
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.928224787
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2841088552
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2241568882
/workspace/coverage/default/49.sram_ctrl_alert_test.2868872212
/workspace/coverage/default/49.sram_ctrl_bijection.2417020812
/workspace/coverage/default/49.sram_ctrl_executable.2179604120
/workspace/coverage/default/49.sram_ctrl_lc_escalation.4136568434
/workspace/coverage/default/49.sram_ctrl_max_throughput.576888083
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3556484053
/workspace/coverage/default/49.sram_ctrl_mem_walk.1712506259
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2872676322
/workspace/coverage/default/49.sram_ctrl_partial_access.2229938842
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2416359574
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4185400951
/workspace/coverage/default/49.sram_ctrl_regwen.2508520956
/workspace/coverage/default/49.sram_ctrl_smoke.1390664927
/workspace/coverage/default/49.sram_ctrl_stress_all.4175918661
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.470179415
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.676760843
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.819078383
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3405655740
/workspace/coverage/default/5.sram_ctrl_alert_test.908213804
/workspace/coverage/default/5.sram_ctrl_bijection.268339633
/workspace/coverage/default/5.sram_ctrl_executable.1709479048
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2913582574
/workspace/coverage/default/5.sram_ctrl_max_throughput.1676921501
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3942939217
/workspace/coverage/default/5.sram_ctrl_mem_walk.1915644879
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1331653318
/workspace/coverage/default/5.sram_ctrl_partial_access.712606872
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.986255856
/workspace/coverage/default/5.sram_ctrl_ram_cfg.357020386
/workspace/coverage/default/5.sram_ctrl_regwen.2560668386
/workspace/coverage/default/5.sram_ctrl_smoke.2939528350
/workspace/coverage/default/5.sram_ctrl_stress_all.2200614146
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3383820960
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3470741500
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4030567841
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1919217368
/workspace/coverage/default/6.sram_ctrl_alert_test.1240781194
/workspace/coverage/default/6.sram_ctrl_bijection.490480066
/workspace/coverage/default/6.sram_ctrl_executable.3132402536
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3014124316
/workspace/coverage/default/6.sram_ctrl_max_throughput.1925164154
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.610425678
/workspace/coverage/default/6.sram_ctrl_mem_walk.2884173067
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2501763765
/workspace/coverage/default/6.sram_ctrl_partial_access.203101284
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1475358597
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1735417212
/workspace/coverage/default/6.sram_ctrl_regwen.1434849060
/workspace/coverage/default/6.sram_ctrl_smoke.1671756023
/workspace/coverage/default/6.sram_ctrl_stress_all.2763628727
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.418254693
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.424690830
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3434588586
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3959982274
/workspace/coverage/default/7.sram_ctrl_alert_test.2183977828
/workspace/coverage/default/7.sram_ctrl_bijection.4208741826
/workspace/coverage/default/7.sram_ctrl_executable.2282378881
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3196361326
/workspace/coverage/default/7.sram_ctrl_max_throughput.618069151
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1981788122
/workspace/coverage/default/7.sram_ctrl_mem_walk.3890485686
/workspace/coverage/default/7.sram_ctrl_partial_access.1200517912
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2917887569
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1114079892
/workspace/coverage/default/7.sram_ctrl_regwen.2686066116
/workspace/coverage/default/7.sram_ctrl_smoke.1815752431
/workspace/coverage/default/7.sram_ctrl_stress_all.3564929426
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2329311132
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1471044394
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.126635260
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3612102184
/workspace/coverage/default/8.sram_ctrl_alert_test.4002430311
/workspace/coverage/default/8.sram_ctrl_bijection.2611009049
/workspace/coverage/default/8.sram_ctrl_executable.3527297298
/workspace/coverage/default/8.sram_ctrl_lc_escalation.978587852
/workspace/coverage/default/8.sram_ctrl_max_throughput.3239798616
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3367584261
/workspace/coverage/default/8.sram_ctrl_mem_walk.2228375245
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1940102206
/workspace/coverage/default/8.sram_ctrl_partial_access.284367493
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1250682528
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3143148685
/workspace/coverage/default/8.sram_ctrl_regwen.487010189
/workspace/coverage/default/8.sram_ctrl_smoke.2264602023
/workspace/coverage/default/8.sram_ctrl_stress_all.2735725222
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1203537946
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1300590548
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.681571091
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2152026087
/workspace/coverage/default/9.sram_ctrl_alert_test.4015158513
/workspace/coverage/default/9.sram_ctrl_bijection.2039376928
/workspace/coverage/default/9.sram_ctrl_executable.2842109813
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2753546510
/workspace/coverage/default/9.sram_ctrl_max_throughput.1254980570
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2446893933
/workspace/coverage/default/9.sram_ctrl_mem_walk.1780539347
/workspace/coverage/default/9.sram_ctrl_multiple_keys.52381384
/workspace/coverage/default/9.sram_ctrl_partial_access.1635241853
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.658606604
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3944982813
/workspace/coverage/default/9.sram_ctrl_regwen.1314965054
/workspace/coverage/default/9.sram_ctrl_smoke.1843335721
/workspace/coverage/default/9.sram_ctrl_stress_all.3068318110
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3436489023
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.808625035
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1058027739

Total test records in report: 1031

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.sram_ctrl_mem_walk.3769703051	Jul 30 07:23:59 PM PDT 24	Jul 30 07:24:05 PM PDT 24	303891689 ps
T2	/workspace/coverage/default/12.sram_ctrl_partial_access.1535218193	Jul 30 07:25:04 PM PDT 24	Jul 30 07:27:34 PM PDT 24	1570210969 ps
T3	/workspace/coverage/default/47.sram_ctrl_lc_escalation.3842241847	Jul 30 07:31:15 PM PDT 24	Jul 30 07:31:17 PM PDT 24	131888641 ps
T5	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2537744821	Jul 30 07:30:18 PM PDT 24	Jul 30 07:32:15 PM PDT 24	161785817 ps
T4	/workspace/coverage/default/15.sram_ctrl_bijection.2717711679	Jul 30 07:25:21 PM PDT 24	Jul 30 07:26:06 PM PDT 24	11267421123 ps
T8	/workspace/coverage/default/28.sram_ctrl_ram_cfg.2188461793	Jul 30 07:27:45 PM PDT 24	Jul 30 07:27:45 PM PDT 24	56575919 ps
T9	/workspace/coverage/default/8.sram_ctrl_max_throughput.3239798616	Jul 30 07:24:28 PM PDT 24	Jul 30 07:24:30 PM PDT 24	45183792 ps
T10	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3959982274	Jul 30 07:24:22 PM PDT 24	Jul 30 07:36:41 PM PDT 24	1436891644 ps
T11	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1555058659	Jul 30 07:27:05 PM PDT 24	Jul 30 07:27:58 PM PDT 24	1775152413 ps
T6	/workspace/coverage/default/41.sram_ctrl_lc_escalation.553924132	Jul 30 07:30:06 PM PDT 24	Jul 30 07:30:12 PM PDT 24	676627368 ps
T24	/workspace/coverage/default/5.sram_ctrl_partial_access.712606872	Jul 30 07:24:18 PM PDT 24	Jul 30 07:24:30 PM PDT 24	272049965 ps
T7	/workspace/coverage/default/15.sram_ctrl_lc_escalation.1590893593	Jul 30 07:25:24 PM PDT 24	Jul 30 07:25:25 PM PDT 24	108763950 ps
T41	/workspace/coverage/default/30.sram_ctrl_multiple_keys.3672882353	Jul 30 07:28:01 PM PDT 24	Jul 30 07:30:50 PM PDT 24	8839770227 ps
T54	/workspace/coverage/default/0.sram_ctrl_smoke.776610418	Jul 30 07:23:50 PM PDT 24	Jul 30 07:24:00 PM PDT 24	2064448560 ps
T47	/workspace/coverage/default/10.sram_ctrl_mem_walk.3751527918	Jul 30 07:24:50 PM PDT 24	Jul 30 07:25:01 PM PDT 24	1133090116 ps
T25	/workspace/coverage/default/49.sram_ctrl_partial_access.2229938842	Jul 30 07:31:33 PM PDT 24	Jul 30 07:31:42 PM PDT 24	374255186 ps
T63	/workspace/coverage/default/21.sram_ctrl_smoke.3635483202	Jul 30 07:26:28 PM PDT 24	Jul 30 07:27:28 PM PDT 24	216746572 ps
T28	/workspace/coverage/default/47.sram_ctrl_ram_cfg.2833278619	Jul 30 07:31:20 PM PDT 24	Jul 30 07:31:21 PM PDT 24	27524991 ps
T139	/workspace/coverage/default/38.sram_ctrl_max_throughput.3569569473	Jul 30 07:29:27 PM PDT 24	Jul 30 07:31:25 PM PDT 24	355939063 ps
T67	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.118536418	Jul 30 07:24:53 PM PDT 24	Jul 30 07:30:18 PM PDT 24	12499696189 ps
T27	/workspace/coverage/default/23.sram_ctrl_regwen.2738213440	Jul 30 07:26:52 PM PDT 24	Jul 30 07:31:28 PM PDT 24	4426298162 ps
T83	/workspace/coverage/default/23.sram_ctrl_partial_access.3393484689	Jul 30 07:26:50 PM PDT 24	Jul 30 07:27:11 PM PDT 24	16142262432 ps
T26	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.779735787	Jul 30 07:28:43 PM PDT 24	Jul 30 07:30:52 PM PDT 24	3812742233 ps
T100	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.554518351	Jul 30 07:28:09 PM PDT 24	Jul 30 07:34:01 PM PDT 24	9650428551 ps
T101	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.424690830	Jul 30 07:24:17 PM PDT 24	Jul 30 07:27:30 PM PDT 24	7749176205 ps
T20	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.470179415	Jul 30 07:31:39 PM PDT 24	Jul 30 07:39:05 PM PDT 24	2132282434 ps
T84	/workspace/coverage/default/7.sram_ctrl_partial_access.1200517912	Jul 30 07:24:19 PM PDT 24	Jul 30 07:25:29 PM PDT 24	2135872513 ps
T18	/workspace/coverage/default/13.sram_ctrl_lc_escalation.2769929396	Jul 30 07:25:08 PM PDT 24	Jul 30 07:25:10 PM PDT 24	203934808 ps
T102	/workspace/coverage/default/48.sram_ctrl_smoke.3095267070	Jul 30 07:31:22 PM PDT 24	Jul 30 07:31:36 PM PDT 24	258116003 ps
T22	/workspace/coverage/default/43.sram_ctrl_lc_escalation.3315728883	Jul 30 07:30:31 PM PDT 24	Jul 30 07:30:40 PM PDT 24	1437573926 ps
T19	/workspace/coverage/default/13.sram_ctrl_stress_all.3927147082	Jul 30 07:25:16 PM PDT 24	Jul 30 08:14:22 PM PDT 24	30354437042 ps
T140	/workspace/coverage/default/29.sram_ctrl_smoke.3938852048	Jul 30 07:27:54 PM PDT 24	Jul 30 07:28:09 PM PDT 24	946293238 ps
T23	/workspace/coverage/default/44.sram_ctrl_lc_escalation.1715370813	Jul 30 07:30:42 PM PDT 24	Jul 30 07:30:48 PM PDT 24	8144123373 ps
T141	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3422661083	Jul 30 07:25:02 PM PDT 24	Jul 30 07:27:02 PM PDT 24	377583568 ps
T137	/workspace/coverage/default/42.sram_ctrl_bijection.2217491059	Jul 30 07:30:15 PM PDT 24	Jul 30 07:31:39 PM PDT 24	38235123405 ps
T12	/workspace/coverage/default/27.sram_ctrl_alert_test.3642694627	Jul 30 07:27:36 PM PDT 24	Jul 30 07:27:37 PM PDT 24	26263761 ps
T42	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3204829869	Jul 30 07:30:55 PM PDT 24	Jul 30 07:45:28 PM PDT 24	9929053460 ps
T21	/workspace/coverage/default/1.sram_ctrl_stress_all.1364052	Jul 30 07:23:56 PM PDT 24	Jul 30 07:35:23 PM PDT 24	3835426920 ps
T29	/workspace/coverage/default/9.sram_ctrl_ram_cfg.3944982813	Jul 30 07:24:40 PM PDT 24	Jul 30 07:24:40 PM PDT 24	25959570 ps
T134	/workspace/coverage/default/40.sram_ctrl_multiple_keys.2603031239	Jul 30 07:29:45 PM PDT 24	Jul 30 07:58:15 PM PDT 24	14534534613 ps
T55	/workspace/coverage/default/7.sram_ctrl_mem_walk.3890485686	Jul 30 07:24:27 PM PDT 24	Jul 30 07:24:36 PM PDT 24	180661417 ps
T105	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3554197485	Jul 30 07:30:27 PM PDT 24	Jul 30 07:33:12 PM PDT 24	11240523261 ps
T138	/workspace/coverage/default/19.sram_ctrl_ram_cfg.2401644683	Jul 30 07:26:14 PM PDT 24	Jul 30 07:26:15 PM PDT 24	30245646 ps
T56	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.804131717	Jul 30 07:30:22 PM PDT 24	Jul 30 07:33:08 PM PDT 24	20941632919 ps
T142	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2191124763	Jul 30 07:25:25 PM PDT 24	Jul 30 07:27:10 PM PDT 24	586542035 ps
T143	/workspace/coverage/default/33.sram_ctrl_multiple_keys.3860368265	Jul 30 07:28:33 PM PDT 24	Jul 30 07:42:29 PM PDT 24	9955366259 ps
T57	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1948761535	Jul 30 07:28:33 PM PDT 24	Jul 30 07:28:39 PM PDT 24	381397012 ps
T144	/workspace/coverage/default/36.sram_ctrl_multiple_keys.3250772864	Jul 30 07:28:59 PM PDT 24	Jul 30 07:55:36 PM PDT 24	9907129274 ps
T145	/workspace/coverage/default/39.sram_ctrl_max_throughput.600456704	Jul 30 07:29:38 PM PDT 24	Jul 30 07:29:56 PM PDT 24	526681208 ps
T72	/workspace/coverage/default/9.sram_ctrl_lc_escalation.2753546510	Jul 30 07:24:39 PM PDT 24	Jul 30 07:24:42 PM PDT 24	222007204 ps
T53	/workspace/coverage/default/20.sram_ctrl_mem_walk.808437503	Jul 30 07:26:35 PM PDT 24	Jul 30 07:26:42 PM PDT 24	1373304932 ps
T146	/workspace/coverage/default/46.sram_ctrl_ram_cfg.595618174	Jul 30 07:31:07 PM PDT 24	Jul 30 07:31:08 PM PDT 24	80225238 ps
T106	/workspace/coverage/default/13.sram_ctrl_stress_pipeline.194446455	Jul 30 07:25:06 PM PDT 24	Jul 30 07:29:02 PM PDT 24	2502437509 ps
T15	/workspace/coverage/default/3.sram_ctrl_sec_cm.1984890944	Jul 30 07:24:08 PM PDT 24	Jul 30 07:24:10 PM PDT 24	320609578 ps
T32	/workspace/coverage/default/19.sram_ctrl_max_throughput.2308161356	Jul 30 07:26:12 PM PDT 24	Jul 30 07:28:13 PM PDT 24	409772639 ps
T33	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.639473861	Jul 30 07:25:36 PM PDT 24	Jul 30 07:31:56 PM PDT 24	14992297640 ps
T34	/workspace/coverage/default/26.sram_ctrl_max_throughput.3617434409	Jul 30 07:27:21 PM PDT 24	Jul 30 07:27:23 PM PDT 24	545925203 ps
T35	/workspace/coverage/default/20.sram_ctrl_multiple_keys.329889735	Jul 30 07:26:14 PM PDT 24	Jul 30 07:34:39 PM PDT 24	9445361552 ps
T36	/workspace/coverage/default/43.sram_ctrl_ram_cfg.3926209759	Jul 30 07:30:30 PM PDT 24	Jul 30 07:30:31 PM PDT 24	85228741 ps
T37	/workspace/coverage/default/4.sram_ctrl_mem_walk.1713361262	Jul 30 07:24:13 PM PDT 24	Jul 30 07:24:19 PM PDT 24	631818815 ps
T38	/workspace/coverage/default/46.sram_ctrl_stress_all.1578280989	Jul 30 07:31:05 PM PDT 24	Jul 30 08:13:01 PM PDT 24	12590191370 ps
T39	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1894369430	Jul 30 07:26:31 PM PDT 24	Jul 30 07:27:06 PM PDT 24	114310884 ps
T40	/workspace/coverage/default/12.sram_ctrl_stress_all.3229490637	Jul 30 07:25:05 PM PDT 24	Jul 30 08:57:11 PM PDT 24	15083231598 ps
T44	/workspace/coverage/default/21.sram_ctrl_executable.74812786	Jul 30 07:26:30 PM PDT 24	Jul 30 07:52:40 PM PDT 24	13287584158 ps
T13	/workspace/coverage/default/7.sram_ctrl_alert_test.2183977828	Jul 30 07:24:28 PM PDT 24	Jul 30 07:24:29 PM PDT 24	14747667 ps
T45	/workspace/coverage/default/3.sram_ctrl_regwen.1720913608	Jul 30 07:24:07 PM PDT 24	Jul 30 07:37:55 PM PDT 24	47996242610 ps
T147	/workspace/coverage/default/23.sram_ctrl_smoke.1781725102	Jul 30 07:26:41 PM PDT 24	Jul 30 07:26:45 PM PDT 24	259740177 ps
T148	/workspace/coverage/default/31.sram_ctrl_max_throughput.3023310997	Jul 30 07:28:08 PM PDT 24	Jul 30 07:30:14 PM PDT 24	260094513 ps
T149	/workspace/coverage/default/14.sram_ctrl_smoke.2583337246	Jul 30 07:25:13 PM PDT 24	Jul 30 07:25:26 PM PDT 24	247494746 ps
T107	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1142469439	Jul 30 07:29:45 PM PDT 24	Jul 30 07:32:51 PM PDT 24	3759962192 ps
T129	/workspace/coverage/default/21.sram_ctrl_stress_all.3015458063	Jul 30 07:26:36 PM PDT 24	Jul 30 09:09:57 PM PDT 24	48402505656 ps
T46	/workspace/coverage/default/0.sram_ctrl_stress_all.2881305014	Jul 30 07:23:54 PM PDT 24	Jul 30 07:51:40 PM PDT 24	37975021398 ps
T135	/workspace/coverage/default/7.sram_ctrl_executable.2282378881	Jul 30 07:24:26 PM PDT 24	Jul 30 07:32:47 PM PDT 24	12048659206 ps
T43	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.1734047160	Jul 30 07:27:20 PM PDT 24	Jul 30 07:30:45 PM PDT 24	611036651 ps
T108	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2800373073	Jul 30 07:30:39 PM PDT 24	Jul 30 07:34:01 PM PDT 24	4032257957 ps
T150	/workspace/coverage/default/26.sram_ctrl_mem_walk.3031154952	Jul 30 07:27:23 PM PDT 24	Jul 30 07:27:34 PM PDT 24	444622207 ps
T151	/workspace/coverage/default/29.sram_ctrl_bijection.388376664	Jul 30 07:27:53 PM PDT 24	Jul 30 07:29:14 PM PDT 24	22629973771 ps
T152	/workspace/coverage/default/2.sram_ctrl_partial_access.2456595274	Jul 30 07:23:59 PM PDT 24	Jul 30 07:26:04 PM PDT 24	715436848 ps
T153	/workspace/coverage/default/41.sram_ctrl_bijection.2976044157	Jul 30 07:30:02 PM PDT 24	Jul 30 07:31:10 PM PDT 24	3313548527 ps
T154	/workspace/coverage/default/35.sram_ctrl_max_throughput.3436468750	Jul 30 07:28:48 PM PDT 24	Jul 30 07:30:22 PM PDT 24	120544004 ps
T155	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.674069870	Jul 30 07:24:05 PM PDT 24	Jul 30 07:24:06 PM PDT 24	141973018 ps
T109	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2469659357	Jul 30 07:28:41 PM PDT 24	Jul 30 07:32:17 PM PDT 24	2416841079 ps
T58	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2400073314	Jul 30 07:29:16 PM PDT 24	Jul 30 07:31:26 PM PDT 24	2534509103 ps
T130	/workspace/coverage/default/43.sram_ctrl_regwen.1611701917	Jul 30 07:30:31 PM PDT 24	Jul 30 07:42:54 PM PDT 24	22372274645 ps
T156	/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2985233409	Jul 30 07:24:45 PM PDT 24	Jul 30 07:30:53 PM PDT 24	3766150751 ps
T157	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2558469817	Jul 30 07:29:37 PM PDT 24	Jul 30 07:33:43 PM PDT 24	6045750363 ps
T70	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2706655761	Jul 30 07:28:33 PM PDT 24	Jul 30 07:30:54 PM PDT 24	5851731440 ps
T59	/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.131249837	Jul 30 07:31:00 PM PDT 24	Jul 30 07:42:46 PM PDT 24	13689213677 ps
T131	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1564875126	Jul 30 07:25:00 PM PDT 24	Jul 30 07:30:30 PM PDT 24	66682780593 ps
T132	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3438119354	Jul 30 07:25:36 PM PDT 24	Jul 30 07:30:10 PM PDT 24	10320453939 ps
T87	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.918209572	Jul 30 07:27:16 PM PDT 24	Jul 30 07:36:28 PM PDT 24	4098351626 ps
T158	/workspace/coverage/default/44.sram_ctrl_smoke.1467371926	Jul 30 07:30:33 PM PDT 24	Jul 30 07:30:49 PM PDT 24	1495476046 ps
T159	/workspace/coverage/default/38.sram_ctrl_ram_cfg.4090026164	Jul 30 07:29:25 PM PDT 24	Jul 30 07:29:26 PM PDT 24	45053227 ps
T160	/workspace/coverage/default/3.sram_ctrl_executable.2166899689	Jul 30 07:24:05 PM PDT 24	Jul 30 07:49:01 PM PDT 24	44916418411 ps
T161	/workspace/coverage/default/14.sram_ctrl_mem_walk.2877862793	Jul 30 07:25:15 PM PDT 24	Jul 30 07:25:21 PM PDT 24	233974927 ps
T162	/workspace/coverage/default/20.sram_ctrl_smoke.1441766335	Jul 30 07:26:14 PM PDT 24	Jul 30 07:27:18 PM PDT 24	498375220 ps
T14	/workspace/coverage/default/33.sram_ctrl_alert_test.1133514710	Jul 30 07:28:36 PM PDT 24	Jul 30 07:28:37 PM PDT 24	18345376 ps
T163	/workspace/coverage/default/44.sram_ctrl_mem_walk.256461223	Jul 30 07:31:00 PM PDT 24	Jul 30 07:31:08 PM PDT 24	529856187 ps
T164	/workspace/coverage/default/17.sram_ctrl_bijection.2892118481	Jul 30 07:25:45 PM PDT 24	Jul 30 07:26:54 PM PDT 24	7673675056 ps
T52	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.610425678	Jul 30 07:24:23 PM PDT 24	Jul 30 07:24:27 PM PDT 24	404882579 ps
T165	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1286041905	Jul 30 07:27:52 PM PDT 24	Jul 30 07:27:54 PM PDT 24	541630783 ps
T166	/workspace/coverage/default/43.sram_ctrl_executable.3667014059	Jul 30 07:30:31 PM PDT 24	Jul 30 07:53:00 PM PDT 24	106812191844 ps
T167	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2851465308	Jul 30 07:23:56 PM PDT 24	Jul 30 07:28:52 PM PDT 24	65069824930 ps
T168	/workspace/coverage/default/37.sram_ctrl_lc_escalation.189966370	Jul 30 07:29:13 PM PDT 24	Jul 30 07:29:18 PM PDT 24	992304751 ps
T169	/workspace/coverage/default/43.sram_ctrl_partial_access.3641744515	Jul 30 07:30:32 PM PDT 24	Jul 30 07:30:49 PM PDT 24	1296098693 ps
T170	/workspace/coverage/default/46.sram_ctrl_executable.3342046987	Jul 30 07:31:06 PM PDT 24	Jul 30 07:42:37 PM PDT 24	6319602939 ps
T171	/workspace/coverage/default/32.sram_ctrl_partial_access.2095091259	Jul 30 07:28:16 PM PDT 24	Jul 30 07:29:18 PM PDT 24	489371931 ps
T172	/workspace/coverage/default/22.sram_ctrl_multiple_keys.1226363548	Jul 30 07:26:35 PM PDT 24	Jul 30 07:37:07 PM PDT 24	1750324973 ps
T173	/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2440796542	Jul 30 07:29:38 PM PDT 24	Jul 30 07:30:48 PM PDT 24	136514436 ps
T174	/workspace/coverage/default/9.sram_ctrl_regwen.1314965054	Jul 30 07:24:42 PM PDT 24	Jul 30 07:50:08 PM PDT 24	28297450704 ps
T88	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.257965837	Jul 30 07:25:28 PM PDT 24	Jul 30 07:29:20 PM PDT 24	3531604508 ps
T175	/workspace/coverage/default/44.sram_ctrl_executable.2257134724	Jul 30 07:30:43 PM PDT 24	Jul 30 07:45:11 PM PDT 24	28916154735 ps
T133	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2462213139	Jul 30 07:30:32 PM PDT 24	Jul 30 07:35:59 PM PDT 24	56183254719 ps
T176	/workspace/coverage/default/26.sram_ctrl_lc_escalation.2422981985	Jul 30 07:27:20 PM PDT 24	Jul 30 07:27:26 PM PDT 24	740619467 ps
T177	/workspace/coverage/default/6.sram_ctrl_partial_access.203101284	Jul 30 07:24:17 PM PDT 24	Jul 30 07:24:19 PM PDT 24	226552456 ps
T89	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1919217368	Jul 30 07:24:20 PM PDT 24	Jul 30 07:31:11 PM PDT 24	9074467454 ps
T178	/workspace/coverage/default/10.sram_ctrl_regwen.2995781846	Jul 30 07:24:48 PM PDT 24	Jul 30 07:44:49 PM PDT 24	14825897893 ps
T179	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3734020403	Jul 30 07:24:00 PM PDT 24	Jul 30 07:25:01 PM PDT 24	2118930378 ps
T180	/workspace/coverage/default/9.sram_ctrl_smoke.1843335721	Jul 30 07:24:36 PM PDT 24	Jul 30 07:25:09 PM PDT 24	3442364476 ps
T181	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2758671717	Jul 30 07:28:11 PM PDT 24	Jul 30 07:30:41 PM PDT 24	927692853 ps
T182	/workspace/coverage/default/33.sram_ctrl_bijection.1635303835	Jul 30 07:28:28 PM PDT 24	Jul 30 07:29:44 PM PDT 24	18049969992 ps
T90	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.504016418	Jul 30 07:27:49 PM PDT 24	Jul 30 07:27:53 PM PDT 24	672455665 ps
T183	/workspace/coverage/default/17.sram_ctrl_regwen.1306482373	Jul 30 07:25:53 PM PDT 24	Jul 30 07:36:57 PM PDT 24	2186234232 ps
T184	/workspace/coverage/default/6.sram_ctrl_ram_cfg.1735417212	Jul 30 07:24:19 PM PDT 24	Jul 30 07:24:20 PM PDT 24	182095490 ps
T185	/workspace/coverage/default/30.sram_ctrl_lc_escalation.1874058029	Jul 30 07:28:02 PM PDT 24	Jul 30 07:28:10 PM PDT 24	2701116742 ps
T186	/workspace/coverage/default/13.sram_ctrl_max_throughput.3931148395	Jul 30 07:25:07 PM PDT 24	Jul 30 07:26:01 PM PDT 24	230570833 ps
T187	/workspace/coverage/default/8.sram_ctrl_bijection.2611009049	Jul 30 07:24:27 PM PDT 24	Jul 30 07:25:24 PM PDT 24	5245494579 ps
T188	/workspace/coverage/default/24.sram_ctrl_lc_escalation.1162378680	Jul 30 07:27:01 PM PDT 24	Jul 30 07:27:08 PM PDT 24	646212349 ps
T91	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.308844650	Jul 30 07:25:10 PM PDT 24	Jul 30 07:35:39 PM PDT 24	4140081191 ps
T189	/workspace/coverage/default/18.sram_ctrl_alert_test.415556899	Jul 30 07:26:07 PM PDT 24	Jul 30 07:26:08 PM PDT 24	19136639 ps
T190	/workspace/coverage/default/42.sram_ctrl_regwen.3116971245	Jul 30 07:30:22 PM PDT 24	Jul 30 07:46:52 PM PDT 24	8482312312 ps
T191	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3381124821	Jul 30 07:27:17 PM PDT 24	Jul 30 07:27:20 PM PDT 24	489200328 ps
T192	/workspace/coverage/default/47.sram_ctrl_regwen.1487185062	Jul 30 07:31:18 PM PDT 24	Jul 30 07:43:47 PM PDT 24	6604436676 ps
T193	/workspace/coverage/default/14.sram_ctrl_ram_cfg.4260411148	Jul 30 07:25:18 PM PDT 24	Jul 30 07:25:18 PM PDT 24	58492674 ps
T194	/workspace/coverage/default/2.sram_ctrl_multiple_keys.273746022	Jul 30 07:23:57 PM PDT 24	Jul 30 07:29:43 PM PDT 24	8061440631 ps
T195	/workspace/coverage/default/25.sram_ctrl_stress_all.2206238249	Jul 30 07:27:17 PM PDT 24	Jul 30 07:50:58 PM PDT 24	20521095255 ps
T196	/workspace/coverage/default/6.sram_ctrl_lc_escalation.3014124316	Jul 30 07:24:21 PM PDT 24	Jul 30 07:24:29 PM PDT 24	5190046895 ps
T197	/workspace/coverage/default/6.sram_ctrl_stress_all.2763628727	Jul 30 07:24:23 PM PDT 24	Jul 30 08:16:13 PM PDT 24	187446210584 ps
T198	/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1910657243	Jul 30 07:26:11 PM PDT 24	Jul 30 07:29:10 PM PDT 24	2617419793 ps
T199	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1142053277	Jul 30 07:25:57 PM PDT 24	Jul 30 07:26:16 PM PDT 24	758311165 ps
T200	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3035162029	Jul 30 07:23:53 PM PDT 24	Jul 30 07:25:57 PM PDT 24	2514775493 ps
T201	/workspace/coverage/default/43.sram_ctrl_bijection.2344769583	Jul 30 07:30:28 PM PDT 24	Jul 30 07:31:05 PM PDT 24	1025211003 ps
T202	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1466900811	Jul 30 07:24:12 PM PDT 24	Jul 30 07:25:34 PM PDT 24	1007343334 ps
T203	/workspace/coverage/default/21.sram_ctrl_ram_cfg.3040767297	Jul 30 07:26:31 PM PDT 24	Jul 30 07:26:32 PM PDT 24	29320834 ps
T204	/workspace/coverage/default/25.sram_ctrl_multiple_keys.4247711515	Jul 30 07:27:07 PM PDT 24	Jul 30 07:41:06 PM PDT 24	156806173256 ps
T205	/workspace/coverage/default/37.sram_ctrl_alert_test.2646197339	Jul 30 07:29:23 PM PDT 24	Jul 30 07:29:24 PM PDT 24	24530104 ps
T206	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3463726719	Jul 30 07:25:36 PM PDT 24	Jul 30 07:55:30 PM PDT 24	4731790719 ps
T207	/workspace/coverage/default/38.sram_ctrl_mem_walk.1089401206	Jul 30 07:29:31 PM PDT 24	Jul 30 07:29:36 PM PDT 24	355064388 ps
T208	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2430586151	Jul 30 07:27:26 PM PDT 24	Jul 30 07:27:29 PM PDT 24	88711912 ps
T209	/workspace/coverage/default/23.sram_ctrl_stress_pipeline.579758076	Jul 30 07:26:47 PM PDT 24	Jul 30 07:29:55 PM PDT 24	7824144252 ps
T210	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2411181525	Jul 30 07:29:53 PM PDT 24	Jul 30 07:30:03 PM PDT 24	108313898 ps
T211	/workspace/coverage/default/13.sram_ctrl_regwen.1169581965	Jul 30 07:25:10 PM PDT 24	Jul 30 07:44:28 PM PDT 24	80308401541 ps
T60	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.182438502	Jul 30 07:26:53 PM PDT 24	Jul 30 07:33:33 PM PDT 24	970028315 ps
T212	/workspace/coverage/default/4.sram_ctrl_multiple_keys.1952382571	Jul 30 07:24:08 PM PDT 24	Jul 30 07:28:26 PM PDT 24	923015168 ps
T213	/workspace/coverage/default/39.sram_ctrl_alert_test.198877992	Jul 30 07:29:45 PM PDT 24	Jul 30 07:29:46 PM PDT 24	38333500 ps
T214	/workspace/coverage/default/40.sram_ctrl_max_throughput.1029890172	Jul 30 07:29:49 PM PDT 24	Jul 30 07:32:02 PM PDT 24	506998953 ps
T215	/workspace/coverage/default/15.sram_ctrl_smoke.2970681280	Jul 30 07:25:22 PM PDT 24	Jul 30 07:25:34 PM PDT 24	192831416 ps
T216	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1410287790	Jul 30 07:29:29 PM PDT 24	Jul 30 07:29:33 PM PDT 24	217035188 ps
T217	/workspace/coverage/default/13.sram_ctrl_bijection.2926441472	Jul 30 07:25:05 PM PDT 24	Jul 30 07:26:09 PM PDT 24	36676045265 ps
T218	/workspace/coverage/default/24.sram_ctrl_multiple_keys.198017426	Jul 30 07:26:54 PM PDT 24	Jul 30 07:42:49 PM PDT 24	15855152314 ps
T61	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.4212924461	Jul 30 07:24:01 PM PDT 24	Jul 30 07:24:04 PM PDT 24	205601362 ps
T219	/workspace/coverage/default/37.sram_ctrl_ram_cfg.1520953543	Jul 30 07:29:20 PM PDT 24	Jul 30 07:29:20 PM PDT 24	76669919 ps
T220	/workspace/coverage/default/20.sram_ctrl_ram_cfg.51414826	Jul 30 07:26:23 PM PDT 24	Jul 30 07:26:24 PM PDT 24	78787426 ps
T221	/workspace/coverage/default/20.sram_ctrl_alert_test.3708036767	Jul 30 07:26:26 PM PDT 24	Jul 30 07:26:26 PM PDT 24	30187779 ps
T222	/workspace/coverage/default/6.sram_ctrl_max_throughput.1925164154	Jul 30 07:24:17 PM PDT 24	Jul 30 07:25:20 PM PDT 24	229196253 ps
T223	/workspace/coverage/default/26.sram_ctrl_regwen.1465964897	Jul 30 07:27:19 PM PDT 24	Jul 30 07:56:19 PM PDT 24	107163379847 ps
T224	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.4263521743	Jul 30 07:29:02 PM PDT 24	Jul 30 07:30:56 PM PDT 24	679602359 ps
T225	/workspace/coverage/default/23.sram_ctrl_mem_walk.958485365	Jul 30 07:26:50 PM PDT 24	Jul 30 07:27:01 PM PDT 24	470367784 ps
T62	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2849141024	Jul 30 07:26:34 PM PDT 24	Jul 30 07:27:35 PM PDT 24	4938356791 ps
T226	/workspace/coverage/default/42.sram_ctrl_alert_test.3045600912	Jul 30 07:30:21 PM PDT 24	Jul 30 07:30:22 PM PDT 24	32329101 ps
T227	/workspace/coverage/default/28.sram_ctrl_alert_test.4247442718	Jul 30 07:27:52 PM PDT 24	Jul 30 07:27:53 PM PDT 24	40989725 ps
T71	/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.79111403	Jul 30 07:28:29 PM PDT 24	Jul 30 07:31:01 PM PDT 24	11573667806 ps
T228	/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2329132189	Jul 30 07:29:04 PM PDT 24	Jul 30 07:54:26 PM PDT 24	9405826281 ps
T229	/workspace/coverage/default/41.sram_ctrl_smoke.1726258126	Jul 30 07:30:02 PM PDT 24	Jul 30 07:30:21 PM PDT 24	117887970 ps
T230	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3929960031	Jul 30 07:28:03 PM PDT 24	Jul 30 07:28:22 PM PDT 24	79830470 ps
T231	/workspace/coverage/default/0.sram_ctrl_mem_walk.894354522	Jul 30 07:23:51 PM PDT 24	Jul 30 07:24:03 PM PDT 24	2721475883 ps
T232	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3612754355	Jul 30 07:24:53 PM PDT 24	Jul 30 07:33:36 PM PDT 24	66671061258 ps
T233	/workspace/coverage/default/42.sram_ctrl_lc_escalation.3066216487	Jul 30 07:30:19 PM PDT 24	Jul 30 07:30:23 PM PDT 24	388392040 ps
T234	/workspace/coverage/default/24.sram_ctrl_smoke.1181749135	Jul 30 07:26:55 PM PDT 24	Jul 30 07:27:49 PM PDT 24	982356628 ps
T235	/workspace/coverage/default/35.sram_ctrl_multiple_keys.263865405	Jul 30 07:28:47 PM PDT 24	Jul 30 07:47:58 PM PDT 24	2778206960 ps
T236	/workspace/coverage/default/0.sram_ctrl_regwen.1541685951	Jul 30 07:23:49 PM PDT 24	Jul 30 07:44:27 PM PDT 24	3351830828 ps
T237	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2984813210	Jul 30 07:25:35 PM PDT 24	Jul 30 07:27:18 PM PDT 24	554414942 ps
T238	/workspace/coverage/default/16.sram_ctrl_bijection.737163532	Jul 30 07:25:33 PM PDT 24	Jul 30 07:26:55 PM PDT 24	10345591852 ps
T48	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1203537946	Jul 30 07:24:36 PM PDT 24	Jul 30 07:26:52 PM PDT 24	8185419854 ps
T239	/workspace/coverage/default/39.sram_ctrl_partial_access.1880853140	Jul 30 07:29:37 PM PDT 24	Jul 30 07:29:50 PM PDT 24	445070983 ps
T240	/workspace/coverage/default/29.sram_ctrl_mem_walk.413193768	Jul 30 07:27:58 PM PDT 24	Jul 30 07:28:09 PM PDT 24	1767214391 ps
T241	/workspace/coverage/default/16.sram_ctrl_max_throughput.2135898189	Jul 30 07:25:35 PM PDT 24	Jul 30 07:27:30 PM PDT 24	144748989 ps
T242	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2436880859	Jul 30 07:25:13 PM PDT 24	Jul 30 07:30:31 PM PDT 24	15495500295 ps
T243	/workspace/coverage/default/4.sram_ctrl_regwen.2868658013	Jul 30 07:24:13 PM PDT 24	Jul 30 07:26:57 PM PDT 24	679858582 ps
T244	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1058027739	Jul 30 07:24:38 PM PDT 24	Jul 30 07:24:39 PM PDT 24	126538081 ps
T245	/workspace/coverage/default/49.sram_ctrl_stress_all.4175918661	Jul 30 07:31:39 PM PDT 24	Jul 30 08:05:10 PM PDT 24	85471290929 ps
T246	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3495804692	Jul 30 07:28:11 PM PDT 24	Jul 30 07:31:08 PM PDT 24	3676665755 ps
T247	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1295992	Jul 30 07:30:45 PM PDT 24	Jul 30 07:32:24 PM PDT 24	1184329037 ps
T248	/workspace/coverage/default/27.sram_ctrl_stress_all.464224878	Jul 30 07:27:37 PM PDT 24	Jul 30 07:30:35 PM PDT 24	1580080240 ps
T136	/workspace/coverage/default/40.sram_ctrl_partial_access.6027505	Jul 30 07:29:49 PM PDT 24	Jul 30 07:29:59 PM PDT 24	422544739 ps
T249	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2330720300	Jul 30 07:31:19 PM PDT 24	Jul 30 07:31:24 PM PDT 24	865346001 ps
T250	/workspace/coverage/default/18.sram_ctrl_max_throughput.974156749	Jul 30 07:25:58 PM PDT 24	Jul 30 07:26:38 PM PDT 24	403977323 ps
T251	/workspace/coverage/default/8.sram_ctrl_multiple_keys.1940102206	Jul 30 07:24:28 PM PDT 24	Jul 30 07:46:13 PM PDT 24	8647567978 ps
T252	/workspace/coverage/default/12.sram_ctrl_executable.4158383707	Jul 30 07:25:03 PM PDT 24	Jul 30 07:39:41 PM PDT 24	13289340498 ps
T253	/workspace/coverage/default/25.sram_ctrl_bijection.3914726986	Jul 30 07:27:10 PM PDT 24	Jul 30 07:27:59 PM PDT 24	725767622 ps
T254	/workspace/coverage/default/15.sram_ctrl_ram_cfg.4040744084	Jul 30 07:25:32 PM PDT 24	Jul 30 07:25:33 PM PDT 24	89298760 ps
T255	/workspace/coverage/default/31.sram_ctrl_alert_test.805066587	Jul 30 07:28:14 PM PDT 24	Jul 30 07:28:15 PM PDT 24	16044995 ps
T256	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2148716526	Jul 30 07:30:03 PM PDT 24	Jul 30 07:33:56 PM PDT 24	4870970877 ps
T257	/workspace/coverage/default/8.sram_ctrl_alert_test.4002430311	Jul 30 07:24:34 PM PDT 24	Jul 30 07:24:34 PM PDT 24	108762050 ps
T258	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2786669750	Jul 30 07:26:36 PM PDT 24	Jul 30 07:30:34 PM PDT 24	18623099902 ps
T259	/workspace/coverage/default/38.sram_ctrl_regwen.3930423144	Jul 30 07:29:27 PM PDT 24	Jul 30 07:37:30 PM PDT 24	2409827082 ps
T260	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3120681340	Jul 30 07:23:58 PM PDT 24	Jul 30 07:25:54 PM PDT 24	2511773184 ps
T261	/workspace/coverage/default/27.sram_ctrl_multiple_keys.2702608596	Jul 30 07:27:25 PM PDT 24	Jul 30 07:31:48 PM PDT 24	8854510192 ps
T262	/workspace/coverage/default/39.sram_ctrl_stress_all.3726645473	Jul 30 07:29:45 PM PDT 24	Jul 30 08:33:51 PM PDT 24	22356728292 ps
T263	/workspace/coverage/default/42.sram_ctrl_mem_walk.2546714003	Jul 30 07:30:23 PM PDT 24	Jul 30 07:30:34 PM PDT 24	2303386709 ps
T264	/workspace/coverage/default/31.sram_ctrl_partial_access.1020703846	Jul 30 07:28:08 PM PDT 24	Jul 30 07:30:26 PM PDT 24	2540641150 ps
T265	/workspace/coverage/default/24.sram_ctrl_mem_walk.3385198636	Jul 30 07:27:05 PM PDT 24	Jul 30 07:27:10 PM PDT 24	355370249 ps
T266	/workspace/coverage/default/40.sram_ctrl_stress_all.3602969630	Jul 30 07:29:58 PM PDT 24	Jul 30 08:48:41 PM PDT 24	161606559659 ps
T267	/workspace/coverage/default/16.sram_ctrl_alert_test.1992993433	Jul 30 07:25:44 PM PDT 24	Jul 30 07:25:45 PM PDT 24	20050508 ps
T268	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2319963162	Jul 30 07:31:03 PM PDT 24	Jul 30 07:32:31 PM PDT 24	472614020 ps
T269	/workspace/coverage/default/37.sram_ctrl_multiple_keys.3050647293	Jul 30 07:29:10 PM PDT 24	Jul 30 07:31:28 PM PDT 24	7374486555 ps
T270	/workspace/coverage/default/29.sram_ctrl_partial_access.753445909	Jul 30 07:27:52 PM PDT 24	Jul 30 07:27:55 PM PDT 24	360574276 ps
T271	/workspace/coverage/default/1.sram_ctrl_lc_escalation.3255965992	Jul 30 07:23:56 PM PDT 24	Jul 30 07:24:03 PM PDT 24	549911363 ps
T272	/workspace/coverage/default/15.sram_ctrl_mem_walk.3583579219	Jul 30 07:25:35 PM PDT 24	Jul 30 07:25:43 PM PDT 24	267468274 ps
T273	/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1047706991	Jul 30 07:23:48 PM PDT 24	Jul 30 07:23:53 PM PDT 24	96845088 ps
T274	/workspace/coverage/default/34.sram_ctrl_max_throughput.3717865048	Jul 30 07:28:41 PM PDT 24	Jul 30 07:29:35 PM PDT 24	207057710 ps
T275	/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2917887569	Jul 30 07:24:23 PM PDT 24	Jul 30 07:30:10 PM PDT 24	31777478692 ps
T276	/workspace/coverage/default/24.sram_ctrl_mem_partial_access.3437571920	Jul 30 07:27:03 PM PDT 24	Jul 30 07:27:08 PM PDT 24	445165573 ps
T277	/workspace/coverage/default/9.sram_ctrl_stress_all.3068318110	Jul 30 07:24:46 PM PDT 24	Jul 30 08:46:29 PM PDT 24	11663175197 ps
T278	/workspace/coverage/default/11.sram_ctrl_executable.2981472424	Jul 30 07:24:56 PM PDT 24	Jul 30 07:25:15 PM PDT 24	2269158225 ps
T279	/workspace/coverage/default/49.sram_ctrl_multiple_keys.2872676322	Jul 30 07:31:31 PM PDT 24	Jul 30 07:49:11 PM PDT 24	3248361670 ps
T280	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3612102184	Jul 30 07:24:30 PM PDT 24	Jul 30 07:42:55 PM PDT 24	2953128031 ps
T281	/workspace/coverage/default/30.sram_ctrl_regwen.1584802224	Jul 30 07:28:07 PM PDT 24	Jul 30 07:37:20 PM PDT 24	7900237472 ps
T282	/workspace/coverage/default/3.sram_ctrl_mem_walk.2738438081	Jul 30 07:24:09 PM PDT 24	Jul 30 07:24:18 PM PDT 24	454893743 ps
T283	/workspace/coverage/default/48.sram_ctrl_bijection.2222488859	Jul 30 07:31:27 PM PDT 24	Jul 30 07:32:51 PM PDT 24	5531757981 ps
T284	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3470741500	Jul 30 07:24:14 PM PDT 24	Jul 30 07:27:36 PM PDT 24	2276343662 ps
T285	/workspace/coverage/default/39.sram_ctrl_multiple_keys.4244547918	Jul 30 07:29:33 PM PDT 24	Jul 30 07:38:08 PM PDT 24	1512961338 ps
T286	/workspace/coverage/default/43.sram_ctrl_smoke.3071909493	Jul 30 07:30:23 PM PDT 24	Jul 30 07:31:30 PM PDT 24	101499534 ps
T287	/workspace/coverage/default/34.sram_ctrl_mem_walk.1564035003	Jul 30 07:28:45 PM PDT 24	Jul 30 07:28:56 PM PDT 24	461516119 ps
T288	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2372622269	Jul 30 07:27:16 PM PDT 24	Jul 30 07:28:10 PM PDT 24	202274904 ps
T289	/workspace/coverage/default/47.sram_ctrl_stress_all.3614810547	Jul 30 07:31:18 PM PDT 24	Jul 30 08:16:37 PM PDT 24	135743396202 ps
T290	/workspace/coverage/default/2.sram_ctrl_stress_pipeline.532042815	Jul 30 07:23:57 PM PDT 24	Jul 30 07:28:08 PM PDT 24	13197894749 ps
T291	/workspace/coverage/default/32.sram_ctrl_alert_test.1766449242	Jul 30 07:28:27 PM PDT 24	Jul 30 07:28:28 PM PDT 24	12115171 ps
T292	/workspace/coverage/default/37.sram_ctrl_smoke.4210677160	Jul 30 07:29:11 PM PDT 24	Jul 30 07:29:13 PM PDT 24	79487689 ps
T293	/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2745230544	Jul 30 07:25:05 PM PDT 24	Jul 30 07:29:22 PM PDT 24	11350613001 ps
T294	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2198918904	Jul 30 07:25:01 PM PDT 24	Jul 30 07:27:43 PM PDT 24	3484111480 ps
T295	/workspace/coverage/default/3.sram_ctrl_bijection.3980568017	Jul 30 07:24:04 PM PDT 24	Jul 30 07:25:03 PM PDT 24	914872202 ps
T92	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.48503860	Jul 30 07:25:40 PM PDT 24	Jul 30 07:25:45 PM PDT 24	645927939 ps
T296	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4293676761	Jul 30 07:29:25 PM PDT 24	Jul 30 07:34:09 PM PDT 24	21976415591 ps
T297	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1205480699	Jul 30 07:31:25 PM PDT 24	Jul 30 07:31:31 PM PDT 24	189648075 ps
T298	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3434588586	Jul 30 07:24:24 PM PDT 24	Jul 30 07:24:28 PM PDT 24	106670283 ps
T299	/workspace/coverage/default/18.sram_ctrl_executable.1670339607	Jul 30 07:26:02 PM PDT 24	Jul 30 07:32:16 PM PDT 24	1149966740 ps
T300	/workspace/coverage/default/3.sram_ctrl_alert_test.3826692911	Jul 30 07:24:08 PM PDT 24	Jul 30 07:24:08 PM PDT 24	19306470 ps
T301	/workspace/coverage/default/41.sram_ctrl_max_throughput.1906977882	Jul 30 07:30:02 PM PDT 24	Jul 30 07:31:44 PM PDT 24	278756915 ps
T302	/workspace/coverage/default/42.sram_ctrl_max_throughput.3059700170	Jul 30 07:30:17 PM PDT 24	Jul 30 07:30:33 PM PDT 24	511435752 ps