Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44201756	1			T1	3071		T2	1846		T3	254
triple_byte_access	2447343	1			T2	1660		T3	4		T5	356
halfword_access	3670778	1			T2	2444		T3	9		T5	507
byte_access	4899024	1			T2	3218		T3	11		T5	659
zero_access	1233331	1			T2	878		T3	2		T5	169

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28164713

1

T1

1024

T2

5051

T3

148

auto[1]

28287519

1

T1

2047

T2

4995

T3

132

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22041827	1			T1	1024		T2	933		T3	137
auto[0]	triple_byte_access	1220311	1			T2	856		T3	1		T5	188
auto[0]	halfword_access	1832964	1			T2	1197		T3	3		T5	269
auto[0]	byte_access	2448612	1			T2	1638		T3	7		T5	336
auto[0]	zero_access	620999	1			T2	427		T5	96		T10	365
auto[1]	word_access	22159929	1			T1	2047		T2	913		T3	117
auto[1]	triple_byte_access	1227032	1			T2	804		T3	3		T5	168
auto[1]	halfword_access	1837814	1			T2	1247		T3	6		T5	238
auto[1]	byte_access	2450412	1			T2	1580		T3	4		T5	323
auto[1]	zero_access	612332	1			T2	451		T3	2		T5	73