Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	156392090	1			T1	6142		T2	19748		T3	14632
instr_valid_dis	116466282	1			T1	6142		T2	19748		T3	14632
instr_en	28029799	1			T24	129528		T18	2268		T20	17908

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12832496	1			T24	36384		T18	52826		T20	45688
sram_ifetch_valid_disable	115447668	1			T1	6142		T2	19748		T3	14632
sram_ifetch_enable	28111926	1			T24	105714		T18	67196		T20	159352

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	156392090	1			T1	6142		T2	19748		T3	14632
hw_debug_en_valid_off	115341201	1			T1	6142		T2	19748		T3	14632
hw_debug_en_on	26555431	1			T24	187294		T18	126396		T20	134642

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115447668	1			T1	6142		T2	19748		T3	14632
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99528816	1			T1	6142		T2	19748		T3	14632
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11296335	1			T24	46576		T21	8710		T26	26504
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4953639	1			T18	52826		T20	45688		T26	41796
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2035540	1			T20	27780		T26	41796		T87	183208
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1892931	1			T20	17908		T71	113714		T147	52804
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5320277	1			T24	18098		T26	39010		T71	257076
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2562244	1			T24	8862		T71	42798		T87	101928
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2058699	1			T24	9236		T26	39010		T71	214278
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10145048	1			T24	122846		T18	91272		T20	71438
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4083630	1			T24	28622		T20	71438		T26	6774
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4202356	1			T24	43500		T21	8710		T71	346756

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11555474	1			T24	55430		T18	2268		T21	92734
lc_exec_en	11090106	1			T24	46350		T18	35124		T20	63204
valid_exec_dis	111296028	1			T1	6142		T2	19748		T3	14632
invalid_exec_dis	40944422	1			T24	142098		T18	120022		T20	205040