Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Total tests in report: 1025

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
69.12	69.12	90.34	90.34	68.36	68.36	89.63	89.63	23.81	23.81	77.54	77.54	94.10	94.10	40.04	40.04	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2637454152
86.12	17.00	95.59	5.25	81.16	12.80	92.93	3.29	71.43	47.62	87.68	10.14	96.90	2.80	77.15	37.11	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3008546200
90.33	4.21	96.86	1.27	84.83	3.67	95.87	2.95	80.95	9.52	91.55	3.86	97.05	0.15	85.19	8.04	/workspace/coverage/default/23.sram_ctrl_stress_all.3988637341
93.50	3.17	97.88	1.02	85.19	0.36	95.98	0.10	100.00	19.05	93.00	1.45	97.05	0.00	85.37	0.18	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1363431754
94.42	0.92	98.05	0.17	85.78	0.59	96.19	0.21	100.00	0.00	93.72	0.72	97.05	0.00	90.13	4.75	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3483358961
95.18	0.76	98.22	0.17	87.56	1.78	96.39	0.21	100.00	0.00	94.69	0.97	97.05	0.00	92.32	2.19	/workspace/coverage/default/10.sram_ctrl_regwen.1807001707
95.88	0.71	98.39	0.17	89.34	1.78	97.16	0.76	100.00	0.00	95.41	0.72	97.64	0.59	93.24	0.91	/workspace/coverage/default/0.sram_ctrl_sec_cm.1430215517
96.35	0.47	99.07	0.68	90.05	0.71	98.47	1.32	100.00	0.00	95.65	0.24	97.79	0.15	93.42	0.18	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2529996327
96.61	0.26	99.07	0.00	90.28	0.24	98.54	0.07	100.00	0.00	95.65	0.00	98.97	1.18	93.78	0.37	/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1895210518
96.80	0.18	99.07	0.00	90.52	0.24	98.68	0.14	100.00	0.00	95.65	0.00	98.97	0.00	94.70	0.91	/workspace/coverage/default/44.sram_ctrl_lc_escalation.4212190619
96.94	0.14	99.07	0.00	90.52	0.00	98.75	0.07	100.00	0.00	95.65	0.00	98.97	0.00	95.61	0.91	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1039219582
97.07	0.13	99.15	0.08	90.52	0.00	99.58	0.83	100.00	0.00	95.65	0.00	98.97	0.00	95.61	0.00	/workspace/coverage/default/1.sram_ctrl_ram_cfg.336172393
97.17	0.10	99.15	0.00	90.52	0.00	99.58	0.00	100.00	0.00	95.65	0.00	98.97	0.00	96.34	0.73	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3914843179
97.26	0.09	99.15	0.00	90.64	0.12	99.58	0.00	100.00	0.00	96.14	0.48	98.97	0.00	96.34	0.00	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3016788878
97.33	0.07	99.15	0.00	91.00	0.36	99.72	0.14	100.00	0.00	96.14	0.00	98.97	0.00	96.34	0.00	/workspace/coverage/default/0.sram_ctrl_alert_test.24213296
97.38	0.05	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	98.97	0.00	96.71	0.37	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2901606155
97.44	0.05	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	98.97	0.00	97.07	0.37	/workspace/coverage/default/11.sram_ctrl_executable.1315975728
97.46	0.03	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	98.97	0.00	97.26	0.18	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3840981621
97.49	0.03	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	98.97	0.00	97.44	0.18	/workspace/coverage/default/16.sram_ctrl_executable.1112172759
97.51	0.02	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	99.12	0.15	97.44	0.00	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2228200459

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.738732253
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.390816104
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2635885390
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2254237109
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3212948477
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1519140201
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3370403082
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2619884500
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1116965128
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3307516912
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.689589192
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4278291215
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.944583527
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4220767521
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3643276064
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2920431782
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4172131300
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4028582788
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.48172124
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3972302601
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1606174947
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1553085130
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1648472774
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1363473210
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1342506949
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3118731382
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1934473448
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.868018268
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2296271907
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1939856961
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3413105685
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.867820583
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3533690847
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3829529900
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.19417351
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2568369571
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.344067835
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1177157577
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3155132573
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.384728721
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1850770835
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2140199140
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2729698515
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2598647241
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2369587441
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.219771658
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3632009514
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2346415831
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.39066986
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.773742629
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2585353894
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2257737925
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1426859598
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3757617662
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2040521698
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2680376822
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3956777632
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2011499410
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2544694512
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4067574514
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1225976717
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3766470200
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1127572032
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3187751258
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2885548015
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1643799360
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.435887030
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2198831861
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3390026533
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1778156357
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3005877367
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1805364043
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2073244502
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4190034126
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.446574620
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1395837922
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1948378063
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3751673769
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.215729749
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1159105684
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.201572583
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4198663178
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3121134043
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1079536792
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.955069523
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.335887078
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1773350220
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2842090922
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2906517080
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1842618802
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4125332657
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1482144912
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2325600895
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.521632957
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1163367090
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2743027751
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.214658945
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3231096370
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1814517947
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2027214606
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.972131474
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.15738586
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2730158687
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1913757258
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.115699771
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2255104723
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1654668556
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2546543406
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1343724461
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.633378441
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3158510840
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3190444792
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1829210824
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.204114234
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3306312413
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1337661847
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.724336860
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2938945007
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4058262306
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.41757184
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1131323783
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.156558404
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2764884010
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1267612080
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1041052395
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2262798690
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1843530443
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1266815239
/workspace/coverage/default/0.sram_ctrl_bijection.139652374
/workspace/coverage/default/0.sram_ctrl_executable.55918717
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1890118682
/workspace/coverage/default/0.sram_ctrl_max_throughput.76432869
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1398881504
/workspace/coverage/default/0.sram_ctrl_mem_walk.4210201396
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1488024797
/workspace/coverage/default/0.sram_ctrl_partial_access.805806393
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2265607923
/workspace/coverage/default/0.sram_ctrl_ram_cfg.4001827924
/workspace/coverage/default/0.sram_ctrl_regwen.1503314294
/workspace/coverage/default/0.sram_ctrl_smoke.886147771
/workspace/coverage/default/0.sram_ctrl_stress_all.430058925
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.736084606
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2758414214
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.122485622
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2772345474
/workspace/coverage/default/1.sram_ctrl_alert_test.605787016
/workspace/coverage/default/1.sram_ctrl_bijection.968369054
/workspace/coverage/default/1.sram_ctrl_executable.565308361
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1897429973
/workspace/coverage/default/1.sram_ctrl_max_throughput.1827291900
/workspace/coverage/default/1.sram_ctrl_mem_walk.3835475155
/workspace/coverage/default/1.sram_ctrl_multiple_keys.493002038
/workspace/coverage/default/1.sram_ctrl_partial_access.1072116175
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3500696711
/workspace/coverage/default/1.sram_ctrl_regwen.622477741
/workspace/coverage/default/1.sram_ctrl_sec_cm.406372670
/workspace/coverage/default/1.sram_ctrl_smoke.464020590
/workspace/coverage/default/1.sram_ctrl_stress_all.323867165
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.833777368
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1293008260
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1377535951
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3993737218
/workspace/coverage/default/10.sram_ctrl_alert_test.433431322
/workspace/coverage/default/10.sram_ctrl_bijection.2017981836
/workspace/coverage/default/10.sram_ctrl_executable.493478264
/workspace/coverage/default/10.sram_ctrl_lc_escalation.748575104
/workspace/coverage/default/10.sram_ctrl_max_throughput.2677362996
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1730297850
/workspace/coverage/default/10.sram_ctrl_mem_walk.3489237748
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1813343617
/workspace/coverage/default/10.sram_ctrl_partial_access.3600137964
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2482864968
/workspace/coverage/default/10.sram_ctrl_ram_cfg.4043242581
/workspace/coverage/default/10.sram_ctrl_smoke.1281475472
/workspace/coverage/default/10.sram_ctrl_stress_all.3476119572
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2826927317
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.4264211669
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2133890785
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.446927657
/workspace/coverage/default/11.sram_ctrl_alert_test.3803499718
/workspace/coverage/default/11.sram_ctrl_bijection.2862302768
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2193276911
/workspace/coverage/default/11.sram_ctrl_max_throughput.2062046785
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1760919131
/workspace/coverage/default/11.sram_ctrl_mem_walk.2714483330
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3377993789
/workspace/coverage/default/11.sram_ctrl_partial_access.84865292
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.373342443
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3977302798
/workspace/coverage/default/11.sram_ctrl_regwen.1508165570
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/workspace/coverage/default/42.sram_ctrl_regwen.126406728
/workspace/coverage/default/42.sram_ctrl_smoke.52909172
/workspace/coverage/default/42.sram_ctrl_stress_all.2038846317
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2414472643
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2513806062
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.796169116
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1836915790
/workspace/coverage/default/43.sram_ctrl_alert_test.2745392570
/workspace/coverage/default/43.sram_ctrl_bijection.789411572
/workspace/coverage/default/43.sram_ctrl_executable.3193202704
/workspace/coverage/default/43.sram_ctrl_lc_escalation.100237560
/workspace/coverage/default/43.sram_ctrl_max_throughput.1270722704
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.871295331
/workspace/coverage/default/43.sram_ctrl_mem_walk.422036253
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3546060902
/workspace/coverage/default/43.sram_ctrl_partial_access.3718162849
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.668384278
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3848991873
/workspace/coverage/default/43.sram_ctrl_regwen.447755703
/workspace/coverage/default/43.sram_ctrl_smoke.4258765893
/workspace/coverage/default/43.sram_ctrl_stress_all.1548786109
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2418708857
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.237153395
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1760379978
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3546537982
/workspace/coverage/default/44.sram_ctrl_alert_test.575655555
/workspace/coverage/default/44.sram_ctrl_bijection.1999539625
/workspace/coverage/default/44.sram_ctrl_executable.2139449169
/workspace/coverage/default/44.sram_ctrl_max_throughput.3050075920
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2497230667
/workspace/coverage/default/44.sram_ctrl_mem_walk.1646923422
/workspace/coverage/default/44.sram_ctrl_multiple_keys.789135432
/workspace/coverage/default/44.sram_ctrl_partial_access.3457836655
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.509158438
/workspace/coverage/default/44.sram_ctrl_ram_cfg.336090019
/workspace/coverage/default/44.sram_ctrl_regwen.3187243549
/workspace/coverage/default/44.sram_ctrl_smoke.2786411152
/workspace/coverage/default/44.sram_ctrl_stress_all.1200638764
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1992864960
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2183050719
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3222309545
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3582994020
/workspace/coverage/default/45.sram_ctrl_alert_test.2081888210
/workspace/coverage/default/45.sram_ctrl_bijection.1588878173
/workspace/coverage/default/45.sram_ctrl_executable.3738319299
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1366557764
/workspace/coverage/default/45.sram_ctrl_max_throughput.1545347287
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3913660498
/workspace/coverage/default/45.sram_ctrl_mem_walk.3429248443
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3082640711
/workspace/coverage/default/45.sram_ctrl_partial_access.1646213280
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2243730042
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1652544970
/workspace/coverage/default/45.sram_ctrl_regwen.4046357132
/workspace/coverage/default/45.sram_ctrl_smoke.2063451347
/workspace/coverage/default/45.sram_ctrl_stress_all.2295711001
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2951247894
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.924296854
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3498142429
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1466235357
/workspace/coverage/default/46.sram_ctrl_alert_test.721228248
/workspace/coverage/default/46.sram_ctrl_bijection.251899371
/workspace/coverage/default/46.sram_ctrl_executable.3086709584
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2029128605
/workspace/coverage/default/46.sram_ctrl_max_throughput.1781078666
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.290779150
/workspace/coverage/default/46.sram_ctrl_mem_walk.3451215129
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2097907223
/workspace/coverage/default/46.sram_ctrl_partial_access.445011695
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.945374638
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2571824065
/workspace/coverage/default/46.sram_ctrl_regwen.1576906804
/workspace/coverage/default/46.sram_ctrl_smoke.3010431051
/workspace/coverage/default/46.sram_ctrl_stress_all.3658546344
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.975599798
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1135687689
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4145238168
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.90987171
/workspace/coverage/default/47.sram_ctrl_alert_test.3735266223
/workspace/coverage/default/47.sram_ctrl_bijection.2368687376
/workspace/coverage/default/47.sram_ctrl_executable.3747961554
/workspace/coverage/default/47.sram_ctrl_lc_escalation.977857328
/workspace/coverage/default/47.sram_ctrl_max_throughput.3194771940
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3956744354
/workspace/coverage/default/47.sram_ctrl_mem_walk.489502756
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3575813875
/workspace/coverage/default/47.sram_ctrl_partial_access.3562590849
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2064720188
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2001134186
/workspace/coverage/default/47.sram_ctrl_regwen.1170406008
/workspace/coverage/default/47.sram_ctrl_smoke.3442970646
/workspace/coverage/default/47.sram_ctrl_stress_all.1744488294
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3699797530
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2769324196
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3792597384
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3742124030
/workspace/coverage/default/48.sram_ctrl_alert_test.516109184
/workspace/coverage/default/48.sram_ctrl_bijection.3574302154
/workspace/coverage/default/48.sram_ctrl_executable.348352396
/workspace/coverage/default/48.sram_ctrl_lc_escalation.690183649
/workspace/coverage/default/48.sram_ctrl_max_throughput.2447322682
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1244485401
/workspace/coverage/default/48.sram_ctrl_mem_walk.1818164241
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1776162792
/workspace/coverage/default/48.sram_ctrl_partial_access.381354850
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2839072471
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1682884459
/workspace/coverage/default/48.sram_ctrl_regwen.18909403
/workspace/coverage/default/48.sram_ctrl_smoke.279691846
/workspace/coverage/default/48.sram_ctrl_stress_all.1607764278
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3544208666
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2884198417
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3777536647
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.692301070
/workspace/coverage/default/49.sram_ctrl_alert_test.2979897156
/workspace/coverage/default/49.sram_ctrl_bijection.2517554171
/workspace/coverage/default/49.sram_ctrl_executable.3504273455
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1066511955
/workspace/coverage/default/49.sram_ctrl_max_throughput.2174232813
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3644617309
/workspace/coverage/default/49.sram_ctrl_mem_walk.335038388
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1345708710
/workspace/coverage/default/49.sram_ctrl_partial_access.2357200255
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1747897925
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1408680231
/workspace/coverage/default/49.sram_ctrl_regwen.1704674766
/workspace/coverage/default/49.sram_ctrl_smoke.2192487285
/workspace/coverage/default/49.sram_ctrl_stress_all.378647055
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4132365720
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3577488667
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.313483251
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1493554604
/workspace/coverage/default/5.sram_ctrl_alert_test.536703209
/workspace/coverage/default/5.sram_ctrl_bijection.1099127876
/workspace/coverage/default/5.sram_ctrl_executable.1516374317
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2567628444
/workspace/coverage/default/5.sram_ctrl_max_throughput.1214575936
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2778222958
/workspace/coverage/default/5.sram_ctrl_mem_walk.1846835415
/workspace/coverage/default/5.sram_ctrl_multiple_keys.4027233844
/workspace/coverage/default/5.sram_ctrl_partial_access.890598941
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3924914688
/workspace/coverage/default/5.sram_ctrl_ram_cfg.942814343
/workspace/coverage/default/5.sram_ctrl_regwen.1794962930
/workspace/coverage/default/5.sram_ctrl_smoke.2545204111
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3138727147
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1643644980
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1555263316
/workspace/coverage/default/6.sram_ctrl_alert_test.3697419211
/workspace/coverage/default/6.sram_ctrl_bijection.217275979
/workspace/coverage/default/6.sram_ctrl_executable.2067192949
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1294717136
/workspace/coverage/default/6.sram_ctrl_max_throughput.2960679222
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3589319201
/workspace/coverage/default/6.sram_ctrl_mem_walk.3497118678
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1843488239
/workspace/coverage/default/6.sram_ctrl_partial_access.3821556764
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.175419065
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1173358415
/workspace/coverage/default/6.sram_ctrl_regwen.2711373622
/workspace/coverage/default/6.sram_ctrl_smoke.2386327588
/workspace/coverage/default/6.sram_ctrl_stress_all.915460573
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3206325509
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3437907081
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.372879522
/workspace/coverage/default/7.sram_ctrl_alert_test.4069540741
/workspace/coverage/default/7.sram_ctrl_bijection.164326129
/workspace/coverage/default/7.sram_ctrl_executable.80132501
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2525663820
/workspace/coverage/default/7.sram_ctrl_max_throughput.1348438247
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3698586759
/workspace/coverage/default/7.sram_ctrl_mem_walk.2071786337
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4142297254
/workspace/coverage/default/7.sram_ctrl_partial_access.1539386044
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4294328072
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2129462963
/workspace/coverage/default/7.sram_ctrl_regwen.2111840390
/workspace/coverage/default/7.sram_ctrl_smoke.3458558643
/workspace/coverage/default/7.sram_ctrl_stress_all.2609791879
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1666576457
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.4255699906
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1890921769
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2747153232
/workspace/coverage/default/8.sram_ctrl_alert_test.2676773058
/workspace/coverage/default/8.sram_ctrl_bijection.914153583
/workspace/coverage/default/8.sram_ctrl_executable.1970685046
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3556147315
/workspace/coverage/default/8.sram_ctrl_max_throughput.2706598802
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.930748771
/workspace/coverage/default/8.sram_ctrl_mem_walk.4017570314
/workspace/coverage/default/8.sram_ctrl_partial_access.893959450
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3626830720
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1041000045
/workspace/coverage/default/8.sram_ctrl_regwen.3998639938
/workspace/coverage/default/8.sram_ctrl_smoke.628223709
/workspace/coverage/default/8.sram_ctrl_stress_all.3073177027
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1757107122
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3196982285
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2550760008
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.564440004
/workspace/coverage/default/9.sram_ctrl_alert_test.4162471392
/workspace/coverage/default/9.sram_ctrl_bijection.1585583159
/workspace/coverage/default/9.sram_ctrl_executable.548608587
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3257660504
/workspace/coverage/default/9.sram_ctrl_max_throughput.1953336879
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.440235045
/workspace/coverage/default/9.sram_ctrl_mem_walk.3755793482
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2212918262
/workspace/coverage/default/9.sram_ctrl_partial_access.3258595475
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1073468489
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1511772420
/workspace/coverage/default/9.sram_ctrl_regwen.2949884737
/workspace/coverage/default/9.sram_ctrl_smoke.358743876
/workspace/coverage/default/9.sram_ctrl_stress_all.860190987
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1743765671
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1557277318
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3923100237

Total test records in report: 1025

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/13.sram_ctrl_mem_walk.1750978578	Jul 31 07:39:38 PM PDT 24	Jul 31 07:39:44 PM PDT 24	2242120913 ps
T2	/workspace/coverage/default/10.sram_ctrl_max_throughput.2677362996	Jul 31 07:39:32 PM PDT 24	Jul 31 07:41:50 PM PDT 24	266582093 ps
T3	/workspace/coverage/default/6.sram_ctrl_smoke.2386327588	Jul 31 07:39:05 PM PDT 24	Jul 31 07:40:10 PM PDT 24	414243371 ps
T4	/workspace/coverage/default/15.sram_ctrl_mem_walk.58413508	Jul 31 07:39:48 PM PDT 24	Jul 31 07:39:54 PM PDT 24	186577709 ps
T5	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2637454152	Jul 31 07:41:39 PM PDT 24	Jul 31 07:50:47 PM PDT 24	2780687991 ps
T9	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2529996327	Jul 31 07:39:10 PM PDT 24	Jul 31 07:43:20 PM PDT 24	15916731019 ps
T10	/workspace/coverage/default/0.sram_ctrl_alert_test.24213296	Jul 31 07:38:43 PM PDT 24	Jul 31 07:38:44 PM PDT 24	46446728 ps
T11	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.175419065	Jul 31 07:39:06 PM PDT 24	Jul 31 07:44:44 PM PDT 24	13299781598 ps
T12	/workspace/coverage/default/21.sram_ctrl_alert_test.3475645712	Jul 31 07:40:24 PM PDT 24	Jul 31 07:40:25 PM PDT 24	13267616 ps
T13	/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.4041302151	Jul 31 07:41:24 PM PDT 24	Jul 31 07:43:29 PM PDT 24	6215115350 ps
T42	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2755372744	Jul 31 07:41:49 PM PDT 24	Jul 31 07:42:36 PM PDT 24	485664637 ps
T43	/workspace/coverage/default/26.sram_ctrl_smoke.1269086225	Jul 31 07:40:53 PM PDT 24	Jul 31 07:41:15 PM PDT 24	271392688 ps
T47	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.372879522	Jul 31 07:39:06 PM PDT 24	Jul 31 07:42:10 PM PDT 24	607718300 ps
T14	/workspace/coverage/default/14.sram_ctrl_alert_test.1346040503	Jul 31 07:39:43 PM PDT 24	Jul 31 07:39:43 PM PDT 24	13511831 ps
T27	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1752705212	Jul 31 07:40:53 PM PDT 24	Jul 31 07:46:48 PM PDT 24	19779988771 ps
T46	/workspace/coverage/default/37.sram_ctrl_partial_access.1609985595	Jul 31 07:42:19 PM PDT 24	Jul 31 07:42:27 PM PDT 24	1774502159 ps
T44	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1363431754	Jul 31 07:38:49 PM PDT 24	Jul 31 07:38:56 PM PDT 24	196923822 ps
T65	/workspace/coverage/default/48.sram_ctrl_max_throughput.2447322682	Jul 31 07:44:10 PM PDT 24	Jul 31 07:45:06 PM PDT 24	107110043 ps
T28	/workspace/coverage/default/31.sram_ctrl_ram_cfg.213548124	Jul 31 07:41:31 PM PDT 24	Jul 31 07:41:32 PM PDT 24	53409181 ps
T57	/workspace/coverage/default/40.sram_ctrl_mem_walk.135798540	Jul 31 07:42:53 PM PDT 24	Jul 31 07:42:58 PM PDT 24	356010658 ps
T53	/workspace/coverage/default/46.sram_ctrl_mem_walk.3451215129	Jul 31 07:43:57 PM PDT 24	Jul 31 07:44:03 PM PDT 24	541184457 ps
T66	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.786108096	Jul 31 07:40:00 PM PDT 24	Jul 31 07:40:03 PM PDT 24	73453686 ps
T24	/workspace/coverage/default/11.sram_ctrl_executable.1315975728	Jul 31 07:39:29 PM PDT 24	Jul 31 07:56:01 PM PDT 24	25388686606 ps
T6	/workspace/coverage/default/4.sram_ctrl_lc_escalation.2294749494	Jul 31 07:38:58 PM PDT 24	Jul 31 07:39:05 PM PDT 24	1359261120 ps
T67	/workspace/coverage/default/18.sram_ctrl_smoke.3266025293	Jul 31 07:39:56 PM PDT 24	Jul 31 07:40:09 PM PDT 24	1230511072 ps
T45	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1039219582	Jul 31 07:43:08 PM PDT 24	Jul 31 07:50:44 PM PDT 24	20311255025 ps
T52	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.4063443619	Jul 31 07:39:29 PM PDT 24	Jul 31 07:39:33 PM PDT 24	185005245 ps
T75	/workspace/coverage/default/7.sram_ctrl_smoke.3458558643	Jul 31 07:39:07 PM PDT 24	Jul 31 07:39:11 PM PDT 24	80751644 ps
T23	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3008546200	Jul 31 07:41:00 PM PDT 24	Jul 31 07:41:24 PM PDT 24	674780588 ps
T18	/workspace/coverage/default/1.sram_ctrl_regwen.622477741	Jul 31 07:38:48 PM PDT 24	Jul 31 07:53:39 PM PDT 24	11215842071 ps
T76	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3498142429	Jul 31 07:43:50 PM PDT 24	Jul 31 07:44:43 PM PDT 24	241788595 ps
T29	/workspace/coverage/default/16.sram_ctrl_ram_cfg.1570076218	Jul 31 07:39:51 PM PDT 24	Jul 31 07:39:52 PM PDT 24	57389298 ps
T77	/workspace/coverage/default/21.sram_ctrl_smoke.3843312771	Jul 31 07:40:15 PM PDT 24	Jul 31 07:40:17 PM PDT 24	193503466 ps
T82	/workspace/coverage/default/30.sram_ctrl_multiple_keys.1205428469	Jul 31 07:41:20 PM PDT 24	Jul 31 07:55:08 PM PDT 24	25951107204 ps
T83	/workspace/coverage/default/26.sram_ctrl_max_throughput.3244650884	Jul 31 07:40:51 PM PDT 24	Jul 31 07:42:52 PM PDT 24	529646515 ps
T84	/workspace/coverage/default/41.sram_ctrl_max_throughput.4167202909	Jul 31 07:43:01 PM PDT 24	Jul 31 07:43:32 PM PDT 24	87489412 ps
T85	/workspace/coverage/default/35.sram_ctrl_smoke.2240230766	Jul 31 07:41:56 PM PDT 24	Jul 31 07:42:07 PM PDT 24	2550085123 ps
T86	/workspace/coverage/default/9.sram_ctrl_alert_test.4162471392	Jul 31 07:39:20 PM PDT 24	Jul 31 07:39:21 PM PDT 24	14683349 ps
T19	/workspace/coverage/default/48.sram_ctrl_bijection.3574302154	Jul 31 07:44:16 PM PDT 24	Jul 31 07:44:40 PM PDT 24	4103987813 ps
T120	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2839072471	Jul 31 07:44:08 PM PDT 24	Jul 31 07:48:28 PM PDT 24	3633413076 ps
T7	/workspace/coverage/default/49.sram_ctrl_lc_escalation.1066511955	Jul 31 07:44:23 PM PDT 24	Jul 31 07:44:25 PM PDT 24	228403835 ps
T8	/workspace/coverage/default/20.sram_ctrl_lc_escalation.996292457	Jul 31 07:40:17 PM PDT 24	Jul 31 07:40:25 PM PDT 24	2581326974 ps
T30	/workspace/coverage/default/1.sram_ctrl_ram_cfg.336172393	Jul 31 07:38:49 PM PDT 24	Jul 31 07:38:50 PM PDT 24	30413267 ps
T20	/workspace/coverage/default/25.sram_ctrl_regwen.4045374416	Jul 31 07:40:43 PM PDT 24	Jul 31 07:58:59 PM PDT 24	17572263526 ps
T21	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3839757779	Jul 31 07:41:48 PM PDT 24	Jul 31 07:53:42 PM PDT 24	6712840846 ps
T26	/workspace/coverage/default/23.sram_ctrl_stress_all.3988637341	Jul 31 07:40:38 PM PDT 24	Jul 31 08:39:17 PM PDT 24	43350041831 ps
T48	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.446927657	Jul 31 07:39:47 PM PDT 24	Jul 31 07:44:37 PM PDT 24	11663554204 ps
T71	/workspace/coverage/default/2.sram_ctrl_stress_all.1521231171	Jul 31 07:38:53 PM PDT 24	Jul 31 09:23:34 PM PDT 24	310471189653 ps
T22	/workspace/coverage/default/44.sram_ctrl_lc_escalation.4212190619	Jul 31 07:43:32 PM PDT 24	Jul 31 07:43:38 PM PDT 24	817172800 ps
T152	/workspace/coverage/default/19.sram_ctrl_partial_access.3530562162	Jul 31 07:40:10 PM PDT 24	Jul 31 07:40:27 PM PDT 24	495929926 ps
T153	/workspace/coverage/default/9.sram_ctrl_max_throughput.1953336879	Jul 31 07:39:14 PM PDT 24	Jul 31 07:39:16 PM PDT 24	253739883 ps
T154	/workspace/coverage/default/30.sram_ctrl_partial_access.1498036668	Jul 31 07:41:20 PM PDT 24	Jul 31 07:41:22 PM PDT 24	99631925 ps
T121	/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.675056441	Jul 31 07:41:51 PM PDT 24	Jul 31 07:50:32 PM PDT 24	90298906883 ps
T155	/workspace/coverage/default/17.sram_ctrl_ram_cfg.403567425	Jul 31 07:39:58 PM PDT 24	Jul 31 07:39:59 PM PDT 24	28635096 ps
T58	/workspace/coverage/default/18.sram_ctrl_mem_walk.2396017404	Jul 31 07:40:03 PM PDT 24	Jul 31 07:40:13 PM PDT 24	460899603 ps
T102	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3774242252	Jul 31 07:40:17 PM PDT 24	Jul 31 07:40:20 PM PDT 24	393520108 ps
T151	/workspace/coverage/default/38.sram_ctrl_multiple_keys.2917069673	Jul 31 07:42:28 PM PDT 24	Jul 31 07:50:52 PM PDT 24	15998241212 ps
T87	/workspace/coverage/default/37.sram_ctrl_stress_all.3211528847	Jul 31 07:42:22 PM PDT 24	Jul 31 08:57:55 PM PDT 24	696318370307 ps
T156	/workspace/coverage/default/36.sram_ctrl_partial_access.1415589079	Jul 31 07:42:11 PM PDT 24	Jul 31 07:42:49 PM PDT 24	295343221 ps
T122	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.971254195	Jul 31 07:40:00 PM PDT 24	Jul 31 07:47:59 PM PDT 24	83398826697 ps
T25	/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3257176100	Jul 31 07:43:02 PM PDT 24	Jul 31 07:45:31 PM PDT 24	800904562 ps
T157	/workspace/coverage/default/9.sram_ctrl_executable.548608587	Jul 31 07:39:18 PM PDT 24	Jul 31 07:58:31 PM PDT 24	23711218573 ps
T158	/workspace/coverage/default/30.sram_ctrl_ram_cfg.806326171	Jul 31 07:41:20 PM PDT 24	Jul 31 07:41:21 PM PDT 24	86580947 ps
T147	/workspace/coverage/default/34.sram_ctrl_executable.328695756	Jul 31 07:41:49 PM PDT 24	Jul 31 07:49:23 PM PDT 24	34047652115 ps
T88	/workspace/coverage/default/32.sram_ctrl_lc_escalation.496525227	Jul 31 07:41:31 PM PDT 24	Jul 31 07:41:37 PM PDT 24	1065171112 ps
T159	/workspace/coverage/default/32.sram_ctrl_ram_cfg.3674766064	Jul 31 07:41:42 PM PDT 24	Jul 31 07:41:43 PM PDT 24	33082903 ps
T160	/workspace/coverage/default/5.sram_ctrl_lc_escalation.2567628444	Jul 31 07:38:59 PM PDT 24	Jul 31 07:39:02 PM PDT 24	462170428 ps
T161	/workspace/coverage/default/12.sram_ctrl_partial_access.3009628254	Jul 31 07:39:30 PM PDT 24	Jul 31 07:39:39 PM PDT 24	180574052 ps
T59	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3206325509	Jul 31 07:39:07 PM PDT 24	Jul 31 07:41:35 PM PDT 24	2657459116 ps
T162	/workspace/coverage/default/14.sram_ctrl_ram_cfg.4166046021	Jul 31 07:39:41 PM PDT 24	Jul 31 07:39:42 PM PDT 24	88685641 ps
T54	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.226955463	Jul 31 07:42:42 PM PDT 24	Jul 31 07:42:48 PM PDT 24	227805031 ps
T148	/workspace/coverage/default/21.sram_ctrl_lc_escalation.48108106	Jul 31 07:40:28 PM PDT 24	Jul 31 07:40:33 PM PDT 24	400190312 ps
T163	/workspace/coverage/default/7.sram_ctrl_alert_test.4069540741	Jul 31 07:39:14 PM PDT 24	Jul 31 07:39:15 PM PDT 24	189830546 ps
T143	/workspace/coverage/default/10.sram_ctrl_regwen.1807001707	Jul 31 07:39:19 PM PDT 24	Jul 31 07:53:03 PM PDT 24	49899676943 ps
T123	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.970729275	Jul 31 07:42:38 PM PDT 24	Jul 31 07:45:14 PM PDT 24	6691058096 ps
T164	/workspace/coverage/default/26.sram_ctrl_bijection.1211863023	Jul 31 07:40:51 PM PDT 24	Jul 31 07:41:46 PM PDT 24	5108101965 ps
T55	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.709626928	Jul 31 07:39:01 PM PDT 24	Jul 31 07:39:07 PM PDT 24	786021116 ps
T165	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.4207461590	Jul 31 07:40:46 PM PDT 24	Jul 31 07:44:34 PM PDT 24	6259975620 ps
T166	/workspace/coverage/default/10.sram_ctrl_multiple_keys.1813343617	Jul 31 07:39:22 PM PDT 24	Jul 31 07:50:16 PM PDT 24	10536314904 ps
T150	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2787394158	Jul 31 07:42:51 PM PDT 24	Jul 31 07:45:07 PM PDT 24	398445488 ps
T78	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3699797530	Jul 31 07:44:09 PM PDT 24	Jul 31 07:46:29 PM PDT 24	1650724647 ps
T167	/workspace/coverage/default/12.sram_ctrl_mem_walk.146814505	Jul 31 07:39:26 PM PDT 24	Jul 31 07:39:35 PM PDT 24	716777224 ps
T144	/workspace/coverage/default/47.sram_ctrl_executable.3747961554	Jul 31 07:44:04 PM PDT 24	Jul 31 07:49:43 PM PDT 24	18513919449 ps
T168	/workspace/coverage/default/7.sram_ctrl_stress_all.2609791879	Jul 31 07:39:14 PM PDT 24	Jul 31 08:20:53 PM PDT 24	178592974317 ps
T169	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.884739609	Jul 31 07:41:09 PM PDT 24	Jul 31 07:47:23 PM PDT 24	12769380520 ps
T79	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.833777368	Jul 31 07:38:50 PM PDT 24	Jul 31 07:39:07 PM PDT 24	220754445 ps
T170	/workspace/coverage/default/25.sram_ctrl_bijection.3769880465	Jul 31 07:40:45 PM PDT 24	Jul 31 07:41:54 PM PDT 24	8748183640 ps
T171	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3724843227	Jul 31 07:42:22 PM PDT 24	Jul 31 07:45:09 PM PDT 24	6534303349 ps
T172	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3792597384	Jul 31 07:44:01 PM PDT 24	Jul 31 07:46:31 PM PDT 24	153739044 ps
T173	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3835674858	Jul 31 07:38:58 PM PDT 24	Jul 31 07:47:39 PM PDT 24	19174263438 ps
T174	/workspace/coverage/default/16.sram_ctrl_mem_walk.3344170465	Jul 31 07:39:46 PM PDT 24	Jul 31 07:39:52 PM PDT 24	873702347 ps
T103	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.250009363	Jul 31 07:41:42 PM PDT 24	Jul 31 07:41:47 PM PDT 24	98599485 ps
T175	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3706245893	Jul 31 07:42:15 PM PDT 24	Jul 31 07:44:05 PM PDT 24	271223242 ps
T176	/workspace/coverage/default/47.sram_ctrl_max_throughput.3194771940	Jul 31 07:44:01 PM PDT 24	Jul 31 07:44:05 PM PDT 24	51749537 ps
T15	/workspace/coverage/default/0.sram_ctrl_sec_cm.1430215517	Jul 31 07:38:39 PM PDT 24	Jul 31 07:38:41 PM PDT 24	574651746 ps
T33	/workspace/coverage/default/38.sram_ctrl_partial_access.1136582210	Jul 31 07:42:22 PM PDT 24	Jul 31 07:42:34 PM PDT 24	885024293 ps
T34	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1773626533	Jul 31 07:40:03 PM PDT 24	Jul 31 07:46:14 PM PDT 24	7318060613 ps
T35	/workspace/coverage/default/17.sram_ctrl_multiple_keys.1578945570	Jul 31 07:39:56 PM PDT 24	Jul 31 07:45:31 PM PDT 24	2068139271 ps
T36	/workspace/coverage/default/10.sram_ctrl_ram_cfg.4043242581	Jul 31 07:39:22 PM PDT 24	Jul 31 07:39:23 PM PDT 24	27668226 ps
T37	/workspace/coverage/default/36.sram_ctrl_max_throughput.1490354037	Jul 31 07:42:10 PM PDT 24	Jul 31 07:43:04 PM PDT 24	1176016494 ps
T38	/workspace/coverage/default/23.sram_ctrl_bijection.2382994614	Jul 31 07:40:38 PM PDT 24	Jul 31 07:41:47 PM PDT 24	1070441700 ps
T39	/workspace/coverage/default/33.sram_ctrl_max_throughput.4253511114	Jul 31 07:41:41 PM PDT 24	Jul 31 07:41:59 PM PDT 24	137954051 ps
T40	/workspace/coverage/default/24.sram_ctrl_partial_access.753011487	Jul 31 07:40:37 PM PDT 24	Jul 31 07:40:43 PM PDT 24	302840188 ps
T41	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3358633399	Jul 31 07:41:22 PM PDT 24	Jul 31 07:44:23 PM PDT 24	10412818515 ps
T177	/workspace/coverage/default/14.sram_ctrl_max_throughput.2954530849	Jul 31 07:39:49 PM PDT 24	Jul 31 07:40:33 PM PDT 24	420847970 ps
T145	/workspace/coverage/default/4.sram_ctrl_regwen.1444526182	Jul 31 07:38:57 PM PDT 24	Jul 31 08:02:28 PM PDT 24	13781321793 ps
T60	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4132365720	Jul 31 07:44:23 PM PDT 24	Jul 31 07:45:41 PM PDT 24	277044642 ps
T178	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2482864968	Jul 31 07:39:23 PM PDT 24	Jul 31 07:43:20 PM PDT 24	9346401860 ps
T179	/workspace/coverage/default/10.sram_ctrl_lc_escalation.748575104	Jul 31 07:39:21 PM PDT 24	Jul 31 07:39:27 PM PDT 24	2432440585 ps
T180	/workspace/coverage/default/44.sram_ctrl_stress_all.1200638764	Jul 31 07:43:38 PM PDT 24	Jul 31 08:34:29 PM PDT 24	20020729049 ps
T181	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1279142577	Jul 31 07:41:44 PM PDT 24	Jul 31 07:44:09 PM PDT 24	152744176 ps
T61	/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1085380463	Jul 31 07:41:21 PM PDT 24	Jul 31 07:41:27 PM PDT 24	172226550 ps
T182	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1551529144	Jul 31 07:39:33 PM PDT 24	Jul 31 07:39:39 PM PDT 24	606810834 ps
T183	/workspace/coverage/default/19.sram_ctrl_mem_walk.3393470296	Jul 31 07:40:09 PM PDT 24	Jul 31 07:40:20 PM PDT 24	855239309 ps
T56	/workspace/coverage/default/44.sram_ctrl_mem_walk.1646923422	Jul 31 07:43:31 PM PDT 24	Jul 31 07:43:43 PM PDT 24	2707501225 ps
T184	/workspace/coverage/default/47.sram_ctrl_partial_access.3562590849	Jul 31 07:44:03 PM PDT 24	Jul 31 07:45:28 PM PDT 24	2405252303 ps
T80	/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.975599798	Jul 31 07:43:58 PM PDT 24	Jul 31 07:44:06 PM PDT 24	288202924 ps
T185	/workspace/coverage/default/19.sram_ctrl_ram_cfg.1789917560	Jul 31 07:40:09 PM PDT 24	Jul 31 07:40:10 PM PDT 24	129747991 ps
T186	/workspace/coverage/default/14.sram_ctrl_smoke.4216873206	Jul 31 07:39:35 PM PDT 24	Jul 31 07:39:42 PM PDT 24	427266446 ps
T146	/workspace/coverage/default/2.sram_ctrl_executable.1184592585	Jul 31 07:38:50 PM PDT 24	Jul 31 07:43:23 PM PDT 24	59910887195 ps
T187	/workspace/coverage/default/45.sram_ctrl_smoke.2063451347	Jul 31 07:43:38 PM PDT 24	Jul 31 07:43:59 PM PDT 24	81556861 ps
T188	/workspace/coverage/default/39.sram_ctrl_executable.3937116404	Jul 31 07:42:37 PM PDT 24	Jul 31 08:02:53 PM PDT 24	3013371595 ps
T189	/workspace/coverage/default/6.sram_ctrl_mem_walk.3497118678	Jul 31 07:39:08 PM PDT 24	Jul 31 07:39:19 PM PDT 24	929027862 ps
T62	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.3096781841	Jul 31 07:40:02 PM PDT 24	Jul 31 07:40:07 PM PDT 24	183953314 ps
T190	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.1941556487	Jul 31 07:41:20 PM PDT 24	Jul 31 07:52:21 PM PDT 24	6986090384 ps
T191	/workspace/coverage/default/0.sram_ctrl_multiple_keys.1488024797	Jul 31 07:38:41 PM PDT 24	Jul 31 08:02:23 PM PDT 24	3969191664 ps
T192	/workspace/coverage/default/1.sram_ctrl_mem_walk.3835475155	Jul 31 07:39:01 PM PDT 24	Jul 31 07:39:13 PM PDT 24	1340379808 ps
T63	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1384931	Jul 31 07:38:57 PM PDT 24	Jul 31 07:39:01 PM PDT 24	108960324 ps
T193	/workspace/coverage/default/28.sram_ctrl_regwen.3021326185	Jul 31 07:41:14 PM PDT 24	Jul 31 07:52:49 PM PDT 24	26467594650 ps
T194	/workspace/coverage/default/46.sram_ctrl_max_throughput.1781078666	Jul 31 07:43:55 PM PDT 24	Jul 31 07:46:28 PM PDT 24	533819119 ps
T195	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.509158438	Jul 31 07:43:34 PM PDT 24	Jul 31 07:48:47 PM PDT 24	13426415214 ps
T196	/workspace/coverage/default/5.sram_ctrl_regwen.1794962930	Jul 31 07:38:58 PM PDT 24	Jul 31 07:54:32 PM PDT 24	19835346629 ps
T197	/workspace/coverage/default/1.sram_ctrl_stress_all.323867165	Jul 31 07:38:50 PM PDT 24	Jul 31 07:50:57 PM PDT 24	18272324738 ps
T198	/workspace/coverage/default/7.sram_ctrl_multiple_keys.4142297254	Jul 31 07:39:07 PM PDT 24	Jul 31 07:45:25 PM PDT 24	8871581332 ps
T199	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3698586759	Jul 31 07:39:06 PM PDT 24	Jul 31 07:39:10 PM PDT 24	89486891 ps
T200	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.922401719	Jul 31 07:41:30 PM PDT 24	Jul 31 07:44:50 PM PDT 24	7903560969 ps
T201	/workspace/coverage/default/39.sram_ctrl_ram_cfg.2974612943	Jul 31 07:42:42 PM PDT 24	Jul 31 07:42:43 PM PDT 24	29098053 ps
T149	/workspace/coverage/default/38.sram_ctrl_stress_all.924135744	Jul 31 07:42:35 PM PDT 24	Jul 31 07:58:08 PM PDT 24	15335409022 ps
T202	/workspace/coverage/default/4.sram_ctrl_max_throughput.2205986481	Jul 31 07:38:59 PM PDT 24	Jul 31 07:41:27 PM PDT 24	270961160 ps
T203	/workspace/coverage/default/2.sram_ctrl_lc_escalation.546101897	Jul 31 07:39:02 PM PDT 24	Jul 31 07:39:07 PM PDT 24	1084178089 ps
T204	/workspace/coverage/default/45.sram_ctrl_lc_escalation.1366557764	Jul 31 07:43:49 PM PDT 24	Jul 31 07:43:55 PM PDT 24	525321860 ps
T205	/workspace/coverage/default/11.sram_ctrl_mem_walk.2714483330	Jul 31 07:39:26 PM PDT 24	Jul 31 07:39:36 PM PDT 24	852763883 ps
T206	/workspace/coverage/default/32.sram_ctrl_mem_walk.3658873247	Jul 31 07:41:41 PM PDT 24	Jul 31 07:41:46 PM PDT 24	931454200 ps
T207	/workspace/coverage/default/21.sram_ctrl_executable.2658987538	Jul 31 07:40:23 PM PDT 24	Jul 31 07:51:23 PM PDT 24	63329494337 ps
T208	/workspace/coverage/default/38.sram_ctrl_lc_escalation.1466653846	Jul 31 07:42:27 PM PDT 24	Jul 31 07:42:31 PM PDT 24	484555129 ps
T209	/workspace/coverage/default/0.sram_ctrl_max_throughput.76432869	Jul 31 07:38:45 PM PDT 24	Jul 31 07:40:32 PM PDT 24	126272448 ps
T210	/workspace/coverage/default/47.sram_ctrl_multiple_keys.3575813875	Jul 31 07:43:56 PM PDT 24	Jul 31 08:10:59 PM PDT 24	43789347891 ps
T64	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1592044431	Jul 31 07:41:50 PM PDT 24	Jul 31 07:50:26 PM PDT 24	19158334979 ps
T211	/workspace/coverage/default/9.sram_ctrl_partial_access.3258595475	Jul 31 07:39:15 PM PDT 24	Jul 31 07:39:57 PM PDT 24	488734814 ps
T212	/workspace/coverage/default/8.sram_ctrl_partial_access.893959450	Jul 31 07:39:15 PM PDT 24	Jul 31 07:41:05 PM PDT 24	809909521 ps
T213	/workspace/coverage/default/33.sram_ctrl_partial_access.3076757070	Jul 31 07:41:41 PM PDT 24	Jul 31 07:42:00 PM PDT 24	1129083264 ps
T214	/workspace/coverage/default/32.sram_ctrl_partial_access.1759282141	Jul 31 07:41:34 PM PDT 24	Jul 31 07:43:30 PM PDT 24	741595095 ps
T215	/workspace/coverage/default/18.sram_ctrl_executable.4270175135	Jul 31 07:40:01 PM PDT 24	Jul 31 07:50:32 PM PDT 24	16777129808 ps
T216	/workspace/coverage/default/15.sram_ctrl_stress_all.2001539525	Jul 31 07:39:48 PM PDT 24	Jul 31 08:03:33 PM PDT 24	22331877728 ps
T217	/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1398881504	Jul 31 07:38:43 PM PDT 24	Jul 31 07:38:47 PM PDT 24	422305811 ps
T218	/workspace/coverage/default/33.sram_ctrl_stress_all.544156726	Jul 31 07:41:51 PM PDT 24	Jul 31 08:00:30 PM PDT 24	6613820325 ps
T219	/workspace/coverage/default/33.sram_ctrl_ram_cfg.3428532996	Jul 31 07:41:49 PM PDT 24	Jul 31 07:41:50 PM PDT 24	38921198 ps
T220	/workspace/coverage/default/11.sram_ctrl_lc_escalation.2193276911	Jul 31 07:39:22 PM PDT 24	Jul 31 07:39:27 PM PDT 24	356670025 ps
T221	/workspace/coverage/default/47.sram_ctrl_bijection.2368687376	Jul 31 07:44:06 PM PDT 24	Jul 31 07:45:00 PM PDT 24	7265766754 ps
T222	/workspace/coverage/default/49.sram_ctrl_stress_all.378647055	Jul 31 07:44:29 PM PDT 24	Jul 31 09:05:59 PM PDT 24	267537170245 ps
T223	/workspace/coverage/default/31.sram_ctrl_executable.3352744963	Jul 31 07:41:31 PM PDT 24	Jul 31 07:53:43 PM PDT 24	10908580863 ps
T224	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1293008260	Jul 31 07:38:50 PM PDT 24	Jul 31 07:40:42 PM PDT 24	4432911257 ps
T225	/workspace/coverage/default/40.sram_ctrl_stress_all.1875590799	Jul 31 07:42:59 PM PDT 24	Jul 31 09:16:26 PM PDT 24	58693549381 ps
T226	/workspace/coverage/default/7.sram_ctrl_ram_cfg.2129462963	Jul 31 07:39:08 PM PDT 24	Jul 31 07:39:08 PM PDT 24	45589726 ps
T227	/workspace/coverage/default/42.sram_ctrl_ram_cfg.181080571	Jul 31 07:43:08 PM PDT 24	Jul 31 07:43:09 PM PDT 24	70205855 ps
T228	/workspace/coverage/default/37.sram_ctrl_lc_escalation.3250597116	Jul 31 07:42:17 PM PDT 24	Jul 31 07:42:23 PM PDT 24	460529720 ps
T229	/workspace/coverage/default/18.sram_ctrl_multiple_keys.3617031425	Jul 31 07:40:02 PM PDT 24	Jul 31 07:53:37 PM PDT 24	22362388450 ps
T230	/workspace/coverage/default/24.sram_ctrl_alert_test.935585974	Jul 31 07:40:45 PM PDT 24	Jul 31 07:40:46 PM PDT 24	41332552 ps
T231	/workspace/coverage/default/27.sram_ctrl_regwen.1545047033	Jul 31 07:41:01 PM PDT 24	Jul 31 07:49:19 PM PDT 24	3018850436 ps
T232	/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2133890785	Jul 31 07:39:23 PM PDT 24	Jul 31 07:41:02 PM PDT 24	2887371986 ps
T233	/workspace/coverage/default/47.sram_ctrl_mem_walk.489502756	Jul 31 07:44:09 PM PDT 24	Jul 31 07:44:15 PM PDT 24	662777884 ps
T234	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1589878287	Jul 31 07:42:36 PM PDT 24	Jul 31 07:48:42 PM PDT 24	17781918752 ps
T235	/workspace/coverage/default/0.sram_ctrl_stress_all.430058925	Jul 31 07:38:40 PM PDT 24	Jul 31 08:02:17 PM PDT 24	6317456805 ps
T236	/workspace/coverage/default/3.sram_ctrl_alert_test.2979379741	Jul 31 07:38:58 PM PDT 24	Jul 31 07:38:59 PM PDT 24	18679305 ps
T237	/workspace/coverage/default/44.sram_ctrl_max_throughput.3050075920	Jul 31 07:43:32 PM PDT 24	Jul 31 07:43:48 PM PDT 24	277964480 ps
T238	/workspace/coverage/default/4.sram_ctrl_partial_access.4171113401	Jul 31 07:39:00 PM PDT 24	Jul 31 07:40:44 PM PDT 24	577762699 ps
T239	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3117039689	Jul 31 07:42:55 PM PDT 24	Jul 31 07:50:44 PM PDT 24	21256187140 ps
T240	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1929706008	Jul 31 07:43:04 PM PDT 24	Jul 31 07:50:38 PM PDT 24	1803460638 ps
T241	/workspace/coverage/default/27.sram_ctrl_alert_test.3581038636	Jul 31 07:41:01 PM PDT 24	Jul 31 07:41:01 PM PDT 24	16539574 ps
T242	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.90987171	Jul 31 07:44:04 PM PDT 24	Jul 31 07:44:44 PM PDT 24	630670285 ps
T243	/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1867533229	Jul 31 07:42:21 PM PDT 24	Jul 31 07:48:28 PM PDT 24	14788841580 ps
T244	/workspace/coverage/default/24.sram_ctrl_stress_all.391716464	Jul 31 07:40:46 PM PDT 24	Jul 31 09:11:32 PM PDT 24	13892431005 ps
T245	/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1643644980	Jul 31 07:38:59 PM PDT 24	Jul 31 07:39:01 PM PDT 24	49354666 ps
T246	/workspace/coverage/default/6.sram_ctrl_partial_access.3821556764	Jul 31 07:39:08 PM PDT 24	Jul 31 07:39:55 PM PDT 24	1358319934 ps
T247	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3301834790	Jul 31 07:43:01 PM PDT 24	Jul 31 07:43:04 PM PDT 24	171374229 ps
T248	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4145238168	Jul 31 07:43:55 PM PDT 24	Jul 31 07:44:45 PM PDT 24	108753489 ps
T249	/workspace/coverage/default/34.sram_ctrl_max_throughput.3890079547	Jul 31 07:41:52 PM PDT 24	Jul 31 07:43:29 PM PDT 24	150698652 ps
T250	/workspace/coverage/default/18.sram_ctrl_max_throughput.84340064	Jul 31 07:40:01 PM PDT 24	Jul 31 07:40:23 PM PDT 24	82119370 ps
T251	/workspace/coverage/default/42.sram_ctrl_regwen.126406728	Jul 31 07:43:07 PM PDT 24	Jul 31 07:45:42 PM PDT 24	850509558 ps
T252	/workspace/coverage/default/34.sram_ctrl_alert_test.4207436059	Jul 31 07:41:58 PM PDT 24	Jul 31 07:41:59 PM PDT 24	30345909 ps
T253	/workspace/coverage/default/33.sram_ctrl_alert_test.3040215690	Jul 31 07:41:52 PM PDT 24	Jul 31 07:41:52 PM PDT 24	25840384 ps
T254	/workspace/coverage/default/20.sram_ctrl_multiple_keys.3935025487	Jul 31 07:40:09 PM PDT 24	Jul 31 07:53:07 PM PDT 24	64578718831 ps
T255	/workspace/coverage/default/21.sram_ctrl_regwen.1770498903	Jul 31 07:40:23 PM PDT 24	Jul 31 07:56:12 PM PDT 24	36198665900 ps
T256	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3030935658	Jul 31 07:39:50 PM PDT 24	Jul 31 07:42:46 PM PDT 24	17539576872 ps
T257	/workspace/coverage/default/5.sram_ctrl_alert_test.536703209	Jul 31 07:39:16 PM PDT 24	Jul 31 07:39:17 PM PDT 24	56728867 ps
T258	/workspace/coverage/default/44.sram_ctrl_regwen.3187243549	Jul 31 07:43:32 PM PDT 24	Jul 31 08:13:05 PM PDT 24	35820218118 ps
T81	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2949126601	Jul 31 07:42:03 PM PDT 24	Jul 31 07:49:43 PM PDT 24	24298232587 ps
T259	/workspace/coverage/default/21.sram_ctrl_stress_all.3317893656	Jul 31 07:40:27 PM PDT 24	Jul 31 08:07:10 PM PDT 24	150012741791 ps
T260	/workspace/coverage/default/5.sram_ctrl_mem_walk.1846835415	Jul 31 07:39:08 PM PDT 24	Jul 31 07:39:13 PM PDT 24	82961710 ps
T261	/workspace/coverage/default/28.sram_ctrl_partial_access.1885256795	Jul 31 07:41:13 PM PDT 24	Jul 31 07:44:06 PM PDT 24	774473281 ps
T262	/workspace/coverage/default/34.sram_ctrl_partial_access.642112914	Jul 31 07:41:48 PM PDT 24	Jul 31 07:44:19 PM PDT 24	666770060 ps
T263	/workspace/coverage/default/47.sram_ctrl_regwen.1170406008	Jul 31 07:44:04 PM PDT 24	Jul 31 08:09:15 PM PDT 24	11038388953 ps
T264	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3004705528	Jul 31 07:41:02 PM PDT 24	Jul 31 07:41:07 PM PDT 24	68232984 ps
T265	/workspace/coverage/default/25.sram_ctrl_max_throughput.699669579	Jul 31 07:40:47 PM PDT 24	Jul 31 07:40:53 PM PDT 24	197843043 ps
T266	/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2497230667	Jul 31 07:43:42 PM PDT 24	Jul 31 07:43:45 PM PDT 24	376160324 ps
T267	/workspace/coverage/default/44.sram_ctrl_bijection.1999539625	Jul 31 07:43:32 PM PDT 24	Jul 31 07:44:27 PM PDT 24	1663437190 ps
T268	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3542178700	Jul 31 07:40:38 PM PDT 24	Jul 31 07:41:51 PM PDT 24	447451781 ps
T269	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3579187096	Jul 31 07:42:05 PM PDT 24	Jul 31 07:42:08 PM PDT 24	511568067 ps
T270	/workspace/coverage/default/25.sram_ctrl_partial_access.4130245751	Jul 31 07:40:44 PM PDT 24	Jul 31 07:41:57 PM PDT 24	2153098887 ps
T271	/workspace/coverage/default/49.sram_ctrl_smoke.2192487285	Jul 31 07:44:14 PM PDT 24	Jul 31 07:45:18 PM PDT 24	894440934 ps
T272	/workspace/coverage/default/39.sram_ctrl_bijection.3708411251	Jul 31 07:42:39 PM PDT 24	Jul 31 07:43:53 PM PDT 24	1091902064 ps
T273	/workspace/coverage/default/18.sram_ctrl_alert_test.298833161	Jul 31 07:40:03 PM PDT 24	Jul 31 07:40:04 PM PDT 24	13944187 ps
T274	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1193491809	Jul 31 07:42:54 PM PDT 24	Jul 31 07:42:57 PM PDT 24	175644465 ps
T275	/workspace/coverage/default/16.sram_ctrl_executable.1112172759	Jul 31 07:39:53 PM PDT 24	Jul 31 08:05:14 PM PDT 24	3221635085 ps
T276	/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3993737218	Jul 31 07:39:22 PM PDT 24	Jul 31 07:40:29 PM PDT 24	2716630030 ps
T277	/workspace/coverage/default/42.sram_ctrl_mem_walk.2174105721	Jul 31 07:43:13 PM PDT 24	Jul 31 07:43:19 PM PDT 24	670064728 ps
T278	/workspace/coverage/default/16.sram_ctrl_max_throughput.359903859	Jul 31 07:39:49 PM PDT 24	Jul 31 07:41:06 PM PDT 24	124372614 ps
T279	/workspace/coverage/default/33.sram_ctrl_lc_escalation.3406096843	Jul 31 07:41:39 PM PDT 24	Jul 31 07:41:43 PM PDT 24	422225582 ps
T280	/workspace/coverage/default/32.sram_ctrl_bijection.1580540548	Jul 31 07:41:30 PM PDT 24	Jul 31 07:42:36 PM PDT 24	11084028414 ps
T281	/workspace/coverage/default/30.sram_ctrl_alert_test.2850658180	Jul 31 07:41:30 PM PDT 24	Jul 31 07:41:31 PM PDT 24	33644103 ps
T282	/workspace/coverage/default/6.sram_ctrl_multiple_keys.1843488239	Jul 31 07:39:07 PM PDT 24	Jul 31 07:48:38 PM PDT 24	2636217038 ps
T283	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1518933466	Jul 31 07:40:44 PM PDT 24	Jul 31 07:40:48 PM PDT 24	591975291 ps
T284	/workspace/coverage/default/21.sram_ctrl_partial_access.2340018552	Jul 31 07:40:16 PM PDT 24	Jul 31 07:40:18 PM PDT 24	50584049 ps
T285	/workspace/coverage/default/47.sram_ctrl_lc_escalation.977857328	Jul 31 07:44:05 PM PDT 24	Jul 31 07:44:09 PM PDT 24	1410696393 ps
T286	/workspace/coverage/default/1.sram_ctrl_bijection.968369054	Jul 31 07:38:43 PM PDT 24	Jul 31 07:40:06 PM PDT 24	9252088501 ps
T287	/workspace/coverage/default/42.sram_ctrl_mem_partial_access.9908778	Jul 31 07:43:13 PM PDT 24	Jul 31 07:43:16 PM PDT 24	355679374 ps
T288	/workspace/coverage/default/35.sram_ctrl_alert_test.3859358312	Jul 31 07:42:03 PM PDT 24	Jul 31 07:42:04 PM PDT 24	11346926 ps
T289	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1244485401	Jul 31 07:44:17 PM PDT 24	Jul 31 07:44:20 PM PDT 24	367213383 ps
T290	/workspace/coverage/default/37.sram_ctrl_multiple_keys.3578940338	Jul 31 07:42:21 PM PDT 24	Jul 31 07:57:13 PM PDT 24	7822345083 ps
T291	/workspace/coverage/default/34.sram_ctrl_stress_all.3821465539	Jul 31 07:41:55 PM PDT 24	Jul 31 08:23:13 PM PDT 24	29193554981 ps
T292	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2550760008	Jul 31 07:39:14 PM PDT 24	Jul 31 07:39:22 PM PDT 24	69366181 ps
T293	/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3147636676	Jul 31 07:42:04 PM PDT 24	Jul 31 07:43:53 PM PDT 24	594769430 ps
T294	/workspace/coverage/default/8.sram_ctrl_lc_escalation.3556147315	Jul 31 07:39:13 PM PDT 24	Jul 31 07:39:19 PM PDT 24	426295638 ps
T295	/workspace/coverage/default/37.sram_ctrl_ram_cfg.3510509642	Jul 31 07:42:20 PM PDT 24	Jul 31 07:42:21 PM PDT 24	28523632 ps
T296	/workspace/coverage/default/9.sram_ctrl_multiple_keys.2212918262	Jul 31 07:39:14 PM PDT 24	Jul 31 07:51:08 PM PDT 24	10179593283 ps
T297	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.782013105	Jul 31 07:42:03 PM PDT 24	Jul 31 07:46:14 PM PDT 24	805828859 ps
T298	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1266815239	Jul 31 07:38:51 PM PDT 24	Jul 31 07:48:18 PM PDT 24	2044712916 ps
T299	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.230028915	Jul 31 07:41:12 PM PDT 24	Jul 31 07:59:06 PM PDT 24	8731115469 ps
T300	/workspace/coverage/default/11.sram_ctrl_partial_access.84865292	Jul 31 07:39:19 PM PDT 24	Jul 31 07:39:29 PM PDT 24	552386962 ps
T301	/workspace/coverage/default/27.sram_ctrl_executable.1869801990	Jul 31 07:41:01 PM PDT 24	Jul 31 07:53:22 PM PDT 24	7032826922 ps
T302	/workspace/coverage/default/49.sram_ctrl_mem_walk.335038388	Jul 31 07:44:25 PM PDT 24	Jul 31 07:44:31 PM PDT 24	387909030 ps
T303	/workspace/coverage/default/21.sram_ctrl_max_throughput.4255587329	Jul 31 07:40:23 PM PDT 24	Jul 31 07:41:31 PM PDT 24	399580500 ps
T304	/workspace/coverage/default/39.sram_ctrl_lc_escalation.197182326	Jul 31 07:42:37 PM PDT 24	Jul 31 07:42:44 PM PDT 24	583144915 ps
T305	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.3251523629	Jul 31 07:42:28 PM PDT 24	Jul 31 07:42:34 PM PDT 24	400149091 ps
T306	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.198935639	Jul 31 07:42:10 PM PDT 24	Jul 31 07:42:15 PM PDT 24	196035633 ps
T307	/workspace/coverage/default/14.sram_ctrl_mem_walk.3673641471	Jul 31 07:39:41 PM PDT 24	Jul 31 07:39:53 PM PDT 24	2728093214 ps
T308	/workspace/coverage/default/14.sram_ctrl_executable.581388486	Jul 31 07:39:42 PM PDT 24	Jul 31 07:54:44 PM PDT 24	56940374180 ps
T309	/workspace/coverage/default/29.sram_ctrl_stress_all.776141174	Jul 31 07:41:22 PM PDT 24	Jul 31 07:46:57 PM PDT 24	4213251930 ps
T310	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3793932194	Jul 31 07:40:46 PM PDT 24	Jul 31 07:43:41 PM PDT 24	4520968187 ps
T311	/workspace/coverage/default/20.sram_ctrl_mem_walk.2354318176	Jul 31 07:40:18 PM PDT 24	Jul 31 07:40:23 PM PDT 24	239311128 ps