Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45717104	1			T1	3071		T2	9874		T3	6664
triple_byte_access	2537455	1			T3	133		T5	2474		T9	3520
halfword_access	3806508	1			T3	191		T5	3795		T9	5430
byte_access	5082110	1			T3	256		T5	5042		T9	7317
zero_access	1277427	1			T3	72		T5	1277		T9	1838

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29157183

1

T1

1024

T2

5003

T3

3641

auto[1]

29263421

1

T1

2047

T2

4871

T3

3675

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22811260	1			T1	1024		T2	5003		T3	3313
auto[0]	triple_byte_access	1264955	1			T3	68		T5	1221		T9	1711
auto[0]	halfword_access	1899078	1			T3	86		T5	1877		T9	2720
auto[0]	byte_access	2540175	1			T3	128		T5	2552		T9	3655
auto[0]	zero_access	641715	1			T3	46		T5	631		T9	941
auto[1]	word_access	22905844	1			T1	2047		T2	4871		T3	3351
auto[1]	triple_byte_access	1272500	1			T3	65		T5	1253		T9	1809
auto[1]	halfword_access	1907430	1			T3	105		T5	1918		T9	2710
auto[1]	byte_access	2541935	1			T3	128		T5	2490		T9	3662
auto[1]	zero_access	635712	1			T3	26		T5	646		T9	897