Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147467976	1			T1	36864		T2	20000		T3	358376
instr_valid_dis	115114309	1			T1	36864		T2	20000		T3	133384
instr_en	23399706	1			T3	178002		T5	11110		T20	189836

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9447715	1			T3	79902		T22	40076		T20	50502
sram_ifetch_valid_disable	116594430	1			T1	36864		T2	20000		T3	162688
sram_ifetch_enable	21425831	1			T3	115786		T22	138424		T20	101730

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147467976	1			T1	36864		T2	20000		T3	358376
hw_debug_en_valid_off	113580429	1			T1	36864		T2	20000		T3	4810
hw_debug_en_on	23139816	1			T3	284180		T22	26388		T20	50152

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	116594430	1			T1	36864		T2	20000		T3	162688
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102765318	1			T1	36864		T2	20000		T3	56438
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9852986	1			T3	106250		T5	11110		T20	67716
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3546752	1			T60	26188		T131	15958		T64	57176
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1652820	1			T60	26188		T131	15958		T69	38854
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1463096	1			T64	57176		T23	7934		T29	122794
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4181279	1			T3	79902		T20	20000		T9	27464
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1695731	1			T3	38808		T9	27464		T60	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1949242	1			T3	41094		T20	20000		T64	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9688841	1			T3	112678		T22	98		T20	12550
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3567814	1			T3	6524		T22	98		T9	94294
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4125781	1			T3	106154		T20	12550		T131	3918

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9465100	1			T3	30658		T20	85910		T9	38946
lc_exec_en	9269696	1			T3	91600		T22	26290		T20	17602
valid_exec_dis	110550145	1			T1	36864		T2	20000		T3	42948
invalid_exec_dis	30873546	1			T3	195688		T22	178500		T20	152232