Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44074041	1			T1	18432		T2	10000		T3	65314
triple_byte_access	2587429	1			T3	1282		T4	4841		T5	84
halfword_access	3884188	1			T3	2000		T4	7528		T5	131
byte_access	5187181	1			T3	2586		T4	9839		T5	168
zero_access	1305819	1			T3	635		T4	2466		T5	49

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28464188

1

T1

9216

T2

4980

T3

35856

auto[1]

28574470

1

T1

9216

T2

5020

T3

35961

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21989393	1			T1	9216		T2	4980		T3	32615
auto[0]	triple_byte_access	1290231	1			T3	632		T4	2450		T5	45
auto[0]	halfword_access	1938487	1			T3	994		T4	3804		T5	63
auto[0]	byte_access	2589672	1			T3	1292		T4	4891		T5	86
auto[0]	zero_access	656405	1			T3	323		T4	1255		T5	23
auto[1]	word_access	22084648	1			T1	9216		T2	5020		T3	32699
auto[1]	triple_byte_access	1297198	1			T3	650		T4	2391		T5	39
auto[1]	halfword_access	1945701	1			T3	1006		T4	3724		T5	68
auto[1]	byte_access	2597509	1			T3	1294		T4	4948		T5	82
auto[1]	zero_access	649414	1			T3	312		T4	1211		T5	26