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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1026
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T791 /workspace/coverage/default/12.sram_ctrl_max_throughput.451426648 Aug 01 06:32:53 PM PDT 24 Aug 01 06:33:39 PM PDT 24 1145857991 ps
T792 /workspace/coverage/default/27.sram_ctrl_max_throughput.1220625053 Aug 01 06:33:57 PM PDT 24 Aug 01 06:34:04 PM PDT 24 109240977 ps
T793 /workspace/coverage/default/34.sram_ctrl_lc_escalation.3972495684 Aug 01 06:35:40 PM PDT 24 Aug 01 06:35:45 PM PDT 24 317948091 ps
T794 /workspace/coverage/default/8.sram_ctrl_regwen.2913783748 Aug 01 06:32:26 PM PDT 24 Aug 01 06:46:34 PM PDT 24 60954748065 ps
T795 /workspace/coverage/default/6.sram_ctrl_alert_test.3321622423 Aug 01 06:32:23 PM PDT 24 Aug 01 06:32:24 PM PDT 24 35938523 ps
T796 /workspace/coverage/default/20.sram_ctrl_bijection.811305302 Aug 01 06:33:11 PM PDT 24 Aug 01 06:33:55 PM PDT 24 2540293338 ps
T797 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1489045033 Aug 01 06:32:52 PM PDT 24 Aug 01 06:38:28 PM PDT 24 1224524395 ps
T798 /workspace/coverage/default/38.sram_ctrl_mem_walk.1034962853 Aug 01 06:36:39 PM PDT 24 Aug 01 06:36:50 PM PDT 24 356457998 ps
T799 /workspace/coverage/default/16.sram_ctrl_partial_access.2200734855 Aug 01 06:32:50 PM PDT 24 Aug 01 06:32:52 PM PDT 24 205844750 ps
T800 /workspace/coverage/default/47.sram_ctrl_smoke.845315613 Aug 01 06:38:26 PM PDT 24 Aug 01 06:38:34 PM PDT 24 748754224 ps
T801 /workspace/coverage/default/19.sram_ctrl_multiple_keys.3948070965 Aug 01 06:33:05 PM PDT 24 Aug 01 06:49:34 PM PDT 24 3429446645 ps
T802 /workspace/coverage/default/39.sram_ctrl_alert_test.3199333199 Aug 01 06:36:51 PM PDT 24 Aug 01 06:36:52 PM PDT 24 53712023 ps
T803 /workspace/coverage/default/8.sram_ctrl_executable.1600617954 Aug 01 06:32:33 PM PDT 24 Aug 01 06:43:32 PM PDT 24 1447024846 ps
T804 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1345841204 Aug 01 06:32:50 PM PDT 24 Aug 01 06:32:52 PM PDT 24 58600851 ps
T805 /workspace/coverage/default/31.sram_ctrl_multiple_keys.1740025584 Aug 01 06:34:48 PM PDT 24 Aug 01 06:52:49 PM PDT 24 7981840141 ps
T806 /workspace/coverage/default/23.sram_ctrl_ram_cfg.2607184410 Aug 01 06:33:34 PM PDT 24 Aug 01 06:33:35 PM PDT 24 110256335 ps
T807 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3590440415 Aug 01 06:32:13 PM PDT 24 Aug 01 06:32:15 PM PDT 24 43393866 ps
T808 /workspace/coverage/default/48.sram_ctrl_mem_walk.3015309615 Aug 01 06:38:48 PM PDT 24 Aug 01 06:38:59 PM PDT 24 353964911 ps
T809 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3985631473 Aug 01 06:35:59 PM PDT 24 Aug 01 06:48:52 PM PDT 24 4287806008 ps
T810 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.847825437 Aug 01 06:32:58 PM PDT 24 Aug 01 06:36:39 PM PDT 24 6448014540 ps
T811 /workspace/coverage/default/43.sram_ctrl_stress_all.2137734717 Aug 01 06:37:46 PM PDT 24 Aug 01 07:55:43 PM PDT 24 50025676517 ps
T812 /workspace/coverage/default/12.sram_ctrl_lc_escalation.1257290641 Aug 01 06:32:48 PM PDT 24 Aug 01 06:32:53 PM PDT 24 342322759 ps
T813 /workspace/coverage/default/17.sram_ctrl_max_throughput.339666309 Aug 01 06:33:00 PM PDT 24 Aug 01 06:33:28 PM PDT 24 331229179 ps
T814 /workspace/coverage/default/2.sram_ctrl_stress_all.3734400849 Aug 01 06:32:18 PM PDT 24 Aug 01 06:47:22 PM PDT 24 9748201059 ps
T815 /workspace/coverage/default/6.sram_ctrl_lc_escalation.2703709474 Aug 01 06:32:25 PM PDT 24 Aug 01 06:32:33 PM PDT 24 461179430 ps
T816 /workspace/coverage/default/28.sram_ctrl_regwen.2558740496 Aug 01 06:34:10 PM PDT 24 Aug 01 06:35:34 PM PDT 24 1562518086 ps
T817 /workspace/coverage/default/10.sram_ctrl_executable.580604809 Aug 01 06:32:37 PM PDT 24 Aug 01 06:43:13 PM PDT 24 30438095217 ps
T818 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3359313912 Aug 01 06:32:51 PM PDT 24 Aug 01 06:32:57 PM PDT 24 753736207 ps
T819 /workspace/coverage/default/49.sram_ctrl_mem_walk.4270267116 Aug 01 06:39:01 PM PDT 24 Aug 01 06:39:06 PM PDT 24 699116775 ps
T820 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3299603372 Aug 01 06:34:49 PM PDT 24 Aug 01 06:39:33 PM PDT 24 2915743754 ps
T821 /workspace/coverage/default/29.sram_ctrl_smoke.2517908256 Aug 01 06:34:18 PM PDT 24 Aug 01 06:34:37 PM PDT 24 88863297 ps
T822 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3243037689 Aug 01 06:32:51 PM PDT 24 Aug 01 06:42:01 PM PDT 24 4264618588 ps
T823 /workspace/coverage/default/36.sram_ctrl_multiple_keys.1019569084 Aug 01 06:35:56 PM PDT 24 Aug 01 06:52:38 PM PDT 24 19933188624 ps
T824 /workspace/coverage/default/45.sram_ctrl_smoke.2235562052 Aug 01 06:37:59 PM PDT 24 Aug 01 06:38:12 PM PDT 24 622747823 ps
T825 /workspace/coverage/default/20.sram_ctrl_smoke.3258234430 Aug 01 06:33:10 PM PDT 24 Aug 01 06:34:50 PM PDT 24 525960394 ps
T826 /workspace/coverage/default/16.sram_ctrl_stress_all.270807913 Aug 01 06:32:52 PM PDT 24 Aug 01 06:44:22 PM PDT 24 6833371477 ps
T827 /workspace/coverage/default/30.sram_ctrl_executable.2445112710 Aug 01 06:34:35 PM PDT 24 Aug 01 06:57:13 PM PDT 24 26163407305 ps
T828 /workspace/coverage/default/9.sram_ctrl_partial_access.2393115633 Aug 01 06:32:40 PM PDT 24 Aug 01 06:32:45 PM PDT 24 69155203 ps
T829 /workspace/coverage/default/38.sram_ctrl_bijection.3837654385 Aug 01 06:36:26 PM PDT 24 Aug 01 06:36:44 PM PDT 24 975368491 ps
T830 /workspace/coverage/default/14.sram_ctrl_executable.105928711 Aug 01 06:32:55 PM PDT 24 Aug 01 06:56:52 PM PDT 24 81867685835 ps
T831 /workspace/coverage/default/24.sram_ctrl_ram_cfg.1823306539 Aug 01 06:33:35 PM PDT 24 Aug 01 06:33:36 PM PDT 24 31660600 ps
T832 /workspace/coverage/default/20.sram_ctrl_multiple_keys.1765865035 Aug 01 06:33:13 PM PDT 24 Aug 01 06:36:05 PM PDT 24 3347750432 ps
T833 /workspace/coverage/default/11.sram_ctrl_ram_cfg.1364038072 Aug 01 06:32:41 PM PDT 24 Aug 01 06:32:42 PM PDT 24 30273808 ps
T834 /workspace/coverage/default/27.sram_ctrl_regwen.1619810526 Aug 01 06:33:58 PM PDT 24 Aug 01 06:37:25 PM PDT 24 2939727760 ps
T835 /workspace/coverage/default/48.sram_ctrl_bijection.3772231305 Aug 01 06:38:49 PM PDT 24 Aug 01 06:39:03 PM PDT 24 954567786 ps
T836 /workspace/coverage/default/5.sram_ctrl_multiple_keys.4268353656 Aug 01 06:32:22 PM PDT 24 Aug 01 06:51:40 PM PDT 24 83798435125 ps
T837 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3550378566 Aug 01 06:35:20 PM PDT 24 Aug 01 06:39:22 PM PDT 24 3266741874 ps
T838 /workspace/coverage/default/40.sram_ctrl_ram_cfg.981995672 Aug 01 06:37:01 PM PDT 24 Aug 01 06:37:02 PM PDT 24 30423912 ps
T839 /workspace/coverage/default/49.sram_ctrl_partial_access.2258476443 Aug 01 06:39:04 PM PDT 24 Aug 01 06:39:06 PM PDT 24 80214567 ps
T840 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.4070275765 Aug 01 06:38:23 PM PDT 24 Aug 01 07:01:24 PM PDT 24 22137117877 ps
T841 /workspace/coverage/default/29.sram_ctrl_lc_escalation.600071917 Aug 01 06:34:22 PM PDT 24 Aug 01 06:34:31 PM PDT 24 3957060008 ps
T842 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1813460989 Aug 01 06:32:56 PM PDT 24 Aug 01 06:33:00 PM PDT 24 92192473 ps
T843 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2506052106 Aug 01 06:33:00 PM PDT 24 Aug 01 06:34:46 PM PDT 24 1149993143 ps
T844 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.4147752547 Aug 01 06:33:12 PM PDT 24 Aug 01 06:41:17 PM PDT 24 36494286372 ps
T845 /workspace/coverage/default/45.sram_ctrl_executable.2430752123 Aug 01 06:38:23 PM PDT 24 Aug 01 06:58:59 PM PDT 24 36341587059 ps
T846 /workspace/coverage/default/33.sram_ctrl_max_throughput.1067086079 Aug 01 06:35:20 PM PDT 24 Aug 01 06:35:25 PM PDT 24 53133590 ps
T847 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3398798145 Aug 01 06:39:00 PM PDT 24 Aug 01 06:41:17 PM PDT 24 1332872354 ps
T848 /workspace/coverage/default/9.sram_ctrl_multiple_keys.2060943447 Aug 01 06:32:44 PM PDT 24 Aug 01 06:47:38 PM PDT 24 16943012433 ps
T849 /workspace/coverage/default/23.sram_ctrl_mem_walk.1141483345 Aug 01 06:33:33 PM PDT 24 Aug 01 06:33:44 PM PDT 24 1772409976 ps
T850 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3969345847 Aug 01 06:35:54 PM PDT 24 Aug 01 06:35:57 PM PDT 24 317275446 ps
T851 /workspace/coverage/default/20.sram_ctrl_lc_escalation.4211683398 Aug 01 06:33:10 PM PDT 24 Aug 01 06:33:15 PM PDT 24 1573289801 ps
T852 /workspace/coverage/default/1.sram_ctrl_stress_all.3525587460 Aug 01 06:32:12 PM PDT 24 Aug 01 07:06:15 PM PDT 24 8263606359 ps
T28 /workspace/coverage/default/0.sram_ctrl_sec_cm.751718124 Aug 01 06:32:10 PM PDT 24 Aug 01 06:32:14 PM PDT 24 411262640 ps
T853 /workspace/coverage/default/46.sram_ctrl_stress_all.2070780249 Aug 01 06:38:24 PM PDT 24 Aug 01 07:11:26 PM PDT 24 88537587322 ps
T854 /workspace/coverage/default/13.sram_ctrl_mem_walk.2823717821 Aug 01 06:32:49 PM PDT 24 Aug 01 06:32:56 PM PDT 24 347712508 ps
T855 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.1626002175 Aug 01 06:32:24 PM PDT 24 Aug 01 06:35:55 PM PDT 24 2249564299 ps
T856 /workspace/coverage/default/41.sram_ctrl_regwen.3645152331 Aug 01 06:37:12 PM PDT 24 Aug 01 07:00:03 PM PDT 24 7127089637 ps
T857 /workspace/coverage/default/39.sram_ctrl_ram_cfg.2262574722 Aug 01 06:36:51 PM PDT 24 Aug 01 06:36:52 PM PDT 24 77380567 ps
T858 /workspace/coverage/default/8.sram_ctrl_ram_cfg.2959500885 Aug 01 06:32:41 PM PDT 24 Aug 01 06:32:42 PM PDT 24 32851235 ps
T859 /workspace/coverage/default/19.sram_ctrl_stress_all.271444012 Aug 01 06:33:03 PM PDT 24 Aug 01 06:55:28 PM PDT 24 5529572389 ps
T860 /workspace/coverage/default/17.sram_ctrl_bijection.165937888 Aug 01 06:32:54 PM PDT 24 Aug 01 06:33:28 PM PDT 24 2340621069 ps
T861 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.924796452 Aug 01 06:33:33 PM PDT 24 Aug 01 06:37:50 PM PDT 24 4124018483 ps
T862 /workspace/coverage/default/24.sram_ctrl_multiple_keys.3783593107 Aug 01 06:33:35 PM PDT 24 Aug 01 06:49:36 PM PDT 24 63429860704 ps
T863 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.335112854 Aug 01 06:32:24 PM PDT 24 Aug 01 06:33:12 PM PDT 24 735814222 ps
T864 /workspace/coverage/default/21.sram_ctrl_lc_escalation.1047162671 Aug 01 06:33:10 PM PDT 24 Aug 01 06:33:18 PM PDT 24 1099644512 ps
T865 /workspace/coverage/default/35.sram_ctrl_ram_cfg.2418430380 Aug 01 06:35:51 PM PDT 24 Aug 01 06:35:52 PM PDT 24 119553825 ps
T866 /workspace/coverage/default/12.sram_ctrl_stress_all.1063851961 Aug 01 06:32:51 PM PDT 24 Aug 01 07:08:43 PM PDT 24 10954871195 ps
T867 /workspace/coverage/default/16.sram_ctrl_max_throughput.1179245902 Aug 01 06:32:51 PM PDT 24 Aug 01 06:33:20 PM PDT 24 1222918876 ps
T868 /workspace/coverage/default/11.sram_ctrl_stress_all.1276137104 Aug 01 06:32:36 PM PDT 24 Aug 01 07:18:38 PM PDT 24 8076463825 ps
T869 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3475544040 Aug 01 06:36:29 PM PDT 24 Aug 01 06:59:24 PM PDT 24 21482811050 ps
T870 /workspace/coverage/default/7.sram_ctrl_bijection.3153822966 Aug 01 06:32:24 PM PDT 24 Aug 01 06:33:25 PM PDT 24 3239175451 ps
T871 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.422328497 Aug 01 06:37:25 PM PDT 24 Aug 01 06:37:31 PM PDT 24 180572586 ps
T872 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2513482909 Aug 01 06:37:02 PM PDT 24 Aug 01 06:37:08 PM PDT 24 1846612534 ps
T873 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2534621695 Aug 01 06:33:10 PM PDT 24 Aug 01 06:43:57 PM PDT 24 3797063017 ps
T874 /workspace/coverage/default/4.sram_ctrl_bijection.4215962815 Aug 01 06:32:19 PM PDT 24 Aug 01 06:32:38 PM PDT 24 4423106868 ps
T875 /workspace/coverage/default/49.sram_ctrl_multiple_keys.1633800211 Aug 01 06:39:00 PM PDT 24 Aug 01 06:50:04 PM PDT 24 42596093325 ps
T876 /workspace/coverage/default/13.sram_ctrl_executable.1742677853 Aug 01 06:32:46 PM PDT 24 Aug 01 06:38:29 PM PDT 24 19214489501 ps
T877 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.42154094 Aug 01 06:35:52 PM PDT 24 Aug 01 06:42:42 PM PDT 24 8749936730 ps
T878 /workspace/coverage/default/43.sram_ctrl_smoke.620368154 Aug 01 06:37:41 PM PDT 24 Aug 01 06:37:47 PM PDT 24 1381599656 ps
T879 /workspace/coverage/default/24.sram_ctrl_lc_escalation.4018946650 Aug 01 06:33:32 PM PDT 24 Aug 01 06:33:38 PM PDT 24 524647743 ps
T880 /workspace/coverage/default/22.sram_ctrl_smoke.1435260713 Aug 01 06:33:12 PM PDT 24 Aug 01 06:33:20 PM PDT 24 340208894 ps
T881 /workspace/coverage/default/17.sram_ctrl_stress_all.2538867961 Aug 01 06:32:59 PM PDT 24 Aug 01 07:14:09 PM PDT 24 7799226965 ps
T882 /workspace/coverage/default/34.sram_ctrl_partial_access.1716238039 Aug 01 06:35:30 PM PDT 24 Aug 01 06:36:12 PM PDT 24 6516485748 ps
T883 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3100060555 Aug 01 06:32:41 PM PDT 24 Aug 01 06:33:38 PM PDT 24 301364390 ps
T884 /workspace/coverage/default/37.sram_ctrl_lc_escalation.3986617651 Aug 01 06:36:26 PM PDT 24 Aug 01 06:36:33 PM PDT 24 727895431 ps
T885 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2247019694 Aug 01 06:36:20 PM PDT 24 Aug 01 06:41:07 PM PDT 24 5389443527 ps
T886 /workspace/coverage/default/47.sram_ctrl_multiple_keys.1198165430 Aug 01 06:38:24 PM PDT 24 Aug 01 07:00:21 PM PDT 24 100170157586 ps
T887 /workspace/coverage/default/28.sram_ctrl_lc_escalation.2471528689 Aug 01 06:34:09 PM PDT 24 Aug 01 06:34:16 PM PDT 24 2243310336 ps
T888 /workspace/coverage/default/40.sram_ctrl_lc_escalation.3702143804 Aug 01 06:37:02 PM PDT 24 Aug 01 06:37:12 PM PDT 24 653382465 ps
T889 /workspace/coverage/default/44.sram_ctrl_alert_test.391519396 Aug 01 06:37:58 PM PDT 24 Aug 01 06:37:59 PM PDT 24 21038737 ps
T890 /workspace/coverage/default/2.sram_ctrl_executable.2856618800 Aug 01 06:32:14 PM PDT 24 Aug 01 06:46:44 PM PDT 24 2908908662 ps
T891 /workspace/coverage/default/14.sram_ctrl_bijection.1705942868 Aug 01 06:32:48 PM PDT 24 Aug 01 06:33:52 PM PDT 24 6137537336 ps
T892 /workspace/coverage/default/47.sram_ctrl_partial_access.4063529084 Aug 01 06:38:35 PM PDT 24 Aug 01 06:38:42 PM PDT 24 144293199 ps
T893 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2457047852 Aug 01 06:38:22 PM PDT 24 Aug 01 06:41:28 PM PDT 24 3828088812 ps
T894 /workspace/coverage/default/42.sram_ctrl_executable.4254482736 Aug 01 06:37:34 PM PDT 24 Aug 01 06:45:26 PM PDT 24 963116186 ps
T895 /workspace/coverage/default/37.sram_ctrl_multiple_keys.2718490976 Aug 01 06:36:12 PM PDT 24 Aug 01 06:37:37 PM PDT 24 5925344960 ps
T896 /workspace/coverage/default/39.sram_ctrl_mem_walk.934684470 Aug 01 06:36:57 PM PDT 24 Aug 01 06:37:06 PM PDT 24 596160517 ps
T897 /workspace/coverage/default/28.sram_ctrl_mem_walk.1471812479 Aug 01 06:34:10 PM PDT 24 Aug 01 06:34:22 PM PDT 24 2434471094 ps
T898 /workspace/coverage/default/18.sram_ctrl_mem_walk.4184823823 Aug 01 06:33:00 PM PDT 24 Aug 01 06:33:06 PM PDT 24 447557052 ps
T899 /workspace/coverage/default/48.sram_ctrl_alert_test.592207595 Aug 01 06:39:00 PM PDT 24 Aug 01 06:39:00 PM PDT 24 45279487 ps
T900 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2973619946 Aug 01 06:32:51 PM PDT 24 Aug 01 06:38:44 PM PDT 24 4962798458 ps
T901 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2674807043 Aug 01 06:36:57 PM PDT 24 Aug 01 06:42:30 PM PDT 24 3384232496 ps
T902 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1391214706 Aug 01 06:33:01 PM PDT 24 Aug 01 06:33:04 PM PDT 24 95253309 ps
T903 /workspace/coverage/default/7.sram_ctrl_executable.433932234 Aug 01 06:32:29 PM PDT 24 Aug 01 06:49:47 PM PDT 24 56481509026 ps
T904 /workspace/coverage/default/14.sram_ctrl_smoke.1786999045 Aug 01 06:32:47 PM PDT 24 Aug 01 06:34:20 PM PDT 24 9909684750 ps
T905 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2271346170 Aug 01 06:33:10 PM PDT 24 Aug 01 06:52:06 PM PDT 24 4306552992 ps
T906 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.712547729 Aug 01 06:35:30 PM PDT 24 Aug 01 06:48:44 PM PDT 24 3792922943 ps
T907 /workspace/coverage/default/4.sram_ctrl_multiple_keys.543140937 Aug 01 06:32:18 PM PDT 24 Aug 01 06:35:36 PM PDT 24 2011241605 ps
T908 /workspace/coverage/default/16.sram_ctrl_ram_cfg.2800131005 Aug 01 06:32:52 PM PDT 24 Aug 01 06:32:53 PM PDT 24 44379174 ps
T909 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3475956170 Aug 01 06:32:23 PM PDT 24 Aug 01 06:32:52 PM PDT 24 193353903 ps
T910 /workspace/coverage/default/20.sram_ctrl_regwen.1035324833 Aug 01 06:33:10 PM PDT 24 Aug 01 06:44:31 PM PDT 24 10371805492 ps
T911 /workspace/coverage/default/26.sram_ctrl_regwen.2067875180 Aug 01 06:33:48 PM PDT 24 Aug 01 06:40:41 PM PDT 24 1048738683 ps
T912 /workspace/coverage/default/35.sram_ctrl_alert_test.1839033906 Aug 01 06:35:52 PM PDT 24 Aug 01 06:35:53 PM PDT 24 56079922 ps
T913 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2333559881 Aug 01 06:32:40 PM PDT 24 Aug 01 06:37:15 PM PDT 24 11591500716 ps
T914 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.4246514550 Aug 01 06:35:01 PM PDT 24 Aug 01 06:35:44 PM PDT 24 399035781 ps
T915 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3494227017 Aug 01 06:32:05 PM PDT 24 Aug 01 06:37:39 PM PDT 24 7374064197 ps
T916 /workspace/coverage/default/28.sram_ctrl_partial_access.244971368 Aug 01 06:33:58 PM PDT 24 Aug 01 06:35:37 PM PDT 24 618720933 ps
T917 /workspace/coverage/default/10.sram_ctrl_mem_walk.3346121646 Aug 01 06:32:38 PM PDT 24 Aug 01 06:32:44 PM PDT 24 418567213 ps
T918 /workspace/coverage/default/41.sram_ctrl_stress_all.2997216267 Aug 01 06:37:25 PM PDT 24 Aug 01 07:31:02 PM PDT 24 63310363381 ps
T919 /workspace/coverage/default/35.sram_ctrl_max_throughput.2147310430 Aug 01 06:35:51 PM PDT 24 Aug 01 06:38:10 PM PDT 24 571849571 ps
T920 /workspace/coverage/default/2.sram_ctrl_alert_test.3794788158 Aug 01 06:32:14 PM PDT 24 Aug 01 06:32:14 PM PDT 24 40508427 ps
T921 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2137284405 Aug 01 06:35:44 PM PDT 24 Aug 01 06:35:54 PM PDT 24 170140765 ps
T922 /workspace/coverage/default/42.sram_ctrl_max_throughput.4143277006 Aug 01 06:37:23 PM PDT 24 Aug 01 06:37:32 PM PDT 24 882984114 ps
T923 /workspace/coverage/default/42.sram_ctrl_stress_all.3637595936 Aug 01 06:37:34 PM PDT 24 Aug 01 07:41:02 PM PDT 24 117903252378 ps
T110 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2468510963 Aug 01 06:36:38 PM PDT 24 Aug 01 06:36:48 PM PDT 24 4699473219 ps
T924 /workspace/coverage/default/36.sram_ctrl_executable.4003047257 Aug 01 06:36:20 PM PDT 24 Aug 01 06:52:01 PM PDT 24 8437182166 ps
T111 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2819093569 Aug 01 06:37:59 PM PDT 24 Aug 01 06:38:19 PM PDT 24 4563922635 ps
T925 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1969250843 Aug 01 06:32:51 PM PDT 24 Aug 01 06:37:57 PM PDT 24 11602181486 ps
T926 /workspace/coverage/default/45.sram_ctrl_partial_access.3540886909 Aug 01 06:38:11 PM PDT 24 Aug 01 06:38:22 PM PDT 24 581984496 ps
T927 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1213045703 Aug 01 06:34:56 PM PDT 24 Aug 01 06:34:59 PM PDT 24 108658496 ps
T928 /workspace/coverage/default/10.sram_ctrl_multiple_keys.3011661959 Aug 01 06:32:41 PM PDT 24 Aug 01 06:41:08 PM PDT 24 4501493750 ps
T929 /workspace/coverage/default/18.sram_ctrl_ram_cfg.3846508088 Aug 01 06:32:59 PM PDT 24 Aug 01 06:32:59 PM PDT 24 239475697 ps
T930 /workspace/coverage/default/2.sram_ctrl_max_throughput.4023176418 Aug 01 06:32:12 PM PDT 24 Aug 01 06:32:19 PM PDT 24 182457541 ps
T61 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2888742514 Aug 01 05:47:20 PM PDT 24 Aug 01 05:47:21 PM PDT 24 54211408 ps
T62 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.520702686 Aug 01 05:47:51 PM PDT 24 Aug 01 05:47:52 PM PDT 24 105656202 ps
T63 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.492921188 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:35 PM PDT 24 21337902 ps
T57 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3107265244 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:37 PM PDT 24 159782219 ps
T95 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.793086528 Aug 01 05:47:36 PM PDT 24 Aug 01 05:47:37 PM PDT 24 83328971 ps
T73 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3225326092 Aug 01 05:47:17 PM PDT 24 Aug 01 05:47:18 PM PDT 24 53295187 ps
T74 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.859017973 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:36 PM PDT 24 19512214 ps
T118 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3533729761 Aug 01 05:47:29 PM PDT 24 Aug 01 05:47:33 PM PDT 24 296192261 ps
T58 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4152444987 Aug 01 05:47:22 PM PDT 24 Aug 01 05:47:25 PM PDT 24 612824048 ps
T931 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3280815951 Aug 01 05:47:20 PM PDT 24 Aug 01 05:47:23 PM PDT 24 153053673 ps
T75 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2972951736 Aug 01 05:47:21 PM PDT 24 Aug 01 05:47:22 PM PDT 24 27159540 ps
T932 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1560111363 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:36 PM PDT 24 32528255 ps
T933 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1567161171 Aug 01 05:47:50 PM PDT 24 Aug 01 05:47:51 PM PDT 24 109704290 ps
T934 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3557009471 Aug 01 05:47:38 PM PDT 24 Aug 01 05:47:41 PM PDT 24 130128104 ps
T76 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.21482833 Aug 01 05:47:51 PM PDT 24 Aug 01 05:47:51 PM PDT 24 17528077 ps
T77 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3946432402 Aug 01 05:47:21 PM PDT 24 Aug 01 05:47:22 PM PDT 24 12369859 ps
T59 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2667419234 Aug 01 05:47:54 PM PDT 24 Aug 01 05:47:56 PM PDT 24 121083390 ps
T123 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1829713435 Aug 01 05:47:36 PM PDT 24 Aug 01 05:47:38 PM PDT 24 120067582 ps
T78 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.296256230 Aug 01 05:47:53 PM PDT 24 Aug 01 05:47:57 PM PDT 24 1655507029 ps
T935 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3791789311 Aug 01 05:47:54 PM PDT 24 Aug 01 05:47:55 PM PDT 24 31244558 ps
T79 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2218329742 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:39 PM PDT 24 812148500 ps
T936 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.931462745 Aug 01 05:47:32 PM PDT 24 Aug 01 05:47:33 PM PDT 24 45679961 ps
T937 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3146854541 Aug 01 05:47:33 PM PDT 24 Aug 01 05:47:34 PM PDT 24 22698814 ps
T96 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2914384662 Aug 01 05:47:55 PM PDT 24 Aug 01 05:47:55 PM PDT 24 17264504 ps
T80 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2469768597 Aug 01 05:47:19 PM PDT 24 Aug 01 05:47:21 PM PDT 24 830408370 ps
T121 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2527579817 Aug 01 05:47:32 PM PDT 24 Aug 01 05:47:34 PM PDT 24 350279842 ps
T938 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2206226517 Aug 01 05:47:40 PM PDT 24 Aug 01 05:47:41 PM PDT 24 175484832 ps
T81 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3681194068 Aug 01 05:47:36 PM PDT 24 Aug 01 05:47:38 PM PDT 24 336328537 ps
T939 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3314245579 Aug 01 05:47:31 PM PDT 24 Aug 01 05:47:34 PM PDT 24 317743980 ps
T940 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1829850563 Aug 01 05:47:37 PM PDT 24 Aug 01 05:47:38 PM PDT 24 12705775 ps
T82 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2499455563 Aug 01 05:47:31 PM PDT 24 Aug 01 05:47:32 PM PDT 24 18586869 ps
T941 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.574849814 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:36 PM PDT 24 54602302 ps
T942 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3349050879 Aug 01 05:47:31 PM PDT 24 Aug 01 05:47:33 PM PDT 24 662890236 ps
T943 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4095677628 Aug 01 05:47:40 PM PDT 24 Aug 01 05:47:43 PM PDT 24 31237204 ps
T124 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1494664539 Aug 01 05:47:57 PM PDT 24 Aug 01 05:47:58 PM PDT 24 253665835 ps
T122 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1469527100 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:37 PM PDT 24 696723340 ps
T944 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1112769704 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:36 PM PDT 24 29702767 ps
T945 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1964884671 Aug 01 05:47:32 PM PDT 24 Aug 01 05:47:33 PM PDT 24 18006595 ps
T946 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3096422213 Aug 01 05:47:36 PM PDT 24 Aug 01 05:47:37 PM PDT 24 35430607 ps
T947 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3674924079 Aug 01 05:47:38 PM PDT 24 Aug 01 05:47:39 PM PDT 24 49527877 ps
T948 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2916815941 Aug 01 05:47:49 PM PDT 24 Aug 01 05:47:51 PM PDT 24 62090603 ps
T83 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2230870697 Aug 01 05:47:46 PM PDT 24 Aug 01 05:47:50 PM PDT 24 545332772 ps
T949 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1312992731 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:35 PM PDT 24 13448510 ps
T950 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.758970063 Aug 01 05:47:58 PM PDT 24 Aug 01 05:47:59 PM PDT 24 34120630 ps
T127 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4253360883 Aug 01 05:47:40 PM PDT 24 Aug 01 05:47:42 PM PDT 24 250630877 ps
T951 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2478727653 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:36 PM PDT 24 54836124 ps
T952 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1847099007 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:37 PM PDT 24 327465748 ps
T953 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1785308822 Aug 01 05:47:20 PM PDT 24 Aug 01 05:47:22 PM PDT 24 636227287 ps
T954 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3227634442 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:39 PM PDT 24 1293361632 ps
T84 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.955382614 Aug 01 05:47:31 PM PDT 24 Aug 01 05:47:32 PM PDT 24 196700617 ps
T955 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3395675668 Aug 01 05:47:19 PM PDT 24 Aug 01 05:47:20 PM PDT 24 44613992 ps
T85 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1653249894 Aug 01 05:47:49 PM PDT 24 Aug 01 05:47:52 PM PDT 24 1710667056 ps
T956 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1416392080 Aug 01 05:47:21 PM PDT 24 Aug 01 05:47:22 PM PDT 24 34781268 ps
T957 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4066425232 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:35 PM PDT 24 11760073 ps
T958 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2547002543 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:37 PM PDT 24 76027847 ps
T86 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1831501919 Aug 01 05:47:32 PM PDT 24 Aug 01 05:47:34 PM PDT 24 406947843 ps
T959 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.630760867 Aug 01 05:47:21 PM PDT 24 Aug 01 05:47:21 PM PDT 24 57221433 ps
T960 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3956204374 Aug 01 05:47:53 PM PDT 24 Aug 01 05:47:54 PM PDT 24 16044644 ps
T91 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.321970847 Aug 01 05:47:36 PM PDT 24 Aug 01 05:47:37 PM PDT 24 11808501 ps
T961 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3195868266 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:38 PM PDT 24 66893498 ps
T962 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1802014880 Aug 01 05:47:32 PM PDT 24 Aug 01 05:47:33 PM PDT 24 29532099 ps
T963 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.365699638 Aug 01 05:47:32 PM PDT 24 Aug 01 05:47:34 PM PDT 24 113975109 ps
T964 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2341936141 Aug 01 05:47:23 PM PDT 24 Aug 01 05:47:24 PM PDT 24 97580169 ps
T965 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2628655609 Aug 01 05:47:50 PM PDT 24 Aug 01 05:47:51 PM PDT 24 14527998 ps
T966 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1311573927 Aug 01 05:47:33 PM PDT 24 Aug 01 05:47:34 PM PDT 24 371360225 ps
T92 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2621303164 Aug 01 05:47:32 PM PDT 24 Aug 01 05:47:35 PM PDT 24 422544474 ps
T967 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1178926165 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:35 PM PDT 24 35118040 ps
T968 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2792202849 Aug 01 05:47:32 PM PDT 24 Aug 01 05:47:35 PM PDT 24 68213916 ps
T93 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4041262142 Aug 01 05:47:37 PM PDT 24 Aug 01 05:47:40 PM PDT 24 1613858524 ps
T969 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3211426143 Aug 01 05:47:54 PM PDT 24 Aug 01 05:47:56 PM PDT 24 54853259 ps
T970 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3901660850 Aug 01 05:47:20 PM PDT 24 Aug 01 05:47:25 PM PDT 24 2382750751 ps
T971 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3176291294 Aug 01 05:47:33 PM PDT 24 Aug 01 05:47:34 PM PDT 24 21495680 ps
T94 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3464446617 Aug 01 05:47:37 PM PDT 24 Aug 01 05:47:40 PM PDT 24 810739688 ps
T972 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1515402742 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:35 PM PDT 24 161399631 ps
T973 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2247173687 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:39 PM PDT 24 4221422829 ps
T974 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.452911810 Aug 01 05:47:50 PM PDT 24 Aug 01 05:47:51 PM PDT 24 92716201 ps
T975 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3239338781 Aug 01 05:47:52 PM PDT 24 Aug 01 05:47:52 PM PDT 24 11362283 ps
T125 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1322824326 Aug 01 05:47:33 PM PDT 24 Aug 01 05:47:35 PM PDT 24 309471481 ps
T976 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3698845285 Aug 01 05:47:51 PM PDT 24 Aug 01 05:47:53 PM PDT 24 1075689917 ps
T977 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3270318677 Aug 01 05:47:54 PM PDT 24 Aug 01 05:47:56 PM PDT 24 1227462984 ps
T978 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3435247660 Aug 01 05:47:49 PM PDT 24 Aug 01 05:47:51 PM PDT 24 224317049 ps
T979 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1709199796 Aug 01 05:47:58 PM PDT 24 Aug 01 05:47:59 PM PDT 24 45381614 ps
T980 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4265886146 Aug 01 05:47:50 PM PDT 24 Aug 01 05:47:52 PM PDT 24 147962491 ps
T981 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3777420670 Aug 01 05:47:19 PM PDT 24 Aug 01 05:47:21 PM PDT 24 661388980 ps
T982 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1318674169 Aug 01 05:47:53 PM PDT 24 Aug 01 05:47:54 PM PDT 24 130099291 ps
T983 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1039992832 Aug 01 05:47:55 PM PDT 24 Aug 01 05:47:56 PM PDT 24 49147094 ps
T984 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2990875382 Aug 01 05:47:50 PM PDT 24 Aug 01 05:47:52 PM PDT 24 732351430 ps
T985 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3744787802 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:35 PM PDT 24 12862788 ps
T986 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2089569743 Aug 01 05:47:38 PM PDT 24 Aug 01 05:47:39 PM PDT 24 58054775 ps
T987 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4249810318 Aug 01 05:47:37 PM PDT 24 Aug 01 05:47:39 PM PDT 24 114297385 ps
T988 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3049804975 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:36 PM PDT 24 25325605 ps
T989 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3076573316 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:37 PM PDT 24 68543616 ps
T990 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.598769298 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:36 PM PDT 24 26315965 ps
T991 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3236919528 Aug 01 05:47:31 PM PDT 24 Aug 01 05:47:32 PM PDT 24 47322452 ps
T992 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1361377646 Aug 01 05:47:36 PM PDT 24 Aug 01 05:47:39 PM PDT 24 58831949 ps
T993 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.360487711 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:36 PM PDT 24 25007822 ps
T994 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2936876218 Aug 01 05:47:34 PM PDT 24 Aug 01 05:47:38 PM PDT 24 1450430568 ps
T126 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.485479002 Aug 01 05:47:50 PM PDT 24 Aug 01 05:47:51 PM PDT 24 385100671 ps
T995 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2194746771 Aug 01 05:47:49 PM PDT 24 Aug 01 05:47:51 PM PDT 24 225886243 ps
T129 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3784732019 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:38 PM PDT 24 221136152 ps
T130 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4158628353 Aug 01 05:47:54 PM PDT 24 Aug 01 05:47:56 PM PDT 24 185424327 ps
T996 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.240443287 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:35 PM PDT 24 21096791 ps
T997 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1779496814 Aug 01 05:47:35 PM PDT 24 Aug 01 05:47:36 PM PDT 24 15125405 ps
T998 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1879737815 Aug 01 05:47:51 PM PDT 24 Aug 01 05:47:55 PM PDT 24 65915983 ps
T999 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1914267413 Aug 01 05:47:50 PM PDT 24 Aug 01 05:47:54 PM PDT 24 406361663 ps
T1000 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2775203250 Aug 01 05:47:52 PM PDT 24 Aug 01 05:47:54 PM PDT 24 699724698 ps
T1001 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.286489334 Aug 01 05:47:32 PM PDT 24 Aug 01 05:47:33 PM PDT 24 32453275 ps
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