Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145250270	1			T1	106014		T2	581722		T3	19440
instr_valid_dis	107842836	1			T1	307720		T2	581722		T3	19440
instr_en	25938799	1			T1	367888		T21	46		T18	1764

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12106241	1			T1	206140		T21	115318		T18	1764
sram_ifetch_valid_disable	110859328	1			T1	492184		T2	581722		T3	19440
sram_ifetch_enable	22284701	1			T1	361820		T21	52770		T26	199114

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145250270	1			T1	106014		T2	581722		T3	19440
hw_debug_en_valid_off	110536282	1			T1	412264		T2	581722		T3	19440
hw_debug_en_on	23560265	1			T1	560498		T21	250388		T26	227886

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	110859328	1			T1	492184		T2	581722		T3	19440
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	95014807	1			T1	189318		T2	581722		T3	19440
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10816192	1			T1	159244		T26	19372		T125	23554
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4942482	1			T1	50158		T21	47268		T26	41872
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2079880	1			T21	47222		T124	39904		T19	22520
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2081054	1			T1	5618		T21	46		T26	41872
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4594732	1			T1	143166		T21	68050		T26	13738
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1761500	1			T1	472		T21	68050		T26	4754
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1696116	1			T1	5774		T66	17458		T19	64326
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10698782	1			T1	214970		T21	182338		T26	89258
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3722090	1			T1	73262		T21	182338		T26	60694
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5114378	1			T1	65946		T26	2524		T66	32360

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10054045	1			T1	197252		T26	28706		T125	57946
lc_exec_en	8266751	1			T1	202362		T26	124890		T125	76926
valid_exec_dis	103457734	1			T1	382328		T2	581722		T3	19440
invalid_exec_dis	34390942	1			T1	567960		T21	168088		T18	1764