Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42314675	1			T1	260499		T2	264426		T3	8877
triple_byte_access	2422146	1			T1	4475		T2	5295		T3	167
halfword_access	3637792	1			T1	6476		T2	7848		T3	252
byte_access	4855061	1			T1	8774		T2	10599		T3	350
zero_access	1220511	1			T1	2247		T2	2693		T3	74

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27168754

1

T1

141347

T2

145163

T3

4836

auto[1]

27281431

1

T1

141124

T2

145698

T3

4884

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21104859	1			T1	130337		T2	132021		T3	4401
auto[0]	triple_byte_access	1208945	1			T1	2192		T2	2716		T3	88
auto[0]	halfword_access	1814904	1			T1	3292		T2	3876		T3	141
auto[0]	byte_access	2425296	1			T1	4422		T2	5187		T3	167
auto[0]	zero_access	614750	1			T1	1104		T2	1363		T3	39
auto[1]	word_access	21209816	1			T1	130162		T2	132405		T3	4476
auto[1]	triple_byte_access	1213201	1			T1	2283		T2	2579		T3	79
auto[1]	halfword_access	1822888	1			T1	3184		T2	3972		T3	111
auto[1]	byte_access	2429765	1			T1	4352		T2	5412		T3	183
auto[1]	zero_access	605761	1			T1	1143		T2	1330		T3	35