| T795 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.697705797 |
|
|
Aug 02 07:09:12 PM PDT 24 |
Aug 02 07:09:14 PM PDT 24 |
146406755 ps |
| T796 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.2351556864 |
|
|
Aug 02 07:11:58 PM PDT 24 |
Aug 02 07:11:59 PM PDT 24 |
99829819 ps |
| T797 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2319741793 |
|
|
Aug 02 07:10:12 PM PDT 24 |
Aug 02 07:41:18 PM PDT 24 |
3132038217 ps |
| T798 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3953028489 |
|
|
Aug 02 07:08:21 PM PDT 24 |
Aug 02 07:09:41 PM PDT 24 |
403577455 ps |
| T799 |
/workspace/coverage/default/25.sram_ctrl_bijection.2076630996 |
|
|
Aug 02 07:07:33 PM PDT 24 |
Aug 02 07:07:59 PM PDT 24 |
3143516886 ps |
| T800 |
/workspace/coverage/default/23.sram_ctrl_bijection.2748354882 |
|
|
Aug 02 07:06:55 PM PDT 24 |
Aug 02 07:07:59 PM PDT 24 |
1017261740 ps |
| T801 |
/workspace/coverage/default/27.sram_ctrl_executable.1923837682 |
|
|
Aug 02 07:08:34 PM PDT 24 |
Aug 02 07:27:15 PM PDT 24 |
6103518832 ps |
| T802 |
/workspace/coverage/default/43.sram_ctrl_smoke.4294712174 |
|
|
Aug 02 07:13:43 PM PDT 24 |
Aug 02 07:14:40 PM PDT 24 |
913705657 ps |
| T803 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.889983259 |
|
|
Aug 02 07:09:41 PM PDT 24 |
Aug 02 07:15:14 PM PDT 24 |
5427510732 ps |
| T804 |
/workspace/coverage/default/47.sram_ctrl_smoke.2103289707 |
|
|
Aug 02 07:15:04 PM PDT 24 |
Aug 02 07:15:35 PM PDT 24 |
1230022337 ps |
| T805 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.894195861 |
|
|
Aug 02 07:13:03 PM PDT 24 |
Aug 02 07:13:04 PM PDT 24 |
70685457 ps |
| T806 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2554270014 |
|
|
Aug 02 07:01:38 PM PDT 24 |
Aug 02 07:01:56 PM PDT 24 |
638985398 ps |
| T807 |
/workspace/coverage/default/15.sram_ctrl_stress_all.3395799733 |
|
|
Aug 02 07:04:16 PM PDT 24 |
Aug 02 07:56:16 PM PDT 24 |
42114639230 ps |
| T808 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.151596213 |
|
|
Aug 02 07:07:03 PM PDT 24 |
Aug 02 07:27:41 PM PDT 24 |
7293467550 ps |
| T809 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.526924609 |
|
|
Aug 02 07:12:15 PM PDT 24 |
Aug 02 07:12:16 PM PDT 24 |
60060867 ps |
| T810 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2017928819 |
|
|
Aug 02 07:09:59 PM PDT 24 |
Aug 02 07:10:48 PM PDT 24 |
442372640 ps |
| T811 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.355353799 |
|
|
Aug 02 07:01:40 PM PDT 24 |
Aug 02 07:04:01 PM PDT 24 |
289865546 ps |
| T812 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2959616236 |
|
|
Aug 02 07:13:46 PM PDT 24 |
Aug 02 07:13:52 PM PDT 24 |
69600527 ps |
| T813 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.855415119 |
|
|
Aug 02 07:04:20 PM PDT 24 |
Aug 02 07:25:31 PM PDT 24 |
47330493812 ps |
| T814 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1254384787 |
|
|
Aug 02 07:11:39 PM PDT 24 |
Aug 02 07:11:44 PM PDT 24 |
127679647 ps |
| T815 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1585639642 |
|
|
Aug 02 07:14:26 PM PDT 24 |
Aug 02 07:14:46 PM PDT 24 |
181228737 ps |
| T816 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3195197885 |
|
|
Aug 02 07:15:27 PM PDT 24 |
Aug 02 07:15:46 PM PDT 24 |
177608450 ps |
| T817 |
/workspace/coverage/default/32.sram_ctrl_regwen.773718561 |
|
|
Aug 02 07:10:26 PM PDT 24 |
Aug 02 07:23:05 PM PDT 24 |
13282804454 ps |
| T818 |
/workspace/coverage/default/1.sram_ctrl_executable.1626544812 |
|
|
Aug 02 06:58:51 PM PDT 24 |
Aug 02 07:26:55 PM PDT 24 |
52240945134 ps |
| T819 |
/workspace/coverage/default/29.sram_ctrl_regwen.2632769242 |
|
|
Aug 02 07:09:27 PM PDT 24 |
Aug 02 07:23:50 PM PDT 24 |
4111922967 ps |
| T820 |
/workspace/coverage/default/10.sram_ctrl_smoke.3828938034 |
|
|
Aug 02 07:02:34 PM PDT 24 |
Aug 02 07:03:29 PM PDT 24 |
1867513428 ps |
| T821 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3887698141 |
|
|
Aug 02 07:09:44 PM PDT 24 |
Aug 02 07:11:57 PM PDT 24 |
593057735 ps |
| T822 |
/workspace/coverage/default/10.sram_ctrl_partial_access.491690550 |
|
|
Aug 02 07:02:33 PM PDT 24 |
Aug 02 07:02:44 PM PDT 24 |
213265762 ps |
| T823 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1967779335 |
|
|
Aug 02 07:07:46 PM PDT 24 |
Aug 02 07:09:32 PM PDT 24 |
134305998 ps |
| T824 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.3061773806 |
|
|
Aug 02 07:13:02 PM PDT 24 |
Aug 02 07:14:12 PM PDT 24 |
128460275 ps |
| T825 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.621067441 |
|
|
Aug 02 07:15:30 PM PDT 24 |
Aug 02 07:33:47 PM PDT 24 |
1879401750 ps |
| T826 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3508887690 |
|
|
Aug 02 07:14:02 PM PDT 24 |
Aug 02 07:17:48 PM PDT 24 |
39394697272 ps |
| T827 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3108664633 |
|
|
Aug 02 07:02:16 PM PDT 24 |
Aug 02 07:16:11 PM PDT 24 |
8370663133 ps |
| T828 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.100260640 |
|
|
Aug 02 07:13:33 PM PDT 24 |
Aug 02 07:13:36 PM PDT 24 |
184030838 ps |
| T829 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.4111416446 |
|
|
Aug 02 07:01:39 PM PDT 24 |
Aug 02 07:01:40 PM PDT 24 |
90232502 ps |
| T830 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.1437855503 |
|
|
Aug 02 07:11:38 PM PDT 24 |
Aug 02 07:11:46 PM PDT 24 |
1830934790 ps |
| T831 |
/workspace/coverage/default/2.sram_ctrl_smoke.2382765475 |
|
|
Aug 02 06:59:16 PM PDT 24 |
Aug 02 06:59:27 PM PDT 24 |
1813969242 ps |
| T832 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3821364761 |
|
|
Aug 02 07:14:01 PM PDT 24 |
Aug 02 07:14:11 PM PDT 24 |
357461754 ps |
| T833 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2236472217 |
|
|
Aug 02 07:13:03 PM PDT 24 |
Aug 02 07:14:46 PM PDT 24 |
240405616 ps |
| T834 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.132639545 |
|
|
Aug 02 07:09:27 PM PDT 24 |
Aug 02 07:09:33 PM PDT 24 |
347120906 ps |
| T835 |
/workspace/coverage/default/30.sram_ctrl_partial_access.3644222050 |
|
|
Aug 02 07:09:44 PM PDT 24 |
Aug 02 07:10:53 PM PDT 24 |
1663983767 ps |
| T836 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2376823064 |
|
|
Aug 02 07:13:03 PM PDT 24 |
Aug 02 07:31:38 PM PDT 24 |
2457500320 ps |
| T837 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3967859671 |
|
|
Aug 02 07:01:39 PM PDT 24 |
Aug 02 07:01:42 PM PDT 24 |
100658010 ps |
| T838 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1054551513 |
|
|
Aug 02 07:01:40 PM PDT 24 |
Aug 02 07:01:43 PM PDT 24 |
510912679 ps |
| T839 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3814002524 |
|
|
Aug 02 06:58:42 PM PDT 24 |
Aug 02 07:21:38 PM PDT 24 |
5262813982 ps |
| T840 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2091024731 |
|
|
Aug 02 07:15:04 PM PDT 24 |
Aug 02 07:15:04 PM PDT 24 |
22492547 ps |
| T841 |
/workspace/coverage/default/7.sram_ctrl_bijection.2457989802 |
|
|
Aug 02 07:01:39 PM PDT 24 |
Aug 02 07:02:13 PM PDT 24 |
640597838 ps |
| T842 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.3911817743 |
|
|
Aug 02 07:06:15 PM PDT 24 |
Aug 02 07:10:50 PM PDT 24 |
2885428499 ps |
| T843 |
/workspace/coverage/default/19.sram_ctrl_partial_access.4125779207 |
|
|
Aug 02 07:05:28 PM PDT 24 |
Aug 02 07:05:57 PM PDT 24 |
1400314617 ps |
| T844 |
/workspace/coverage/default/18.sram_ctrl_executable.3774109150 |
|
|
Aug 02 07:05:07 PM PDT 24 |
Aug 02 07:10:21 PM PDT 24 |
3711274511 ps |
| T845 |
/workspace/coverage/default/33.sram_ctrl_regwen.3520732802 |
|
|
Aug 02 07:10:42 PM PDT 24 |
Aug 02 07:20:37 PM PDT 24 |
17204295083 ps |
| T846 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.718236858 |
|
|
Aug 02 06:59:31 PM PDT 24 |
Aug 02 07:18:13 PM PDT 24 |
10553653979 ps |
| T847 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.588040014 |
|
|
Aug 02 07:09:43 PM PDT 24 |
Aug 02 07:12:27 PM PDT 24 |
3218218861 ps |
| T848 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3815618287 |
|
|
Aug 02 07:04:34 PM PDT 24 |
Aug 02 07:04:45 PM PDT 24 |
204125651 ps |
| T849 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.4228861981 |
|
|
Aug 02 06:58:29 PM PDT 24 |
Aug 02 06:59:26 PM PDT 24 |
98540950 ps |
| T850 |
/workspace/coverage/default/36.sram_ctrl_partial_access.2476656948 |
|
|
Aug 02 07:11:38 PM PDT 24 |
Aug 02 07:11:53 PM PDT 24 |
957121939 ps |
| T851 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.658444768 |
|
|
Aug 02 07:00:34 PM PDT 24 |
Aug 02 07:04:27 PM PDT 24 |
4594498111 ps |
| T852 |
/workspace/coverage/default/3.sram_ctrl_bijection.2353646032 |
|
|
Aug 02 06:59:32 PM PDT 24 |
Aug 02 07:00:33 PM PDT 24 |
2915239546 ps |
| T853 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2351123466 |
|
|
Aug 02 07:06:16 PM PDT 24 |
Aug 02 07:06:17 PM PDT 24 |
31110811 ps |
| T854 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3791774738 |
|
|
Aug 02 07:08:19 PM PDT 24 |
Aug 02 07:16:24 PM PDT 24 |
10974358885 ps |
| T855 |
/workspace/coverage/default/26.sram_ctrl_alert_test.923256557 |
|
|
Aug 02 07:08:07 PM PDT 24 |
Aug 02 07:08:08 PM PDT 24 |
13971763 ps |
| T856 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.145413281 |
|
|
Aug 02 07:14:26 PM PDT 24 |
Aug 02 07:18:21 PM PDT 24 |
5019569891 ps |
| T857 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1551884429 |
|
|
Aug 02 07:11:41 PM PDT 24 |
Aug 02 07:17:35 PM PDT 24 |
10283515540 ps |
| T858 |
/workspace/coverage/default/9.sram_ctrl_bijection.569783719 |
|
|
Aug 02 07:01:51 PM PDT 24 |
Aug 02 07:03:09 PM PDT 24 |
19837090437 ps |
| T859 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3953022958 |
|
|
Aug 02 07:12:26 PM PDT 24 |
Aug 02 07:17:08 PM PDT 24 |
3882764846 ps |
| T860 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3061622199 |
|
|
Aug 02 06:58:52 PM PDT 24 |
Aug 02 07:02:55 PM PDT 24 |
6556844329 ps |
| T861 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1696877065 |
|
|
Aug 02 07:01:53 PM PDT 24 |
Aug 02 07:14:49 PM PDT 24 |
8453535393 ps |
| T862 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3509094182 |
|
|
Aug 02 07:15:53 PM PDT 24 |
Aug 02 07:15:54 PM PDT 24 |
27780457 ps |
| T863 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.3165768392 |
|
|
Aug 02 07:03:43 PM PDT 24 |
Aug 02 07:03:50 PM PDT 24 |
1600277088 ps |
| T864 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3576379213 |
|
|
Aug 02 07:09:14 PM PDT 24 |
Aug 02 07:13:02 PM PDT 24 |
9177089137 ps |
| T865 |
/workspace/coverage/default/4.sram_ctrl_executable.2141525773 |
|
|
Aug 02 07:00:18 PM PDT 24 |
Aug 02 07:15:01 PM PDT 24 |
97600008416 ps |
| T866 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1443126679 |
|
|
Aug 02 07:04:03 PM PDT 24 |
Aug 02 07:20:56 PM PDT 24 |
11033316074 ps |
| T867 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.336899283 |
|
|
Aug 02 07:08:07 PM PDT 24 |
Aug 02 07:22:18 PM PDT 24 |
1903893486 ps |
| T868 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3378125606 |
|
|
Aug 02 07:07:25 PM PDT 24 |
Aug 02 07:07:37 PM PDT 24 |
1826021769 ps |
| T869 |
/workspace/coverage/default/35.sram_ctrl_bijection.419745490 |
|
|
Aug 02 07:11:39 PM PDT 24 |
Aug 02 07:12:04 PM PDT 24 |
1539017547 ps |
| T870 |
/workspace/coverage/default/49.sram_ctrl_executable.2310539209 |
|
|
Aug 02 07:15:55 PM PDT 24 |
Aug 02 07:33:27 PM PDT 24 |
17102121634 ps |
| T871 |
/workspace/coverage/default/7.sram_ctrl_smoke.2902502241 |
|
|
Aug 02 07:01:40 PM PDT 24 |
Aug 02 07:01:54 PM PDT 24 |
243171119 ps |
| T872 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.1879370228 |
|
|
Aug 02 07:11:39 PM PDT 24 |
Aug 02 07:11:40 PM PDT 24 |
86198971 ps |
| T873 |
/workspace/coverage/default/46.sram_ctrl_executable.1292300031 |
|
|
Aug 02 07:15:04 PM PDT 24 |
Aug 02 07:26:31 PM PDT 24 |
6434368701 ps |
| T874 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4040721735 |
|
|
Aug 02 06:58:29 PM PDT 24 |
Aug 02 06:58:32 PM PDT 24 |
48944281 ps |
| T875 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.127381440 |
|
|
Aug 02 07:05:43 PM PDT 24 |
Aug 02 07:20:31 PM PDT 24 |
12200683177 ps |
| T876 |
/workspace/coverage/default/32.sram_ctrl_alert_test.103063449 |
|
|
Aug 02 07:10:26 PM PDT 24 |
Aug 02 07:10:27 PM PDT 24 |
14743640 ps |
| T877 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.291843347 |
|
|
Aug 02 07:02:32 PM PDT 24 |
Aug 02 07:17:10 PM PDT 24 |
9968564656 ps |
| T878 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1439695578 |
|
|
Aug 02 07:08:19 PM PDT 24 |
Aug 02 07:12:07 PM PDT 24 |
3099634870 ps |
| T879 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3385530229 |
|
|
Aug 02 07:09:58 PM PDT 24 |
Aug 02 07:09:59 PM PDT 24 |
78068027 ps |
| T880 |
/workspace/coverage/default/30.sram_ctrl_alert_test.4229159206 |
|
|
Aug 02 07:09:59 PM PDT 24 |
Aug 02 07:09:59 PM PDT 24 |
118422986 ps |
| T881 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3920586470 |
|
|
Aug 02 07:01:41 PM PDT 24 |
Aug 02 07:05:16 PM PDT 24 |
2323696825 ps |
| T882 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2921758606 |
|
|
Aug 02 07:07:21 PM PDT 24 |
Aug 02 07:08:36 PM PDT 24 |
2430542343 ps |
| T883 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2146468029 |
|
|
Aug 02 07:15:15 PM PDT 24 |
Aug 02 07:17:32 PM PDT 24 |
2619816704 ps |
| T884 |
/workspace/coverage/default/15.sram_ctrl_regwen.2205771507 |
|
|
Aug 02 07:04:09 PM PDT 24 |
Aug 02 07:07:28 PM PDT 24 |
6409941152 ps |
| T885 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.981092662 |
|
|
Aug 02 07:07:47 PM PDT 24 |
Aug 02 07:07:55 PM PDT 24 |
553740738 ps |
| T886 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.634024512 |
|
|
Aug 02 06:58:52 PM PDT 24 |
Aug 02 07:10:34 PM PDT 24 |
13397376758 ps |
| T887 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.4143801834 |
|
|
Aug 02 07:14:49 PM PDT 24 |
Aug 02 07:42:18 PM PDT 24 |
44612945325 ps |
| T888 |
/workspace/coverage/default/49.sram_ctrl_regwen.2721308847 |
|
|
Aug 02 07:15:52 PM PDT 24 |
Aug 02 07:37:11 PM PDT 24 |
105819655726 ps |
| T889 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2734932095 |
|
|
Aug 02 07:01:40 PM PDT 24 |
Aug 02 07:01:46 PM PDT 24 |
344806008 ps |
| T890 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1457573709 |
|
|
Aug 02 07:01:41 PM PDT 24 |
Aug 02 07:01:43 PM PDT 24 |
180021147 ps |
| T891 |
/workspace/coverage/default/43.sram_ctrl_bijection.2176527480 |
|
|
Aug 02 07:13:45 PM PDT 24 |
Aug 02 07:14:58 PM PDT 24 |
9582965928 ps |
| T892 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.2844480862 |
|
|
Aug 02 07:04:02 PM PDT 24 |
Aug 02 07:04:03 PM PDT 24 |
112689372 ps |
| T893 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3829182012 |
|
|
Aug 02 07:09:11 PM PDT 24 |
Aug 02 07:12:04 PM PDT 24 |
5410587766 ps |
| T894 |
/workspace/coverage/default/16.sram_ctrl_smoke.1714661618 |
|
|
Aug 02 07:04:21 PM PDT 24 |
Aug 02 07:05:03 PM PDT 24 |
416586912 ps |
| T895 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1796458797 |
|
|
Aug 02 07:01:20 PM PDT 24 |
Aug 02 07:11:27 PM PDT 24 |
2880844335 ps |
| T896 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2031628557 |
|
|
Aug 02 07:10:28 PM PDT 24 |
Aug 02 07:15:03 PM PDT 24 |
5856506919 ps |
| T897 |
/workspace/coverage/default/47.sram_ctrl_stress_all.2249960125 |
|
|
Aug 02 07:15:28 PM PDT 24 |
Aug 02 07:19:07 PM PDT 24 |
1321290242 ps |
| T898 |
/workspace/coverage/default/13.sram_ctrl_alert_test.4253476220 |
|
|
Aug 02 07:03:39 PM PDT 24 |
Aug 02 07:03:40 PM PDT 24 |
13773960 ps |
| T899 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3099961834 |
|
|
Aug 02 07:14:26 PM PDT 24 |
Aug 02 07:27:39 PM PDT 24 |
13049614813 ps |
| T900 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.4202521304 |
|
|
Aug 02 07:06:28 PM PDT 24 |
Aug 02 07:14:48 PM PDT 24 |
7440832184 ps |
| T901 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.366602517 |
|
|
Aug 02 07:10:10 PM PDT 24 |
Aug 02 07:30:19 PM PDT 24 |
12951364122 ps |
| T902 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.766260957 |
|
|
Aug 02 07:08:08 PM PDT 24 |
Aug 02 07:08:09 PM PDT 24 |
81430953 ps |
| T903 |
/workspace/coverage/default/38.sram_ctrl_bijection.1452435598 |
|
|
Aug 02 07:12:13 PM PDT 24 |
Aug 02 07:13:07 PM PDT 24 |
3300153038 ps |
| T904 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.3982055695 |
|
|
Aug 02 07:10:11 PM PDT 24 |
Aug 02 07:10:49 PM PDT 24 |
367140722 ps |
| T905 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3680038528 |
|
|
Aug 02 06:59:45 PM PDT 24 |
Aug 02 07:06:49 PM PDT 24 |
29859419272 ps |
| T906 |
/workspace/coverage/default/11.sram_ctrl_bijection.2245335873 |
|
|
Aug 02 07:02:45 PM PDT 24 |
Aug 02 07:03:53 PM PDT 24 |
8577539948 ps |
| T907 |
/workspace/coverage/default/37.sram_ctrl_regwen.2997614494 |
|
|
Aug 02 07:11:56 PM PDT 24 |
Aug 02 07:32:03 PM PDT 24 |
27097243604 ps |
| T908 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.1566531794 |
|
|
Aug 02 07:09:14 PM PDT 24 |
Aug 02 07:09:15 PM PDT 24 |
58787790 ps |
| T909 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.1635619356 |
|
|
Aug 02 07:02:02 PM PDT 24 |
Aug 02 07:03:35 PM PDT 24 |
112839405 ps |
| T910 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.4221027119 |
|
|
Aug 02 07:11:02 PM PDT 24 |
Aug 02 07:14:54 PM PDT 24 |
9451776200 ps |
| T911 |
/workspace/coverage/default/5.sram_ctrl_partial_access.4167959672 |
|
|
Aug 02 07:00:36 PM PDT 24 |
Aug 02 07:02:31 PM PDT 24 |
586770218 ps |
| T912 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2998592226 |
|
|
Aug 02 07:15:52 PM PDT 24 |
Aug 02 07:17:47 PM PDT 24 |
1623381655 ps |
| T913 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3170039985 |
|
|
Aug 02 07:01:39 PM PDT 24 |
Aug 02 07:02:00 PM PDT 24 |
100057471 ps |
| T914 |
/workspace/coverage/default/31.sram_ctrl_bijection.932997961 |
|
|
Aug 02 07:09:58 PM PDT 24 |
Aug 02 07:10:34 PM PDT 24 |
2297914877 ps |
| T915 |
/workspace/coverage/default/27.sram_ctrl_regwen.1982351240 |
|
|
Aug 02 07:08:33 PM PDT 24 |
Aug 02 07:12:31 PM PDT 24 |
4081424113 ps |
| T916 |
/workspace/coverage/default/17.sram_ctrl_smoke.1828702175 |
|
|
Aug 02 07:04:50 PM PDT 24 |
Aug 02 07:04:57 PM PDT 24 |
122267529 ps |
| T917 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2620018135 |
|
|
Aug 02 07:15:15 PM PDT 24 |
Aug 02 07:15:16 PM PDT 24 |
32457031 ps |
| T918 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1166730991 |
|
|
Aug 02 07:11:39 PM PDT 24 |
Aug 02 07:17:14 PM PDT 24 |
3563642201 ps |
| T919 |
/workspace/coverage/default/27.sram_ctrl_alert_test.739279073 |
|
|
Aug 02 07:08:55 PM PDT 24 |
Aug 02 07:08:56 PM PDT 24 |
26239184 ps |
| T920 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4258250715 |
|
|
Aug 02 07:02:44 PM PDT 24 |
Aug 02 07:02:53 PM PDT 24 |
66952626 ps |
| T921 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.411533131 |
|
|
Aug 02 07:04:51 PM PDT 24 |
Aug 02 07:10:22 PM PDT 24 |
978770819 ps |
| T922 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.4094452473 |
|
|
Aug 02 07:07:04 PM PDT 24 |
Aug 02 07:07:05 PM PDT 24 |
137425329 ps |
| T923 |
/workspace/coverage/default/17.sram_ctrl_regwen.3059411867 |
|
|
Aug 02 07:04:56 PM PDT 24 |
Aug 02 07:18:48 PM PDT 24 |
25570086945 ps |
| T924 |
/workspace/coverage/default/31.sram_ctrl_executable.4156280977 |
|
|
Aug 02 07:10:12 PM PDT 24 |
Aug 02 07:21:30 PM PDT 24 |
6359560607 ps |
| T925 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4027013557 |
|
|
Aug 02 07:12:16 PM PDT 24 |
Aug 02 07:17:00 PM PDT 24 |
22458984642 ps |
| T926 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2832501786 |
|
|
Aug 02 07:13:17 PM PDT 24 |
Aug 02 07:16:54 PM PDT 24 |
4383915743 ps |
| T927 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1885112940 |
|
|
Aug 02 07:12:46 PM PDT 24 |
Aug 02 07:37:39 PM PDT 24 |
3895325205 ps |
| T928 |
/workspace/coverage/default/30.sram_ctrl_regwen.3100298701 |
|
|
Aug 02 07:09:43 PM PDT 24 |
Aug 02 07:09:59 PM PDT 24 |
826977103 ps |
| T929 |
/workspace/coverage/default/13.sram_ctrl_smoke.3245724716 |
|
|
Aug 02 07:03:11 PM PDT 24 |
Aug 02 07:03:30 PM PDT 24 |
3464840690 ps |
| T930 |
/workspace/coverage/default/23.sram_ctrl_executable.644781627 |
|
|
Aug 02 07:07:02 PM PDT 24 |
Aug 02 07:22:25 PM PDT 24 |
5145016498 ps |
| T931 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.200591331 |
|
|
Aug 02 07:13:03 PM PDT 24 |
Aug 02 07:17:29 PM PDT 24 |
22886036813 ps |
| T932 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1095384572 |
|
|
Aug 02 07:15:40 PM PDT 24 |
Aug 02 07:15:41 PM PDT 24 |
16027425 ps |
| T933 |
/workspace/coverage/default/47.sram_ctrl_executable.3507632008 |
|
|
Aug 02 07:15:17 PM PDT 24 |
Aug 02 07:25:09 PM PDT 24 |
25229594882 ps |
| T934 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3065339638 |
|
|
Aug 02 07:04:50 PM PDT 24 |
Aug 02 07:05:47 PM PDT 24 |
413028467 ps |
| T935 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3406417248 |
|
|
Aug 02 06:43:49 PM PDT 24 |
Aug 02 06:43:52 PM PDT 24 |
40747377 ps |
| T63 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.288636809 |
|
|
Aug 02 06:43:39 PM PDT 24 |
Aug 02 06:43:41 PM PDT 24 |
584302499 ps |
| T67 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.997660997 |
|
|
Aug 02 06:44:02 PM PDT 24 |
Aug 02 06:44:03 PM PDT 24 |
22280117 ps |
| T108 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1582165251 |
|
|
Aug 02 06:43:45 PM PDT 24 |
Aug 02 06:43:46 PM PDT 24 |
294986908 ps |
| T68 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2204131699 |
|
|
Aug 02 06:43:49 PM PDT 24 |
Aug 02 06:43:52 PM PDT 24 |
1639950393 ps |
| T109 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.901522521 |
|
|
Aug 02 06:43:47 PM PDT 24 |
Aug 02 06:43:51 PM PDT 24 |
160013722 ps |
| T936 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2163058489 |
|
|
Aug 02 06:43:47 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
196196070 ps |
| T937 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3729434988 |
|
|
Aug 02 06:43:43 PM PDT 24 |
Aug 02 06:43:45 PM PDT 24 |
92697071 ps |
| T64 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.835806299 |
|
|
Aug 02 06:43:58 PM PDT 24 |
Aug 02 06:44:00 PM PDT 24 |
171841963 ps |
| T98 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.699389732 |
|
|
Aug 02 06:44:00 PM PDT 24 |
Aug 02 06:44:01 PM PDT 24 |
45297192 ps |
| T99 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3783639569 |
|
|
Aug 02 06:43:50 PM PDT 24 |
Aug 02 06:43:50 PM PDT 24 |
22621828 ps |
| T100 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.723451732 |
|
|
Aug 02 06:43:44 PM PDT 24 |
Aug 02 06:43:45 PM PDT 24 |
77205135 ps |
| T65 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3884403281 |
|
|
Aug 02 06:43:49 PM PDT 24 |
Aug 02 06:43:51 PM PDT 24 |
554911037 ps |
| T74 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.168766221 |
|
|
Aug 02 06:43:53 PM PDT 24 |
Aug 02 06:43:57 PM PDT 24 |
396162736 ps |
| T938 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2231210551 |
|
|
Aug 02 06:43:49 PM PDT 24 |
Aug 02 06:43:50 PM PDT 24 |
244605395 ps |
| T101 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2534825359 |
|
|
Aug 02 06:43:40 PM PDT 24 |
Aug 02 06:43:41 PM PDT 24 |
25903391 ps |
| T75 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1439617611 |
|
|
Aug 02 06:43:39 PM PDT 24 |
Aug 02 06:43:40 PM PDT 24 |
16359068 ps |
| T76 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3036016213 |
|
|
Aug 02 06:43:48 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
33495697 ps |
| T104 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.114489915 |
|
|
Aug 02 06:43:53 PM PDT 24 |
Aug 02 06:43:54 PM PDT 24 |
59167683 ps |
| T77 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3819820235 |
|
|
Aug 02 06:43:46 PM PDT 24 |
Aug 02 06:43:47 PM PDT 24 |
78150157 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1746643082 |
|
|
Aug 02 06:43:39 PM PDT 24 |
Aug 02 06:43:40 PM PDT 24 |
11234239 ps |
| T79 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2833210012 |
|
|
Aug 02 06:44:02 PM PDT 24 |
Aug 02 06:44:04 PM PDT 24 |
221694293 ps |
| T939 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1551634222 |
|
|
Aug 02 06:43:45 PM PDT 24 |
Aug 02 06:43:46 PM PDT 24 |
14543063 ps |
| T80 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2406460681 |
|
|
Aug 02 06:43:49 PM PDT 24 |
Aug 02 06:43:50 PM PDT 24 |
50304976 ps |
| T115 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3957804134 |
|
|
Aug 02 06:43:46 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
2904132727 ps |
| T81 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3456538320 |
|
|
Aug 02 06:43:46 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
435790908 ps |
| T110 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1841184379 |
|
|
Aug 02 06:43:58 PM PDT 24 |
Aug 02 06:44:00 PM PDT 24 |
341823692 ps |
| T940 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1043634931 |
|
|
Aug 02 06:43:52 PM PDT 24 |
Aug 02 06:43:53 PM PDT 24 |
25688343 ps |
| T941 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1903567053 |
|
|
Aug 02 06:44:01 PM PDT 24 |
Aug 02 06:44:02 PM PDT 24 |
25372691 ps |
| T82 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2449418133 |
|
|
Aug 02 06:43:50 PM PDT 24 |
Aug 02 06:43:51 PM PDT 24 |
16870133 ps |
| T942 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3590615936 |
|
|
Aug 02 06:43:40 PM PDT 24 |
Aug 02 06:43:42 PM PDT 24 |
60747725 ps |
| T943 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.427175414 |
|
|
Aug 02 06:44:00 PM PDT 24 |
Aug 02 06:44:01 PM PDT 24 |
56545000 ps |
| T111 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2937947949 |
|
|
Aug 02 06:43:49 PM PDT 24 |
Aug 02 06:43:53 PM PDT 24 |
105020516 ps |
| T83 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3696218567 |
|
|
Aug 02 06:43:48 PM PDT 24 |
Aug 02 06:43:51 PM PDT 24 |
1807300034 ps |
| T944 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1037306999 |
|
|
Aug 02 06:43:46 PM PDT 24 |
Aug 02 06:43:48 PM PDT 24 |
38635282 ps |
| T945 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2570791528 |
|
|
Aug 02 06:44:02 PM PDT 24 |
Aug 02 06:44:06 PM PDT 24 |
110510814 ps |
| T112 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2514937019 |
|
|
Aug 02 06:43:50 PM PDT 24 |
Aug 02 06:43:52 PM PDT 24 |
76480684 ps |
| T946 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2953199499 |
|
|
Aug 02 06:43:53 PM PDT 24 |
Aug 02 06:43:54 PM PDT 24 |
35223028 ps |
| T947 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3952112258 |
|
|
Aug 02 06:43:47 PM PDT 24 |
Aug 02 06:43:51 PM PDT 24 |
120030102 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.895069899 |
|
|
Aug 02 06:43:44 PM PDT 24 |
Aug 02 06:43:45 PM PDT 24 |
23368789 ps |
| T84 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2624324669 |
|
|
Aug 02 06:44:00 PM PDT 24 |
Aug 02 06:44:01 PM PDT 24 |
17714960 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3200900129 |
|
|
Aug 02 06:43:39 PM PDT 24 |
Aug 02 06:43:39 PM PDT 24 |
15877597 ps |
| T950 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3621118299 |
|
|
Aug 02 06:44:00 PM PDT 24 |
Aug 02 06:44:01 PM PDT 24 |
33013048 ps |
| T117 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3605914186 |
|
|
Aug 02 06:44:00 PM PDT 24 |
Aug 02 06:44:03 PM PDT 24 |
198681316 ps |
| T120 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2982523294 |
|
|
Aug 02 06:43:41 PM PDT 24 |
Aug 02 06:43:44 PM PDT 24 |
265952645 ps |
| T85 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1270643557 |
|
|
Aug 02 06:44:00 PM PDT 24 |
Aug 02 06:44:04 PM PDT 24 |
1552546928 ps |
| T86 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1008747711 |
|
|
Aug 02 06:44:00 PM PDT 24 |
Aug 02 06:44:04 PM PDT 24 |
1186924373 ps |
| T116 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4247625721 |
|
|
Aug 02 06:43:49 PM PDT 24 |
Aug 02 06:43:51 PM PDT 24 |
193408424 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3528551102 |
|
|
Aug 02 06:43:42 PM PDT 24 |
Aug 02 06:43:43 PM PDT 24 |
20119654 ps |
| T951 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2511000933 |
|
|
Aug 02 06:43:47 PM PDT 24 |
Aug 02 06:43:48 PM PDT 24 |
39176552 ps |
| T952 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4278554500 |
|
|
Aug 02 06:43:46 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
237386910 ps |
| T93 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2958517995 |
|
|
Aug 02 06:43:43 PM PDT 24 |
Aug 02 06:43:45 PM PDT 24 |
344299190 ps |
| T953 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.135715741 |
|
|
Aug 02 06:43:53 PM PDT 24 |
Aug 02 06:43:57 PM PDT 24 |
684576584 ps |
| T954 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1258597072 |
|
|
Aug 02 06:43:38 PM PDT 24 |
Aug 02 06:43:39 PM PDT 24 |
48385006 ps |
| T955 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1979893428 |
|
|
Aug 02 06:44:00 PM PDT 24 |
Aug 02 06:44:02 PM PDT 24 |
214396114 ps |
| T956 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2419139452 |
|
|
Aug 02 06:44:04 PM PDT 24 |
Aug 02 06:44:08 PM PDT 24 |
125634863 ps |
| T957 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3520155707 |
|
|
Aug 02 06:43:45 PM PDT 24 |
Aug 02 06:43:47 PM PDT 24 |
248680301 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2789092275 |
|
|
Aug 02 06:43:50 PM PDT 24 |
Aug 02 06:43:52 PM PDT 24 |
242752419 ps |
| T959 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.192668046 |
|
|
Aug 02 06:44:02 PM PDT 24 |
Aug 02 06:44:04 PM PDT 24 |
72210389 ps |
| T94 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1328562473 |
|
|
Aug 02 06:43:47 PM PDT 24 |
Aug 02 06:43:50 PM PDT 24 |
218855499 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2758654278 |
|
|
Aug 02 06:43:44 PM PDT 24 |
Aug 02 06:43:47 PM PDT 24 |
94085563 ps |
| T961 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2920461042 |
|
|
Aug 02 06:43:41 PM PDT 24 |
Aug 02 06:43:42 PM PDT 24 |
28763308 ps |
| T95 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3506027469 |
|
|
Aug 02 06:43:45 PM PDT 24 |
Aug 02 06:43:46 PM PDT 24 |
33733494 ps |
| T962 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.475684367 |
|
|
Aug 02 06:43:46 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
721215038 ps |
| T963 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2577072986 |
|
|
Aug 02 06:44:00 PM PDT 24 |
Aug 02 06:44:01 PM PDT 24 |
84966702 ps |
| T964 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.497119704 |
|
|
Aug 02 06:44:02 PM PDT 24 |
Aug 02 06:44:03 PM PDT 24 |
33911023 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.774455696 |
|
|
Aug 02 06:43:47 PM PDT 24 |
Aug 02 06:43:48 PM PDT 24 |
33712047 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2878882166 |
|
|
Aug 02 06:43:58 PM PDT 24 |
Aug 02 06:44:02 PM PDT 24 |
45126740 ps |
| T96 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1675944743 |
|
|
Aug 02 06:43:47 PM PDT 24 |
Aug 02 06:43:51 PM PDT 24 |
1540828939 ps |
| T967 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2776469490 |
|
|
Aug 02 06:43:53 PM PDT 24 |
Aug 02 06:43:54 PM PDT 24 |
89618415 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2223935014 |
|
|
Aug 02 06:43:36 PM PDT 24 |
Aug 02 06:43:37 PM PDT 24 |
61014793 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.426065676 |
|
|
Aug 02 06:43:47 PM PDT 24 |
Aug 02 06:43:48 PM PDT 24 |
67769776 ps |
| T970 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4069140618 |
|
|
Aug 02 06:43:46 PM PDT 24 |
Aug 02 06:43:48 PM PDT 24 |
150650290 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.70366315 |
|
|
Aug 02 06:43:39 PM PDT 24 |
Aug 02 06:43:41 PM PDT 24 |
78195549 ps |
| T972 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1643062162 |
|
|
Aug 02 06:43:48 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
440746422 ps |
| T973 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.578680444 |
|
|
Aug 02 06:43:58 PM PDT 24 |
Aug 02 06:44:00 PM PDT 24 |
148923719 ps |
| T974 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.109664248 |
|
|
Aug 02 06:43:51 PM PDT 24 |
Aug 02 06:43:52 PM PDT 24 |
14404477 ps |
| T121 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3384791221 |
|
|
Aug 02 06:43:54 PM PDT 24 |
Aug 02 06:43:55 PM PDT 24 |
354560619 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2591627219 |
|
|
Aug 02 06:43:59 PM PDT 24 |
Aug 02 06:44:02 PM PDT 24 |
82096962 ps |
| T976 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.916434667 |
|
|
Aug 02 06:43:50 PM PDT 24 |
Aug 02 06:43:52 PM PDT 24 |
203315128 ps |
| T97 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.797635555 |
|
|
Aug 02 06:43:48 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
21813969 ps |
| T977 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.381530051 |
|
|
Aug 02 06:43:49 PM PDT 24 |
Aug 02 06:43:50 PM PDT 24 |
39363059 ps |
| T978 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4159394586 |
|
|
Aug 02 06:43:48 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
22958495 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.98449678 |
|
|
Aug 02 06:43:38 PM PDT 24 |
Aug 02 06:43:41 PM PDT 24 |
166593807 ps |
| T980 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2617246191 |
|
|
Aug 02 06:43:59 PM PDT 24 |
Aug 02 06:44:03 PM PDT 24 |
241021924 ps |
| T981 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1203172637 |
|
|
Aug 02 06:43:58 PM PDT 24 |
Aug 02 06:43:59 PM PDT 24 |
136890829 ps |
| T982 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2009602051 |
|
|
Aug 02 06:43:39 PM PDT 24 |
Aug 02 06:43:41 PM PDT 24 |
226303789 ps |
| T119 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2956556528 |
|
|
Aug 02 06:43:55 PM PDT 24 |
Aug 02 06:43:57 PM PDT 24 |
318593474 ps |
| T983 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1089027798 |
|
|
Aug 02 06:43:36 PM PDT 24 |
Aug 02 06:43:39 PM PDT 24 |
400222759 ps |
| T984 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.541449497 |
|
|
Aug 02 06:43:45 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
521004184 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3536500531 |
|
|
Aug 02 06:43:46 PM PDT 24 |
Aug 02 06:43:47 PM PDT 24 |
350760314 ps |
| T986 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3350447860 |
|
|
Aug 02 06:43:50 PM PDT 24 |
Aug 02 06:43:53 PM PDT 24 |
376946501 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.996899417 |
|
|
Aug 02 06:43:38 PM PDT 24 |
Aug 02 06:43:39 PM PDT 24 |
43519636 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3299628322 |
|
|
Aug 02 06:43:42 PM PDT 24 |
Aug 02 06:43:43 PM PDT 24 |
562040810 ps |
| T989 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3701701856 |
|
|
Aug 02 06:43:36 PM PDT 24 |
Aug 02 06:43:37 PM PDT 24 |
31088519 ps |
| T990 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1802764412 |
|
|
Aug 02 06:43:59 PM PDT 24 |
Aug 02 06:44:02 PM PDT 24 |
80945220 ps |
| T991 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2977752841 |
|
|
Aug 02 06:43:49 PM PDT 24 |
Aug 02 06:43:52 PM PDT 24 |
1597609651 ps |
| T992 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.588711326 |
|
|
Aug 02 06:44:02 PM PDT 24 |
Aug 02 06:44:02 PM PDT 24 |
41052491 ps |
| T993 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2411909057 |
|
|
Aug 02 06:43:51 PM PDT 24 |
Aug 02 06:43:52 PM PDT 24 |
21795057 ps |
| T994 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.514141346 |
|
|
Aug 02 06:43:43 PM PDT 24 |
Aug 02 06:43:44 PM PDT 24 |
20032777 ps |
| T995 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1688929638 |
|
|
Aug 02 06:44:00 PM PDT 24 |
Aug 02 06:44:01 PM PDT 24 |
21720519 ps |
| T996 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2152140483 |
|
|
Aug 02 06:43:47 PM PDT 24 |
Aug 02 06:43:48 PM PDT 24 |
13391918 ps |
| T997 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3482153676 |
|
|
Aug 02 06:43:57 PM PDT 24 |
Aug 02 06:43:58 PM PDT 24 |
34156622 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.355267215 |
|
|
Aug 02 06:43:45 PM PDT 24 |
Aug 02 06:43:48 PM PDT 24 |
207778601 ps |
| T91 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2855202130 |
|
|
Aug 02 06:43:48 PM PDT 24 |
Aug 02 06:43:49 PM PDT 24 |
19662352 ps |
| T999 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3047077849 |
|
|
Aug 02 06:43:56 PM PDT 24 |
Aug 02 06:43:59 PM PDT 24 |
29465421 ps |
| T118 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3784464131 |
|
|
Aug 02 06:43:38 PM PDT 24 |
Aug 02 06:43:40 PM PDT 24 |
652072766 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.496051891 |
|
|
Aug 02 06:43:38 PM PDT 24 |
Aug 02 06:43:40 PM PDT 24 |
488634271 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3681670778 |
|
|
Aug 02 06:44:02 PM PDT 24 |
Aug 02 06:44:03 PM PDT 24 |
178834820 ps |
| T1002 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1925871808 |
|
|
Aug 02 06:43:50 PM PDT 24 |
Aug 02 06:43:50 PM PDT 24 |
16677608 ps |