Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147629398	1			T1	82642		T2	456258		T3	2016
instr_valid_dis	115957360	1			T2	456258		T3	2016		T4	316030
instr_en	20717973	1			T12	18508		T26	164720		T45	62496

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11960167	1			T4	103476		T12	18452		T26	101268
sram_ifetch_valid_disable	113387397	1			T1	60766		T2	456258		T3	2016
sram_ifetch_enable	22281834	1			T1	21876		T4	171796		T10	2986

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147629398	1			T1	82642		T2	456258		T3	2016
hw_debug_en_valid_off	113085669	1			T1	30696		T2	456258		T3	2016
hw_debug_en_on	23140045	1			T1	31674		T4	90530		T10	2986

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113387397	1			T1	60766		T2	456258		T3	2016
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100437784	1			T2	456258		T3	2016		T4	40758
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8271534	1			T26	28424		T45	14958		T146	90924
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4709160	1			T4	55474		T26	16828		T45	44668
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2281730	1			T4	55474		T26	820		T45	15218
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1550578	1			T26	16008		T45	29450		T20	54
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4674778	1			T4	32998		T12	18452		T26	84440
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2047122	1			T4	32998		T26	48490		T19	41816
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1942108	1			T12	18452		T26	35950		T65	114312
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9601657	1			T1	30144		T4	40758		T12	14776
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4007651	1			T4	40758		T12	14776		T26	57338
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3393620	1			T146	38068		T65	78870		T8	33204

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8104298	1			T12	56		T26	84338		T19	18188
lc_exec_en	8863610	1			T1	1530		T4	16774		T10	2986
valid_exec_dis	109852475	1			T1	30622		T2	456258		T3	2016
invalid_exec_dis	34242001	1			T1	21876		T4	275272		T10	2986