Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1027
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.88 82.88 95.51 95.51 81.64 81.64 92.16 92.16 61.90 61.90 85.99 85.99 94.40 94.40 68.56 68.56 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3999861973
88.84 5.96 97.20 1.69 82.58 0.95 92.16 0.00 90.48 28.57 89.37 3.38 94.40 0.00 75.69 7.13 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3176260012
92.61 3.77 98.47 1.27 86.97 4.38 95.49 3.33 100.00 9.52 93.48 4.11 95.28 0.88 78.61 2.93 /workspace/coverage/default/48.sram_ctrl_lc_escalation.3202371595
93.71 1.09 98.47 0.00 87.09 0.12 97.36 1.87 100.00 0.00 93.48 0.00 95.28 0.00 84.28 5.67 /workspace/coverage/default/11.sram_ctrl_stress_all.712632928
94.73 1.03 98.64 0.17 87.68 0.59 97.57 0.21 100.00 0.00 94.20 0.72 95.28 0.00 89.76 5.48 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.758080300
95.48 0.75 98.90 0.25 88.15 0.47 97.57 0.00 100.00 0.00 94.93 0.72 95.58 0.29 93.24 3.47 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1418715702
96.06 0.58 99.07 0.17 89.93 1.78 97.99 0.42 100.00 0.00 95.65 0.72 96.17 0.59 93.60 0.37 /workspace/coverage/default/0.sram_ctrl_sec_cm.1098460319
96.31 0.25 99.07 0.00 90.05 0.12 98.34 0.35 100.00 0.00 95.65 0.00 96.17 0.00 94.88 1.28 /workspace/coverage/default/10.sram_ctrl_stress_all.1205785139
96.54 0.23 99.07 0.00 90.28 0.24 98.40 0.07 100.00 0.00 95.65 0.00 97.49 1.33 94.88 0.00 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2380561406
96.76 0.21 99.07 0.00 90.64 0.36 98.82 0.42 100.00 0.00 95.65 0.00 97.49 0.00 95.61 0.73 /workspace/coverage/default/13.sram_ctrl_alert_test.2857374840
96.95 0.19 99.07 0.00 90.76 0.12 98.82 0.00 100.00 0.00 96.14 0.48 98.23 0.74 95.61 0.00 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3676159949
97.11 0.16 99.07 0.00 90.76 0.00 98.89 0.07 100.00 0.00 96.14 0.00 99.12 0.88 95.80 0.18 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3488749154
97.24 0.13 99.15 0.08 90.76 0.00 99.72 0.83 100.00 0.00 96.14 0.00 99.12 0.00 95.80 0.00 /workspace/coverage/default/0.sram_ctrl_ram_cfg.176997862
97.33 0.09 99.15 0.00 91.00 0.24 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.16 0.37 /workspace/coverage/default/41.sram_ctrl_stress_all.1842546239
97.38 0.05 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.53 0.37 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1724586630
97.43 0.05 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.89 0.37 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.547524639
97.48 0.05 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.26 0.37 /workspace/coverage/default/2.sram_ctrl_executable.2894958709
97.51 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.18 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4096169358

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.853389677
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3334617301
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3774913923
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1064016233
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2795186081
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2407574219
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3530016436
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2345315582
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1708324070
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.267150105
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.855720608
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2816007589
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1516353538
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3850277758
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.638901173
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1334268628
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.226649872
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3416549465
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1711288274
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.284451636
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.187445528
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2505438467
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.180935312
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.372399183
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.350006072
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.243165629
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3421432995
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3197033560
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.486020966
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.598650710
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3648249922
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2618593566
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2425552082
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.402737026
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2473335810
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2741105076
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.637343602
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3006376566
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2668041485
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3787326254
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2424478716
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1493893145
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.443688722
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.136858800
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1719488114
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3782807990
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1502987320
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.464804062
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4104925223
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.431169564
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1322615444
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1283019066
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2919886766
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3725705885
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2543975727
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4076166731
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.504270731
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1760077538
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2729661121
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2237654069
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4284491844
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.18632242
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3728410463
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.821082284
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1346369316
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2278642956
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4136215323
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.665755388
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.779334460
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3735218234
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1831219278
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3330488626
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.900071583
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1621089798
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.407657336
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1243775071
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2325847052
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2192523339
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.437723196
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3805598818
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3524061012
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.976112568
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3793359972
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.586173663
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1135040745
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.873419378
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2290570701
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1405671605
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3721786703
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2564580959
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1840631906
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3146524942
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3320954647
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.537486786
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3923072254
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.72899428
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1185614256
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1382809399
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.852991482
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2287208576
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2456646937
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.691587527
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3142071900
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3021035977
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3831681741
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2947996515
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.861689557
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2455215869
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4262943532
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2047521460
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1170999185
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1963036941
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2900276408
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.486111322
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3513450683
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2097389328
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2827034586
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3904469762
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3851028279
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1707147418
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2777492339
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2373921690
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.257831601
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4158957679
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2725834187
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.914912243
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3227799908
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.42750462
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3135374941
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1686587302
/workspace/coverage/default/0.sram_ctrl_alert_test.1940017051
/workspace/coverage/default/0.sram_ctrl_bijection.1830807636
/workspace/coverage/default/0.sram_ctrl_executable.1109693620
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2815306106
/workspace/coverage/default/0.sram_ctrl_max_throughput.3593501586
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1308999838
/workspace/coverage/default/0.sram_ctrl_mem_walk.3622276279
/workspace/coverage/default/0.sram_ctrl_multiple_keys.4262315469
/workspace/coverage/default/0.sram_ctrl_partial_access.1367531194
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2040109257
/workspace/coverage/default/0.sram_ctrl_regwen.1049822610
/workspace/coverage/default/0.sram_ctrl_smoke.2226537064
/workspace/coverage/default/0.sram_ctrl_stress_all.3079110965
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.949732852
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2573631750
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.441435577
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3378162682
/workspace/coverage/default/1.sram_ctrl_alert_test.1213534046
/workspace/coverage/default/1.sram_ctrl_bijection.4071491084
/workspace/coverage/default/1.sram_ctrl_executable.3719317091
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2361442548
/workspace/coverage/default/1.sram_ctrl_max_throughput.1029384216
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2792910312
/workspace/coverage/default/1.sram_ctrl_mem_walk.3182162903
/workspace/coverage/default/1.sram_ctrl_multiple_keys.927994520
/workspace/coverage/default/1.sram_ctrl_partial_access.647467255
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.498401015
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2671666595
/workspace/coverage/default/1.sram_ctrl_regwen.3644618381
/workspace/coverage/default/1.sram_ctrl_sec_cm.1394973870
/workspace/coverage/default/1.sram_ctrl_smoke.2483397460
/workspace/coverage/default/1.sram_ctrl_stress_all.2102157756
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3634009724
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2238270775
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2393905199
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.4170394202
/workspace/coverage/default/10.sram_ctrl_alert_test.3007953526
/workspace/coverage/default/10.sram_ctrl_bijection.165180956
/workspace/coverage/default/10.sram_ctrl_executable.510207018
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2963500517
/workspace/coverage/default/10.sram_ctrl_max_throughput.4050934974
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3660206151
/workspace/coverage/default/10.sram_ctrl_mem_walk.3059684766
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1675330621
/workspace/coverage/default/10.sram_ctrl_partial_access.764568930
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1515260160
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3008317761
/workspace/coverage/default/10.sram_ctrl_regwen.2845855221
/workspace/coverage/default/10.sram_ctrl_smoke.2747424767
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3114619304
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1716472700
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.791370773
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2230891784
/workspace/coverage/default/11.sram_ctrl_alert_test.2483921699
/workspace/coverage/default/11.sram_ctrl_bijection.1396622410
/workspace/coverage/default/11.sram_ctrl_executable.125241275
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3428409731
/workspace/coverage/default/11.sram_ctrl_max_throughput.3878101122
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1855345273
/workspace/coverage/default/11.sram_ctrl_mem_walk.406906081
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3545899273
/workspace/coverage/default/11.sram_ctrl_partial_access.638777809
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.228496514
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2342325086
/workspace/coverage/default/11.sram_ctrl_regwen.3351698447
/workspace/coverage/default/11.sram_ctrl_smoke.4136227818
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.66255714
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3495888183
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1911421422
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.543477355
/workspace/coverage/default/12.sram_ctrl_alert_test.1824115822
/workspace/coverage/default/12.sram_ctrl_bijection.2305754001
/workspace/coverage/default/12.sram_ctrl_executable.62834900
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3481237337
/workspace/coverage/default/12.sram_ctrl_max_throughput.2479027722
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2590156049
/workspace/coverage/default/12.sram_ctrl_mem_walk.3064355062
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2142126605
/workspace/coverage/default/12.sram_ctrl_partial_access.3353490467
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/workspace/coverage/default/43.sram_ctrl_mem_walk.1786759520
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1539129752
/workspace/coverage/default/43.sram_ctrl_partial_access.3593447719
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3739527534
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3886051122
/workspace/coverage/default/43.sram_ctrl_regwen.3979460472
/workspace/coverage/default/43.sram_ctrl_smoke.2421014492
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3710212613
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1972273261
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1341942996
/workspace/coverage/default/44.sram_ctrl_alert_test.516400888
/workspace/coverage/default/44.sram_ctrl_bijection.2193287662
/workspace/coverage/default/44.sram_ctrl_executable.494020438
/workspace/coverage/default/44.sram_ctrl_lc_escalation.142007184
/workspace/coverage/default/44.sram_ctrl_max_throughput.1996719196
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.991750549
/workspace/coverage/default/44.sram_ctrl_mem_walk.3815362018
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2130163631
/workspace/coverage/default/44.sram_ctrl_partial_access.56755695
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.4198117668
/workspace/coverage/default/44.sram_ctrl_ram_cfg.349809980
/workspace/coverage/default/44.sram_ctrl_regwen.3851641313
/workspace/coverage/default/44.sram_ctrl_smoke.3418146458
/workspace/coverage/default/44.sram_ctrl_stress_all.2086613476
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3744511508
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.777113986
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4006820333
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1814469586
/workspace/coverage/default/45.sram_ctrl_alert_test.3557751782
/workspace/coverage/default/45.sram_ctrl_bijection.2451562088
/workspace/coverage/default/45.sram_ctrl_executable.1843393339
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1847538338
/workspace/coverage/default/45.sram_ctrl_max_throughput.2385223959
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.93354763
/workspace/coverage/default/45.sram_ctrl_mem_walk.4250402806
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2375592224
/workspace/coverage/default/45.sram_ctrl_partial_access.145222591
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.4059548956
/workspace/coverage/default/45.sram_ctrl_ram_cfg.543949360
/workspace/coverage/default/45.sram_ctrl_regwen.2483767048
/workspace/coverage/default/45.sram_ctrl_smoke.2090485703
/workspace/coverage/default/45.sram_ctrl_stress_all.3572834579
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1900689435
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1620728578
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2938065335
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2660259203
/workspace/coverage/default/46.sram_ctrl_alert_test.3928152951
/workspace/coverage/default/46.sram_ctrl_bijection.162545098
/workspace/coverage/default/46.sram_ctrl_executable.881829306
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3603050245
/workspace/coverage/default/46.sram_ctrl_max_throughput.1554679269
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.4151742055
/workspace/coverage/default/46.sram_ctrl_mem_walk.1978042536
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1467232339
/workspace/coverage/default/46.sram_ctrl_partial_access.3038464535
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4179396951
/workspace/coverage/default/46.sram_ctrl_ram_cfg.494793263
/workspace/coverage/default/46.sram_ctrl_regwen.1932934246
/workspace/coverage/default/46.sram_ctrl_smoke.526463713
/workspace/coverage/default/46.sram_ctrl_stress_all.1426489426
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1634394170
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2448959560
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2614946735
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.649978896
/workspace/coverage/default/47.sram_ctrl_alert_test.268384348
/workspace/coverage/default/47.sram_ctrl_bijection.1362190888
/workspace/coverage/default/47.sram_ctrl_executable.3929979641
/workspace/coverage/default/47.sram_ctrl_lc_escalation.457200934
/workspace/coverage/default/47.sram_ctrl_max_throughput.3410459801
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3657477676
/workspace/coverage/default/47.sram_ctrl_mem_walk.1573592573
/workspace/coverage/default/47.sram_ctrl_multiple_keys.711561789
/workspace/coverage/default/47.sram_ctrl_partial_access.3125457731
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.194327221
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2598859954
/workspace/coverage/default/47.sram_ctrl_regwen.1804470254
/workspace/coverage/default/47.sram_ctrl_smoke.2128256746
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2211381636
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.983163695
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2137626043
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.4173890083
/workspace/coverage/default/48.sram_ctrl_alert_test.2536441341
/workspace/coverage/default/48.sram_ctrl_bijection.3714970752
/workspace/coverage/default/48.sram_ctrl_executable.3369322975
/workspace/coverage/default/48.sram_ctrl_max_throughput.4270208789
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2613830009
/workspace/coverage/default/48.sram_ctrl_mem_walk.1269676829
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3951682862
/workspace/coverage/default/48.sram_ctrl_partial_access.1411156495
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3884348710
/workspace/coverage/default/48.sram_ctrl_ram_cfg.215741729
/workspace/coverage/default/48.sram_ctrl_regwen.1069942484
/workspace/coverage/default/48.sram_ctrl_smoke.1369765958
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.209764150
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2447744190
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3955509562
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2295275665
/workspace/coverage/default/49.sram_ctrl_alert_test.585169161
/workspace/coverage/default/49.sram_ctrl_bijection.1891654004
/workspace/coverage/default/49.sram_ctrl_executable.115527355
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2944841975
/workspace/coverage/default/49.sram_ctrl_max_throughput.2234959101
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2152657758
/workspace/coverage/default/49.sram_ctrl_mem_walk.3757700774
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3237621222
/workspace/coverage/default/49.sram_ctrl_partial_access.4233216630
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1676902524
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4036113069
/workspace/coverage/default/49.sram_ctrl_regwen.351109104
/workspace/coverage/default/49.sram_ctrl_smoke.56809760
/workspace/coverage/default/49.sram_ctrl_stress_all.2076079125
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3218191695
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3778128938
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2494435962
/workspace/coverage/default/5.sram_ctrl_alert_test.769869558
/workspace/coverage/default/5.sram_ctrl_bijection.2443608141
/workspace/coverage/default/5.sram_ctrl_executable.3579696469
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2948977522
/workspace/coverage/default/5.sram_ctrl_max_throughput.2278335913
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.313439145
/workspace/coverage/default/5.sram_ctrl_mem_walk.3575906861
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2255748113
/workspace/coverage/default/5.sram_ctrl_partial_access.544004545
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4097494775
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1010912500
/workspace/coverage/default/5.sram_ctrl_regwen.2963624257
/workspace/coverage/default/5.sram_ctrl_smoke.3691779040
/workspace/coverage/default/5.sram_ctrl_stress_all.2773438293
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2276879094
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3430032047
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3608063096
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3842548300
/workspace/coverage/default/6.sram_ctrl_alert_test.4159919791
/workspace/coverage/default/6.sram_ctrl_bijection.3636815202
/workspace/coverage/default/6.sram_ctrl_executable.409888802
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2468609846
/workspace/coverage/default/6.sram_ctrl_max_throughput.3482841027
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1612718997
/workspace/coverage/default/6.sram_ctrl_mem_walk.2027642879
/workspace/coverage/default/6.sram_ctrl_multiple_keys.919528638
/workspace/coverage/default/6.sram_ctrl_partial_access.3052153012
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2144270660
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1561427348
/workspace/coverage/default/6.sram_ctrl_regwen.4008489475
/workspace/coverage/default/6.sram_ctrl_smoke.3332522035
/workspace/coverage/default/6.sram_ctrl_stress_all.2924852125
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1843565712
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3873783080
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2237752609
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.100738181
/workspace/coverage/default/7.sram_ctrl_alert_test.4284945307
/workspace/coverage/default/7.sram_ctrl_bijection.4259336320
/workspace/coverage/default/7.sram_ctrl_executable.3833418315
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3020885003
/workspace/coverage/default/7.sram_ctrl_max_throughput.1583979715
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.4091662734
/workspace/coverage/default/7.sram_ctrl_mem_walk.3672755706
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1298086119
/workspace/coverage/default/7.sram_ctrl_partial_access.2349005942
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3316308630
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1783192101
/workspace/coverage/default/7.sram_ctrl_regwen.584539374
/workspace/coverage/default/7.sram_ctrl_smoke.950306606
/workspace/coverage/default/7.sram_ctrl_stress_all.1377781608
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3566497546
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1662690714
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.919929126
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3956785102
/workspace/coverage/default/8.sram_ctrl_alert_test.3409862480
/workspace/coverage/default/8.sram_ctrl_bijection.2198276789
/workspace/coverage/default/8.sram_ctrl_executable.3266614389
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3452073022
/workspace/coverage/default/8.sram_ctrl_max_throughput.2922944805
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3147225893
/workspace/coverage/default/8.sram_ctrl_mem_walk.1153362417
/workspace/coverage/default/8.sram_ctrl_multiple_keys.732088188
/workspace/coverage/default/8.sram_ctrl_partial_access.1448652084
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1440471958
/workspace/coverage/default/8.sram_ctrl_ram_cfg.853682776
/workspace/coverage/default/8.sram_ctrl_regwen.3254768173
/workspace/coverage/default/8.sram_ctrl_smoke.3224330861
/workspace/coverage/default/8.sram_ctrl_stress_all.3798997248
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3432151199
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1943730033
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2950277149
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3535833613
/workspace/coverage/default/9.sram_ctrl_alert_test.1529622259
/workspace/coverage/default/9.sram_ctrl_bijection.2703386889
/workspace/coverage/default/9.sram_ctrl_executable.2108380896
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1339280898
/workspace/coverage/default/9.sram_ctrl_max_throughput.2897956592
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1465840839
/workspace/coverage/default/9.sram_ctrl_mem_walk.2142488588
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3131412319
/workspace/coverage/default/9.sram_ctrl_partial_access.2475183846
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3945071066
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3281701977
/workspace/coverage/default/9.sram_ctrl_regwen.4086385678
/workspace/coverage/default/9.sram_ctrl_smoke.4185387111
/workspace/coverage/default/9.sram_ctrl_stress_all.2318801178
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3644755897
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1760980974
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3921192087



Total test records in report: 1027
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/32.sram_ctrl_regwen.2174635922 Aug 03 06:00:45 PM PDT 24 Aug 03 06:05:12 PM PDT 24 644844934 ps
T2 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2447744190 Aug 03 06:05:11 PM PDT 24 Aug 03 06:09:30 PM PDT 24 3165814180 ps
T3 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3488749154 Aug 03 06:00:27 PM PDT 24 Aug 03 06:00:30 PM PDT 24 344786174 ps
T4 /workspace/coverage/default/45.sram_ctrl_regwen.2483767048 Aug 03 06:04:33 PM PDT 24 Aug 03 06:16:12 PM PDT 24 12968576138 ps
T9 /workspace/coverage/default/32.sram_ctrl_max_throughput.629706109 Aug 03 06:00:41 PM PDT 24 Aug 03 06:01:36 PM PDT 24 377605067 ps
T10 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3999861973 Aug 03 06:01:09 PM PDT 24 Aug 03 06:01:25 PM PDT 24 373505400 ps
T5 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3884348710 Aug 03 06:05:11 PM PDT 24 Aug 03 06:12:36 PM PDT 24 67231714159 ps
T11 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.777113986 Aug 03 06:04:12 PM PDT 24 Aug 03 06:07:36 PM PDT 24 4202958702 ps
T6 /workspace/coverage/default/48.sram_ctrl_lc_escalation.3202371595 Aug 03 06:05:18 PM PDT 24 Aug 03 06:05:24 PM PDT 24 2063111232 ps
T12 /workspace/coverage/default/27.sram_ctrl_regwen.3128882619 Aug 03 05:59:13 PM PDT 24 Aug 03 06:02:19 PM PDT 24 1066298811 ps
T26 /workspace/coverage/default/19.sram_ctrl_executable.1548101697 Aug 03 05:56:22 PM PDT 24 Aug 03 06:10:58 PM PDT 24 17790212981 ps
T42 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1218222609 Aug 03 05:53:16 PM PDT 24 Aug 03 06:21:54 PM PDT 24 9366253421 ps
T41 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1418715702 Aug 03 05:59:09 PM PDT 24 Aug 03 06:03:07 PM PDT 24 11434759893 ps
T56 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1308999838 Aug 03 05:53:10 PM PDT 24 Aug 03 05:53:16 PM PDT 24 1832570266 ps
T57 /workspace/coverage/default/12.sram_ctrl_max_throughput.2479027722 Aug 03 05:54:25 PM PDT 24 Aug 03 05:54:26 PM PDT 24 44285971 ps
T45 /workspace/coverage/default/37.sram_ctrl_executable.4130058144 Aug 03 06:02:27 PM PDT 24 Aug 03 06:11:11 PM PDT 24 5643186853 ps
T46 /workspace/coverage/default/39.sram_ctrl_mem_walk.1838452459 Aug 03 06:03:03 PM PDT 24 Aug 03 06:03:14 PM PDT 24 900092550 ps
T98 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.983163695 Aug 03 06:05:00 PM PDT 24 Aug 03 06:08:18 PM PDT 24 7945704438 ps
T19 /workspace/coverage/default/11.sram_ctrl_stress_all.712632928 Aug 03 05:54:20 PM PDT 24 Aug 03 06:46:39 PM PDT 24 14018873337 ps
T149 /workspace/coverage/default/9.sram_ctrl_max_throughput.2897956592 Aug 03 05:53:59 PM PDT 24 Aug 03 05:54:13 PM PDT 24 252521774 ps
T148 /workspace/coverage/default/32.sram_ctrl_multiple_keys.311565551 Aug 03 06:00:34 PM PDT 24 Aug 03 06:12:09 PM PDT 24 3050265328 ps
T151 /workspace/coverage/default/21.sram_ctrl_partial_access.586275940 Aug 03 05:56:52 PM PDT 24 Aug 03 05:57:11 PM PDT 24 924460492 ps
T20 /workspace/coverage/default/14.sram_ctrl_regwen.4106303711 Aug 03 05:55:00 PM PDT 24 Aug 03 06:13:08 PM PDT 24 13534961274 ps
T64 /workspace/coverage/default/3.sram_ctrl_mem_walk.4066896474 Aug 03 05:53:23 PM PDT 24 Aug 03 05:53:27 PM PDT 24 76601343 ps
T146 /workspace/coverage/default/44.sram_ctrl_executable.494020438 Aug 03 06:04:23 PM PDT 24 Aug 03 06:06:50 PM PDT 24 4091330233 ps
T43 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.4060031976 Aug 03 05:56:18 PM PDT 24 Aug 03 06:14:35 PM PDT 24 6947461812 ps
T153 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1296586616 Aug 03 06:00:26 PM PDT 24 Aug 03 06:00:39 PM PDT 24 83652178 ps
T13 /workspace/coverage/default/20.sram_ctrl_alert_test.1767236709 Aug 03 05:56:41 PM PDT 24 Aug 03 05:56:42 PM PDT 24 128891218 ps
T152 /workspace/coverage/default/14.sram_ctrl_bijection.3622350331 Aug 03 05:54:58 PM PDT 24 Aug 03 05:55:29 PM PDT 24 2010356923 ps
T47 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1465840839 Aug 03 05:53:59 PM PDT 24 Aug 03 05:54:05 PM PDT 24 349637229 ps
T99 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3061739904 Aug 03 05:57:33 PM PDT 24 Aug 03 06:02:12 PM PDT 24 136278140909 ps
T100 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.666285726 Aug 03 06:03:13 PM PDT 24 Aug 03 06:07:59 PM PDT 24 11069297435 ps
T101 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.4059548956 Aug 03 06:04:34 PM PDT 24 Aug 03 06:10:20 PM PDT 24 45233588909 ps
T65 /workspace/coverage/default/6.sram_ctrl_regwen.4008489475 Aug 03 05:53:32 PM PDT 24 Aug 03 06:23:29 PM PDT 24 27889973630 ps
T24 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1634394170 Aug 03 06:04:54 PM PDT 24 Aug 03 06:05:13 PM PDT 24 651520044 ps
T122 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2365355282 Aug 03 06:02:55 PM PDT 24 Aug 03 06:03:38 PM PDT 24 375563616 ps
T123 /workspace/coverage/default/3.sram_ctrl_bijection.2498547760 Aug 03 05:53:24 PM PDT 24 Aug 03 05:54:29 PM PDT 24 16920346643 ps
T7 /workspace/coverage/default/19.sram_ctrl_lc_escalation.2933197758 Aug 03 05:56:19 PM PDT 24 Aug 03 05:56:25 PM PDT 24 1271489204 ps
T25 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1702403684 Aug 03 05:58:33 PM PDT 24 Aug 03 05:59:05 PM PDT 24 1050659866 ps
T8 /workspace/coverage/default/34.sram_ctrl_stress_all.469434170 Aug 03 06:01:31 PM PDT 24 Aug 03 06:42:54 PM PDT 24 8623980539 ps
T124 /workspace/coverage/default/49.sram_ctrl_bijection.1891654004 Aug 03 06:05:33 PM PDT 24 Aug 03 06:06:57 PM PDT 24 6778568479 ps
T21 /workspace/coverage/default/23.sram_ctrl_lc_escalation.2059997724 Aug 03 05:57:40 PM PDT 24 Aug 03 05:57:47 PM PDT 24 1672781710 ps
T125 /workspace/coverage/default/43.sram_ctrl_partial_access.3593447719 Aug 03 06:04:00 PM PDT 24 Aug 03 06:05:03 PM PDT 24 7267463984 ps
T14 /workspace/coverage/default/47.sram_ctrl_alert_test.268384348 Aug 03 06:05:13 PM PDT 24 Aug 03 06:05:14 PM PDT 24 35465482 ps
T102 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3782847003 Aug 03 05:58:42 PM PDT 24 Aug 03 06:02:27 PM PDT 24 2328436949 ps
T53 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3175568803 Aug 03 05:57:46 PM PDT 24 Aug 03 05:57:51 PM PDT 24 326517640 ps
T54 /workspace/coverage/default/31.sram_ctrl_mem_walk.3915697607 Aug 03 06:00:28 PM PDT 24 Aug 03 06:00:33 PM PDT 24 93898100 ps
T155 /workspace/coverage/default/48.sram_ctrl_smoke.1369765958 Aug 03 06:05:13 PM PDT 24 Aug 03 06:05:31 PM PDT 24 4291849833 ps
T147 /workspace/coverage/default/29.sram_ctrl_lc_escalation.3676375833 Aug 03 05:59:47 PM PDT 24 Aug 03 05:59:52 PM PDT 24 2747365281 ps
T15 /workspace/coverage/default/41.sram_ctrl_alert_test.306552465 Aug 03 06:03:41 PM PDT 24 Aug 03 06:03:42 PM PDT 24 18898721 ps
T156 /workspace/coverage/default/38.sram_ctrl_regwen.3803461244 Aug 03 06:02:53 PM PDT 24 Aug 03 06:04:39 PM PDT 24 2516611812 ps
T150 /workspace/coverage/default/42.sram_ctrl_alert_test.1056054010 Aug 03 06:03:56 PM PDT 24 Aug 03 06:03:57 PM PDT 24 38227764 ps
T154 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.225195036 Aug 03 06:01:15 PM PDT 24 Aug 03 06:08:26 PM PDT 24 15710330194 ps
T140 /workspace/coverage/default/40.sram_ctrl_stress_all.2823401919 Aug 03 06:03:29 PM PDT 24 Aug 03 06:51:00 PM PDT 24 49883202965 ps
T141 /workspace/coverage/default/2.sram_ctrl_executable.2894958709 Aug 03 05:53:19 PM PDT 24 Aug 03 06:02:37 PM PDT 24 27042371489 ps
T157 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2129224065 Aug 03 06:02:25 PM PDT 24 Aug 03 06:02:41 PM PDT 24 73141204 ps
T51 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3176260012 Aug 03 06:01:28 PM PDT 24 Aug 03 06:04:27 PM PDT 24 2412098603 ps
T83 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1065422563 Aug 03 06:03:36 PM PDT 24 Aug 03 06:03:41 PM PDT 24 641187418 ps
T158 /workspace/coverage/default/47.sram_ctrl_max_throughput.3410459801 Aug 03 06:04:59 PM PDT 24 Aug 03 06:06:26 PM PDT 24 246025668 ps
T159 /workspace/coverage/default/13.sram_ctrl_alert_test.2857374840 Aug 03 05:54:52 PM PDT 24 Aug 03 05:54:53 PM PDT 24 40999640 ps
T84 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.991750549 Aug 03 06:04:26 PM PDT 24 Aug 03 06:04:30 PM PDT 24 88084625 ps
T27 /workspace/coverage/default/34.sram_ctrl_ram_cfg.53673877 Aug 03 06:01:30 PM PDT 24 Aug 03 06:01:31 PM PDT 24 128993074 ps
T22 /workspace/coverage/default/10.sram_ctrl_lc_escalation.2963500517 Aug 03 05:54:07 PM PDT 24 Aug 03 05:54:10 PM PDT 24 173516228 ps
T160 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1448211456 Aug 03 06:00:45 PM PDT 24 Aug 03 06:00:51 PM PDT 24 169726166 ps
T161 /workspace/coverage/default/27.sram_ctrl_executable.3900722701 Aug 03 05:59:14 PM PDT 24 Aug 03 06:09:06 PM PDT 24 8656244375 ps
T162 /workspace/coverage/default/12.sram_ctrl_partial_access.3353490467 Aug 03 05:54:24 PM PDT 24 Aug 03 05:54:28 PM PDT 24 786416620 ps
T163 /workspace/coverage/default/0.sram_ctrl_partial_access.1367531194 Aug 03 05:53:06 PM PDT 24 Aug 03 05:53:17 PM PDT 24 3609032531 ps
T164 /workspace/coverage/default/14.sram_ctrl_multiple_keys.515893318 Aug 03 05:54:58 PM PDT 24 Aug 03 06:02:01 PM PDT 24 5959103275 ps
T165 /workspace/coverage/default/40.sram_ctrl_multiple_keys.1143579364 Aug 03 06:03:08 PM PDT 24 Aug 03 06:07:09 PM PDT 24 5835692777 ps
T166 /workspace/coverage/default/43.sram_ctrl_bijection.1072980997 Aug 03 06:04:01 PM PDT 24 Aug 03 06:04:18 PM PDT 24 1456378793 ps
T167 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3976830991 Aug 03 05:53:22 PM PDT 24 Aug 03 06:00:00 PM PDT 24 15273079634 ps
T168 /workspace/coverage/default/26.sram_ctrl_executable.1253336192 Aug 03 05:58:48 PM PDT 24 Aug 03 06:25:34 PM PDT 24 31228340480 ps
T169 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3921192087 Aug 03 05:53:59 PM PDT 24 Aug 03 05:56:44 PM PDT 24 2433625419 ps
T170 /workspace/coverage/default/5.sram_ctrl_bijection.2443608141 Aug 03 05:53:28 PM PDT 24 Aug 03 05:54:10 PM PDT 24 6969855966 ps
T23 /workspace/coverage/default/10.sram_ctrl_stress_all.1205785139 Aug 03 05:54:14 PM PDT 24 Aug 03 06:34:28 PM PDT 24 171841031348 ps
T55 /workspace/coverage/default/33.sram_ctrl_mem_walk.3767805385 Aug 03 06:01:11 PM PDT 24 Aug 03 06:01:16 PM PDT 24 914767988 ps
T85 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2868274576 Aug 03 06:01:50 PM PDT 24 Aug 03 06:01:55 PM PDT 24 96771491 ps
T171 /workspace/coverage/default/9.sram_ctrl_partial_access.2475183846 Aug 03 05:53:55 PM PDT 24 Aug 03 05:54:10 PM PDT 24 911492832 ps
T52 /workspace/coverage/default/12.sram_ctrl_mem_walk.3064355062 Aug 03 05:54:29 PM PDT 24 Aug 03 05:54:41 PM PDT 24 663690871 ps
T172 /workspace/coverage/default/16.sram_ctrl_bijection.3453176951 Aug 03 05:55:29 PM PDT 24 Aug 03 05:56:54 PM PDT 24 7097326352 ps
T86 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2888901206 Aug 03 06:03:22 PM PDT 24 Aug 03 06:03:28 PM PDT 24 160127737 ps
T173 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3316370886 Aug 03 05:56:51 PM PDT 24 Aug 03 06:02:15 PM PDT 24 12660674341 ps
T28 /workspace/coverage/default/32.sram_ctrl_ram_cfg.988292253 Aug 03 06:00:47 PM PDT 24 Aug 03 06:00:47 PM PDT 24 149589699 ps
T174 /workspace/coverage/default/19.sram_ctrl_smoke.85592691 Aug 03 05:56:07 PM PDT 24 Aug 03 05:58:35 PM PDT 24 617710275 ps
T175 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.473020543 Aug 03 06:03:36 PM PDT 24 Aug 03 06:03:56 PM PDT 24 106741835 ps
T144 /workspace/coverage/default/40.sram_ctrl_executable.2540810423 Aug 03 06:03:14 PM PDT 24 Aug 03 06:21:15 PM PDT 24 27010322214 ps
T176 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.791370773 Aug 03 05:54:04 PM PDT 24 Aug 03 05:55:20 PM PDT 24 466332575 ps
T69 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1717814185 Aug 03 05:55:40 PM PDT 24 Aug 03 05:55:51 PM PDT 24 174448051 ps
T177 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1760980974 Aug 03 05:53:55 PM PDT 24 Aug 03 05:56:38 PM PDT 24 1846030100 ps
T145 /workspace/coverage/default/4.sram_ctrl_executable.609961971 Aug 03 05:53:27 PM PDT 24 Aug 03 06:02:55 PM PDT 24 33033445548 ps
T178 /workspace/coverage/default/33.sram_ctrl_max_throughput.2915064209 Aug 03 06:00:49 PM PDT 24 Aug 03 06:02:56 PM PDT 24 538222125 ps
T179 /workspace/coverage/default/21.sram_ctrl_stress_all.1596907839 Aug 03 05:57:11 PM PDT 24 Aug 03 06:38:39 PM PDT 24 33237545151 ps
T180 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3671226767 Aug 03 05:59:11 PM PDT 24 Aug 03 05:59:15 PM PDT 24 670390109 ps
T181 /workspace/coverage/default/16.sram_ctrl_partial_access.1922644956 Aug 03 05:55:30 PM PDT 24 Aug 03 05:56:55 PM PDT 24 2330531973 ps
T48 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3566497546 Aug 03 05:53:42 PM PDT 24 Aug 03 05:55:30 PM PDT 24 2110737881 ps
T182 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1946579646 Aug 03 05:55:24 PM PDT 24 Aug 03 05:55:27 PM PDT 24 272870575 ps
T183 /workspace/coverage/default/49.sram_ctrl_max_throughput.2234959101 Aug 03 06:05:31 PM PDT 24 Aug 03 06:05:47 PM PDT 24 164567754 ps
T184 /workspace/coverage/default/38.sram_ctrl_bijection.615194507 Aug 03 06:02:46 PM PDT 24 Aug 03 06:03:48 PM PDT 24 11666392158 ps
T185 /workspace/coverage/default/41.sram_ctrl_partial_access.3928106227 Aug 03 06:03:28 PM PDT 24 Aug 03 06:03:38 PM PDT 24 715134912 ps
T186 /workspace/coverage/default/29.sram_ctrl_multiple_keys.870208112 Aug 03 05:59:42 PM PDT 24 Aug 03 06:19:32 PM PDT 24 13840699740 ps
T187 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2989405114 Aug 03 05:56:18 PM PDT 24 Aug 03 05:56:40 PM PDT 24 468590450 ps
T188 /workspace/coverage/default/46.sram_ctrl_mem_walk.1978042536 Aug 03 06:04:53 PM PDT 24 Aug 03 06:05:04 PM PDT 24 922906363 ps
T189 /workspace/coverage/default/48.sram_ctrl_max_throughput.4270208789 Aug 03 06:05:16 PM PDT 24 Aug 03 06:05:22 PM PDT 24 64187812 ps
T190 /workspace/coverage/default/8.sram_ctrl_partial_access.1448652084 Aug 03 05:53:50 PM PDT 24 Aug 03 05:55:41 PM PDT 24 2492251094 ps
T191 /workspace/coverage/default/15.sram_ctrl_alert_test.242770451 Aug 03 05:55:25 PM PDT 24 Aug 03 05:55:26 PM PDT 24 57628612 ps
T192 /workspace/coverage/default/5.sram_ctrl_regwen.2963624257 Aug 03 05:53:30 PM PDT 24 Aug 03 06:06:04 PM PDT 24 31423944396 ps
T29 /workspace/coverage/default/48.sram_ctrl_ram_cfg.215741729 Aug 03 06:05:23 PM PDT 24 Aug 03 06:05:24 PM PDT 24 52891061 ps
T193 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2069225412 Aug 03 05:54:22 PM PDT 24 Aug 03 05:59:29 PM PDT 24 8801236447 ps
T194 /workspace/coverage/default/31.sram_ctrl_smoke.3568191843 Aug 03 06:00:12 PM PDT 24 Aug 03 06:00:17 PM PDT 24 146764925 ps
T195 /workspace/coverage/default/22.sram_ctrl_partial_access.2387408264 Aug 03 05:57:10 PM PDT 24 Aug 03 05:57:13 PM PDT 24 66294720 ps
T196 /workspace/coverage/default/45.sram_ctrl_smoke.2090485703 Aug 03 06:04:26 PM PDT 24 Aug 03 06:04:55 PM PDT 24 431459632 ps
T197 /workspace/coverage/default/13.sram_ctrl_ram_cfg.3482034091 Aug 03 05:54:51 PM PDT 24 Aug 03 05:54:52 PM PDT 24 74734679 ps
T198 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.179256026 Aug 03 05:54:55 PM PDT 24 Aug 03 05:59:28 PM PDT 24 2752287764 ps
T199 /workspace/coverage/default/45.sram_ctrl_stress_all.3572834579 Aug 03 06:04:33 PM PDT 24 Aug 03 06:59:46 PM PDT 24 36838537093 ps
T200 /workspace/coverage/default/42.sram_ctrl_mem_walk.3889817212 Aug 03 06:03:55 PM PDT 24 Aug 03 06:04:04 PM PDT 24 136345210 ps
T58 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2792910312 Aug 03 05:53:13 PM PDT 24 Aug 03 05:53:17 PM PDT 24 408695300 ps
T44 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1293985250 Aug 03 05:55:52 PM PDT 24 Aug 03 06:11:06 PM PDT 24 3003029035 ps
T70 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2276879094 Aug 03 05:53:33 PM PDT 24 Aug 03 05:53:49 PM PDT 24 787459219 ps
T201 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.4198117668 Aug 03 06:04:19 PM PDT 24 Aug 03 06:10:23 PM PDT 24 29825807005 ps
T202 /workspace/coverage/default/5.sram_ctrl_alert_test.769869558 Aug 03 05:53:32 PM PDT 24 Aug 03 05:53:33 PM PDT 24 43478975 ps
T203 /workspace/coverage/default/19.sram_ctrl_partial_access.1217869696 Aug 03 05:56:18 PM PDT 24 Aug 03 05:56:21 PM PDT 24 352088053 ps
T204 /workspace/coverage/default/49.sram_ctrl_alert_test.585169161 Aug 03 06:05:49 PM PDT 24 Aug 03 06:05:49 PM PDT 24 37635478 ps
T205 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3710212613 Aug 03 06:04:01 PM PDT 24 Aug 03 06:06:50 PM PDT 24 1762180909 ps
T206 /workspace/coverage/default/29.sram_ctrl_bijection.913340262 Aug 03 05:59:41 PM PDT 24 Aug 03 06:00:50 PM PDT 24 24356187218 ps
T207 /workspace/coverage/default/35.sram_ctrl_ram_cfg.315667597 Aug 03 06:01:54 PM PDT 24 Aug 03 06:01:55 PM PDT 24 45659443 ps
T208 /workspace/coverage/default/15.sram_ctrl_multiple_keys.2251705813 Aug 03 05:55:05 PM PDT 24 Aug 03 06:07:45 PM PDT 24 14478375934 ps
T209 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3823212827 Aug 03 05:53:24 PM PDT 24 Aug 03 05:53:27 PM PDT 24 52662542 ps
T210 /workspace/coverage/default/2.sram_ctrl_ram_cfg.1408814959 Aug 03 05:53:17 PM PDT 24 Aug 03 05:53:18 PM PDT 24 90300126 ps
T211 /workspace/coverage/default/7.sram_ctrl_smoke.950306606 Aug 03 05:53:32 PM PDT 24 Aug 03 05:53:46 PM PDT 24 2421389912 ps
T212 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1182565499 Aug 03 06:02:10 PM PDT 24 Aug 03 06:02:11 PM PDT 24 79643683 ps
T213 /workspace/coverage/default/29.sram_ctrl_max_throughput.421868308 Aug 03 05:59:47 PM PDT 24 Aug 03 06:01:30 PM PDT 24 625787634 ps
T214 /workspace/coverage/default/36.sram_ctrl_smoke.1808661621 Aug 03 06:02:07 PM PDT 24 Aug 03 06:02:15 PM PDT 24 442576339 ps
T215 /workspace/coverage/default/41.sram_ctrl_bijection.27908365 Aug 03 06:03:28 PM PDT 24 Aug 03 06:04:16 PM PDT 24 9240372277 ps
T216 /workspace/coverage/default/29.sram_ctrl_stress_all.2352681031 Aug 03 05:59:57 PM PDT 24 Aug 03 06:22:26 PM PDT 24 24333784367 ps
T217 /workspace/coverage/default/3.sram_ctrl_partial_access.2865884305 Aug 03 05:53:24 PM PDT 24 Aug 03 05:54:21 PM PDT 24 623198130 ps
T218 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2448959560 Aug 03 06:04:48 PM PDT 24 Aug 03 06:08:14 PM PDT 24 20964404693 ps
T219 /workspace/coverage/default/48.sram_ctrl_multiple_keys.3951682862 Aug 03 06:05:14 PM PDT 24 Aug 03 06:09:16 PM PDT 24 3768671130 ps
T220 /workspace/coverage/default/3.sram_ctrl_max_throughput.1290715115 Aug 03 05:53:22 PM PDT 24 Aug 03 05:53:24 PM PDT 24 65354614 ps
T221 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.288310125 Aug 03 05:57:55 PM PDT 24 Aug 03 06:00:44 PM PDT 24 15629561696 ps
T222 /workspace/coverage/default/34.sram_ctrl_bijection.3796930180 Aug 03 06:01:14 PM PDT 24 Aug 03 06:02:15 PM PDT 24 7716035984 ps
T59 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.918910781 Aug 03 06:01:57 PM PDT 24 Aug 03 06:03:16 PM PDT 24 2704572706 ps
T223 /workspace/coverage/default/9.sram_ctrl_bijection.2703386889 Aug 03 05:53:52 PM PDT 24 Aug 03 05:54:48 PM PDT 24 7589925166 ps
T224 /workspace/coverage/default/44.sram_ctrl_smoke.3418146458 Aug 03 06:04:13 PM PDT 24 Aug 03 06:04:15 PM PDT 24 79236896 ps
T225 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2393905199 Aug 03 05:53:08 PM PDT 24 Aug 03 05:53:14 PM PDT 24 70598632 ps
T226 /workspace/coverage/default/28.sram_ctrl_partial_access.1130166020 Aug 03 05:59:21 PM PDT 24 Aug 03 06:01:02 PM PDT 24 551810234 ps
T227 /workspace/coverage/default/49.sram_ctrl_smoke.56809760 Aug 03 06:05:27 PM PDT 24 Aug 03 06:05:35 PM PDT 24 155006288 ps
T228 /workspace/coverage/default/4.sram_ctrl_alert_test.192177772 Aug 03 05:53:26 PM PDT 24 Aug 03 05:53:26 PM PDT 24 14085607 ps
T229 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3533274136 Aug 03 06:03:53 PM PDT 24 Aug 03 06:03:56 PM PDT 24 168645869 ps
T230 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3130637787 Aug 03 05:54:24 PM PDT 24 Aug 03 05:54:25 PM PDT 24 38139397 ps
T231 /workspace/coverage/default/1.sram_ctrl_alert_test.1213534046 Aug 03 05:53:12 PM PDT 24 Aug 03 05:53:13 PM PDT 24 53320333 ps
T60 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1843565712 Aug 03 05:53:35 PM PDT 24 Aug 03 05:53:44 PM PDT 24 946156167 ps
T232 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2613830009 Aug 03 06:05:26 PM PDT 24 Aug 03 06:05:31 PM PDT 24 128172195 ps
T233 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1808715751 Aug 03 05:55:21 PM PDT 24 Aug 03 06:22:22 PM PDT 24 15970645075 ps
T142 /workspace/coverage/default/5.sram_ctrl_stress_all.2773438293 Aug 03 05:53:36 PM PDT 24 Aug 03 07:58:56 PM PDT 24 176550028394 ps
T126 /workspace/coverage/default/31.sram_ctrl_lc_escalation.963581648 Aug 03 06:00:23 PM PDT 24 Aug 03 06:00:33 PM PDT 24 3803807329 ps
T234 /workspace/coverage/default/16.sram_ctrl_executable.2854709416 Aug 03 05:55:36 PM PDT 24 Aug 03 06:08:43 PM PDT 24 35196168325 ps
T235 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.949437648 Aug 03 05:53:16 PM PDT 24 Aug 03 06:03:52 PM PDT 24 96695285227 ps
T236 /workspace/coverage/default/43.sram_ctrl_max_throughput.1196059285 Aug 03 06:04:01 PM PDT 24 Aug 03 06:04:12 PM PDT 24 65408870 ps
T237 /workspace/coverage/default/11.sram_ctrl_multiple_keys.3545899273 Aug 03 05:54:09 PM PDT 24 Aug 03 06:04:54 PM PDT 24 67168204793 ps
T238 /workspace/coverage/default/26.sram_ctrl_multiple_keys.2050315073 Aug 03 05:58:37 PM PDT 24 Aug 03 06:22:36 PM PDT 24 15654016103 ps
T71 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3981838286 Aug 03 05:59:14 PM PDT 24 Aug 03 06:04:29 PM PDT 24 8401799567 ps
T239 /workspace/coverage/default/47.sram_ctrl_mem_walk.1573592573 Aug 03 06:05:07 PM PDT 24 Aug 03 06:05:18 PM PDT 24 677371133 ps
T240 /workspace/coverage/default/40.sram_ctrl_mem_walk.2821575449 Aug 03 06:03:23 PM PDT 24 Aug 03 06:03:29 PM PDT 24 611244368 ps
T241 /workspace/coverage/default/39.sram_ctrl_regwen.583098586 Aug 03 06:03:05 PM PDT 24 Aug 03 06:18:12 PM PDT 24 53488761871 ps
T127 /workspace/coverage/default/37.sram_ctrl_stress_all.4206960493 Aug 03 06:02:34 PM PDT 24 Aug 03 06:59:46 PM PDT 24 206203348843 ps
T242 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3535833613 Aug 03 05:53:58 PM PDT 24 Aug 03 05:55:23 PM PDT 24 559516374 ps
T243 /workspace/coverage/default/21.sram_ctrl_lc_escalation.660349300 Aug 03 05:57:01 PM PDT 24 Aug 03 05:57:04 PM PDT 24 242084060 ps
T244 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2152657758 Aug 03 06:05:43 PM PDT 24 Aug 03 06:05:47 PM PDT 24 328108890 ps
T245 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1525495132 Aug 03 05:55:13 PM PDT 24 Aug 03 06:01:53 PM PDT 24 64772811234 ps
T246 /workspace/coverage/default/0.sram_ctrl_ram_cfg.176997862 Aug 03 05:53:10 PM PDT 24 Aug 03 05:53:11 PM PDT 24 29069986 ps
T247 /workspace/coverage/default/1.sram_ctrl_bijection.4071491084 Aug 03 05:53:09 PM PDT 24 Aug 03 05:54:12 PM PDT 24 982044836 ps
T248 /workspace/coverage/default/41.sram_ctrl_mem_walk.1905912622 Aug 03 06:03:37 PM PDT 24 Aug 03 06:03:49 PM PDT 24 657203498 ps
T249 /workspace/coverage/default/5.sram_ctrl_mem_walk.3575906861 Aug 03 05:53:33 PM PDT 24 Aug 03 05:53:45 PM PDT 24 2369095749 ps
T250 /workspace/coverage/default/5.sram_ctrl_ram_cfg.1010912500 Aug 03 05:53:33 PM PDT 24 Aug 03 05:53:34 PM PDT 24 103476851 ps
T251 /workspace/coverage/default/20.sram_ctrl_regwen.73739908 Aug 03 05:56:37 PM PDT 24 Aug 03 05:58:35 PM PDT 24 4258381922 ps
T252 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2144270660 Aug 03 05:53:32 PM PDT 24 Aug 03 05:59:46 PM PDT 24 11121742552 ps
T253 /workspace/coverage/default/26.sram_ctrl_mem_walk.1633399976 Aug 03 05:58:56 PM PDT 24 Aug 03 05:59:02 PM PDT 24 238175622 ps
T254 /workspace/coverage/default/0.sram_ctrl_regwen.1049822610 Aug 03 05:53:09 PM PDT 24 Aug 03 06:08:34 PM PDT 24 13701248526 ps
T255 /workspace/coverage/default/20.sram_ctrl_max_throughput.2221129258 Aug 03 05:56:36 PM PDT 24 Aug 03 05:58:37 PM PDT 24 540466051 ps
T256 /workspace/coverage/default/26.sram_ctrl_regwen.1880139577 Aug 03 05:58:49 PM PDT 24 Aug 03 05:59:31 PM PDT 24 854469925 ps
T257 /workspace/coverage/default/8.sram_ctrl_regwen.3254768173 Aug 03 05:53:53 PM PDT 24 Aug 03 06:02:59 PM PDT 24 2854278842 ps
T128 /workspace/coverage/default/41.sram_ctrl_stress_all.1842546239 Aug 03 06:03:40 PM PDT 24 Aug 03 06:39:42 PM PDT 24 38214736006 ps
T258 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3999189336 Aug 03 05:59:08 PM PDT 24 Aug 03 06:02:31 PM PDT 24 18473593105 ps
T259 /workspace/coverage/default/42.sram_ctrl_multiple_keys.788918894 Aug 03 06:03:41 PM PDT 24 Aug 03 06:22:02 PM PDT 24 40007759557 ps
T260 /workspace/coverage/default/37.sram_ctrl_ram_cfg.2522095640 Aug 03 06:02:28 PM PDT 24 Aug 03 06:02:29 PM PDT 24 252126897 ps
T261 /workspace/coverage/default/18.sram_ctrl_max_throughput.4127873456 Aug 03 05:55:59 PM PDT 24 Aug 03 05:56:03 PM PDT 24 44979712 ps
T262 /workspace/coverage/default/0.sram_ctrl_bijection.1830807636 Aug 03 05:53:04 PM PDT 24 Aug 03 05:53:26 PM PDT 24 4558290715 ps
T263 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2760202794 Aug 03 06:02:13 PM PDT 24 Aug 03 06:20:42 PM PDT 24 2831504120 ps
T264 /workspace/coverage/default/15.sram_ctrl_regwen.2189461923 Aug 03 05:55:19 PM PDT 24 Aug 03 06:03:21 PM PDT 24 2276678564 ps
T265 /workspace/coverage/default/24.sram_ctrl_multiple_keys.673680052 Aug 03 05:57:48 PM PDT 24 Aug 03 06:17:52 PM PDT 24 54967728875 ps
T266 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.4151742055 Aug 03 06:04:53 PM PDT 24 Aug 03 06:04:56 PM PDT 24 61361442 ps
T267 /workspace/coverage/default/11.sram_ctrl_mem_walk.406906081 Aug 03 05:54:19 PM PDT 24 Aug 03 05:54:25 PM PDT 24 290153123 ps
T268 /workspace/coverage/default/39.sram_ctrl_alert_test.317893226 Aug 03 06:03:08 PM PDT 24 Aug 03 06:03:09 PM PDT 24 36891709 ps
T269 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2137626043 Aug 03 06:05:00 PM PDT 24 Aug 03 06:05:40 PM PDT 24 98547541 ps
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T313 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3767088987 Aug 03 06:00:40 PM PDT 24 Aug 03 06:06:41 PM PDT 24 4696942307 ps
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