Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43685781	1			T1	14944		T2	207593		T3	74
triple_byte_access	2518314	1			T1	280		T2	4051		T3	128
halfword_access	3780563	1			T1	496		T2	6180		T3	250
byte_access	5049350	1			T1	637		T2	8217		T3	393
zero_access	1268476	1			T1	143		T2	2088		T3	163

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28100777

1

T1

8227

T2

114011

T3

372

auto[1]

28201707

1

T1

8273

T2

114118

T3

636

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21795355	1			T1	7466		T2	103798		T3	4
auto[0]	triple_byte_access	1254746	1			T1	136		T2	2041		T3	18
auto[0]	halfword_access	1889202	1			T1	252		T2	3037		T3	49
auto[0]	byte_access	2523897	1			T1	307		T2	4105		T3	181
auto[0]	zero_access	637577	1			T1	66		T2	1030		T3	120
auto[1]	word_access	21890426	1			T1	7478		T2	103795		T3	70
auto[1]	triple_byte_access	1263568	1			T1	144		T2	2010		T3	110
auto[1]	halfword_access	1891361	1			T1	244		T2	3143		T3	201
auto[1]	byte_access	2525453	1			T1	330		T2	4112		T3	212
auto[1]	zero_access	630899	1			T1	77		T2	1058		T3	43