Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	142523986	1			T1	1682		T2	467018		T3	16320
instr_valid_dis	108392314	1			T1	1682		T2	467018		T3	16320
instr_en	26147983	1			T25	45062		T27	116898		T7	5238

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10134560	1			T25	11446		T27	99708		T28	136082
sram_ifetch_valid_disable	110532459	1			T1	1682		T2	467018		T3	16320
sram_ifetch_enable	21856967	1			T27	134144		T28	53516		T49	175536

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	142523986	1			T1	1682		T2	467018		T3	16320
hw_debug_en_valid_off	108866901	1			T1	1682		T2	467018		T3	16320
hw_debug_en_on	22359407	1			T25	33616		T27	157392		T28	150954

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	110532459	1			T1	1682		T2	467018		T3	16320
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	96546596	1			T1	1682		T2	467018		T3	16320
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11177630	1			T25	33616		T27	14204		T7	5238
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3662572	1			T27	21238		T28	119160		T49	45624
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1261260	1			T28	91306		T49	22992		T22	11554
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1894194	1			T27	21238		T28	27854		T49	19666
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4126280	1			T27	65022		T28	16922		T21	36900
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1372678	1			T27	47220		T22	35324		T156	11388
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1945760	1			T27	17802		T28	16922		T97	26308
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8602682	1			T25	33616		T27	724		T28	130828
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3056606	1			T28	51102		T49	101008		T97	21054
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4296736	1			T25	33616		T27	724		T28	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10007465	1			T27	50206		T28	53516		T49	46028
lc_exec_en	9630445	1			T27	91646		T28	3204		T49	43952
valid_exec_dis	105465739	1			T1	1682		T2	467018		T3	16320
invalid_exec_dis	31991527	1			T25	11446		T27	233852		T28	189598