Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	41603813	1			T1	841		T2	42326		T3	8160
triple_byte_access	2639380	1			T2	38108		T4	5155		T12	165
halfword_access	3960259	1			T2	57514		T4	7935		T12	290
byte_access	5285840	1			T2	76640		T4	10533		T12	352
zero_access	1330878	1			T2	18921		T4	2597		T12	83

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27360127

1

T1

392

T2

117209

T3

4184

auto[1]

27460043

1

T1

449

T2

116300

T3

3976

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	20756411	1			T1	392		T2	21186		T3	4184
auto[0]	triple_byte_access	1316028	1			T2	19048		T4	2644		T12	74
auto[0]	halfword_access	1976778	1			T2	28837		T4	4008		T12	135
auto[0]	byte_access	2642028	1			T2	38798		T4	5311		T12	178
auto[0]	zero_access	668882	1			T2	9340		T4	1306		T12	41
auto[1]	word_access	20847402	1			T1	449		T2	21140		T3	3976
auto[1]	triple_byte_access	1323352	1			T2	19060		T4	2511		T12	91
auto[1]	halfword_access	1983481	1			T2	28677		T4	3927		T12	155
auto[1]	byte_access	2643812	1			T2	37842		T4	5222		T12	174
auto[1]	zero_access	661996	1			T2	9581		T4	1291		T12	42