| T798 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2722948758 |
|
|
Aug 04 05:43:29 PM PDT 24 |
Aug 04 05:48:52 PM PDT 24 |
14029854838 ps |
| T799 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3714786223 |
|
|
Aug 04 05:44:07 PM PDT 24 |
Aug 04 05:44:14 PM PDT 24 |
647904714 ps |
| T800 |
/workspace/coverage/default/32.sram_ctrl_bijection.2777410089 |
|
|
Aug 04 05:44:16 PM PDT 24 |
Aug 04 05:45:12 PM PDT 24 |
879053152 ps |
| T801 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.1729158774 |
|
|
Aug 04 05:43:39 PM PDT 24 |
Aug 04 05:43:40 PM PDT 24 |
29663791 ps |
| T802 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3828751256 |
|
|
Aug 04 05:42:44 PM PDT 24 |
Aug 04 05:42:49 PM PDT 24 |
248718446 ps |
| T803 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2867266055 |
|
|
Aug 04 05:44:23 PM PDT 24 |
Aug 04 05:44:24 PM PDT 24 |
14973415 ps |
| T804 |
/workspace/coverage/default/40.sram_ctrl_smoke.3882916196 |
|
|
Aug 04 05:45:04 PM PDT 24 |
Aug 04 05:47:02 PM PDT 24 |
136319741 ps |
| T805 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.198080595 |
|
|
Aug 04 05:42:48 PM PDT 24 |
Aug 04 05:42:54 PM PDT 24 |
347895159 ps |
| T806 |
/workspace/coverage/default/4.sram_ctrl_smoke.2079897904 |
|
|
Aug 04 05:42:56 PM PDT 24 |
Aug 04 05:43:01 PM PDT 24 |
411145120 ps |
| T807 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3579565783 |
|
|
Aug 04 05:45:49 PM PDT 24 |
Aug 04 05:52:39 PM PDT 24 |
1285102946 ps |
| T808 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1772753971 |
|
|
Aug 04 05:45:15 PM PDT 24 |
Aug 04 05:45:24 PM PDT 24 |
1203500790 ps |
| T809 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3121587642 |
|
|
Aug 04 05:42:52 PM PDT 24 |
Aug 04 05:45:58 PM PDT 24 |
4015201421 ps |
| T810 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3258409235 |
|
|
Aug 04 05:43:29 PM PDT 24 |
Aug 04 05:48:43 PM PDT 24 |
14002974660 ps |
| T811 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1091753717 |
|
|
Aug 04 05:43:33 PM PDT 24 |
Aug 04 05:49:17 PM PDT 24 |
2945444674 ps |
| T812 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.29348225 |
|
|
Aug 04 05:45:20 PM PDT 24 |
Aug 04 05:55:15 PM PDT 24 |
5849594738 ps |
| T813 |
/workspace/coverage/default/28.sram_ctrl_regwen.238253548 |
|
|
Aug 04 05:44:14 PM PDT 24 |
Aug 04 06:04:25 PM PDT 24 |
93752583660 ps |
| T814 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3899627846 |
|
|
Aug 04 05:43:15 PM PDT 24 |
Aug 04 06:04:21 PM PDT 24 |
4113031488 ps |
| T815 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.1773553970 |
|
|
Aug 04 05:43:39 PM PDT 24 |
Aug 04 05:43:40 PM PDT 24 |
81762294 ps |
| T816 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.311559642 |
|
|
Aug 04 05:42:49 PM PDT 24 |
Aug 04 05:42:50 PM PDT 24 |
89528050 ps |
| T817 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.2434186031 |
|
|
Aug 04 05:43:28 PM PDT 24 |
Aug 04 05:43:36 PM PDT 24 |
135693879 ps |
| T818 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2747556895 |
|
|
Aug 04 05:43:31 PM PDT 24 |
Aug 04 05:53:07 PM PDT 24 |
13052572148 ps |
| T819 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3101931368 |
|
|
Aug 04 05:44:46 PM PDT 24 |
Aug 04 06:02:30 PM PDT 24 |
16147504548 ps |
| T820 |
/workspace/coverage/default/38.sram_ctrl_partial_access.311633030 |
|
|
Aug 04 05:44:49 PM PDT 24 |
Aug 04 05:45:08 PM PDT 24 |
12524430912 ps |
| T821 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.110926330 |
|
|
Aug 04 05:42:43 PM PDT 24 |
Aug 04 05:49:47 PM PDT 24 |
16765607428 ps |
| T822 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.277020838 |
|
|
Aug 04 05:43:49 PM PDT 24 |
Aug 04 05:46:58 PM PDT 24 |
8106430358 ps |
| T823 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2398259257 |
|
|
Aug 04 05:43:34 PM PDT 24 |
Aug 04 05:43:35 PM PDT 24 |
14121919 ps |
| T824 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3779288330 |
|
|
Aug 04 05:43:30 PM PDT 24 |
Aug 04 05:52:22 PM PDT 24 |
2897344779 ps |
| T825 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3847606081 |
|
|
Aug 04 05:45:42 PM PDT 24 |
Aug 04 05:49:35 PM PDT 24 |
12987796208 ps |
| T826 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1548002643 |
|
|
Aug 04 05:44:49 PM PDT 24 |
Aug 04 06:04:59 PM PDT 24 |
10388779286 ps |
| T827 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3446229685 |
|
|
Aug 04 05:43:27 PM PDT 24 |
Aug 04 05:48:49 PM PDT 24 |
4522033799 ps |
| T828 |
/workspace/coverage/default/28.sram_ctrl_bijection.47618575 |
|
|
Aug 04 05:44:13 PM PDT 24 |
Aug 04 05:45:33 PM PDT 24 |
13947948210 ps |
| T829 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.741266655 |
|
|
Aug 04 05:44:12 PM PDT 24 |
Aug 04 05:44:24 PM PDT 24 |
1099588995 ps |
| T830 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.3959968720 |
|
|
Aug 04 05:42:53 PM PDT 24 |
Aug 04 05:42:54 PM PDT 24 |
89807171 ps |
| T831 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.2657721996 |
|
|
Aug 04 05:44:43 PM PDT 24 |
Aug 04 05:44:46 PM PDT 24 |
484938586 ps |
| T832 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3240935300 |
|
|
Aug 04 05:43:35 PM PDT 24 |
Aug 04 05:44:09 PM PDT 24 |
168755177 ps |
| T833 |
/workspace/coverage/default/25.sram_ctrl_executable.3810918331 |
|
|
Aug 04 05:43:54 PM PDT 24 |
Aug 04 05:58:59 PM PDT 24 |
25554755076 ps |
| T834 |
/workspace/coverage/default/3.sram_ctrl_executable.636230064 |
|
|
Aug 04 05:42:52 PM PDT 24 |
Aug 04 05:58:02 PM PDT 24 |
75661097288 ps |
| T835 |
/workspace/coverage/default/14.sram_ctrl_partial_access.2796583596 |
|
|
Aug 04 05:43:31 PM PDT 24 |
Aug 04 05:44:04 PM PDT 24 |
853922596 ps |
| T836 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3791328402 |
|
|
Aug 04 05:43:31 PM PDT 24 |
Aug 04 05:52:20 PM PDT 24 |
154029019962 ps |
| T837 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3924057997 |
|
|
Aug 04 05:45:33 PM PDT 24 |
Aug 04 05:45:44 PM PDT 24 |
712074920 ps |
| T838 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2837363182 |
|
|
Aug 04 05:42:44 PM PDT 24 |
Aug 04 05:56:26 PM PDT 24 |
10193112022 ps |
| T839 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3771397074 |
|
|
Aug 04 05:42:42 PM PDT 24 |
Aug 04 05:42:49 PM PDT 24 |
450103208 ps |
| T840 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1674838927 |
|
|
Aug 04 05:45:05 PM PDT 24 |
Aug 04 05:52:30 PM PDT 24 |
5248112749 ps |
| T841 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1253868748 |
|
|
Aug 04 05:43:57 PM PDT 24 |
Aug 04 05:48:41 PM PDT 24 |
45633852869 ps |
| T842 |
/workspace/coverage/default/30.sram_ctrl_bijection.3775026158 |
|
|
Aug 04 05:44:10 PM PDT 24 |
Aug 04 05:45:18 PM PDT 24 |
3865994449 ps |
| T843 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2055626786 |
|
|
Aug 04 05:43:23 PM PDT 24 |
Aug 04 05:44:14 PM PDT 24 |
414101023 ps |
| T844 |
/workspace/coverage/default/49.sram_ctrl_smoke.35678765 |
|
|
Aug 04 05:46:07 PM PDT 24 |
Aug 04 05:46:13 PM PDT 24 |
151172494 ps |
| T845 |
/workspace/coverage/default/25.sram_ctrl_regwen.280762519 |
|
|
Aug 04 05:43:52 PM PDT 24 |
Aug 04 05:47:46 PM PDT 24 |
2014009807 ps |
| T846 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3502301317 |
|
|
Aug 04 05:44:26 PM PDT 24 |
Aug 04 05:46:47 PM PDT 24 |
2283291260 ps |
| T847 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.461229555 |
|
|
Aug 04 05:45:55 PM PDT 24 |
Aug 04 05:53:37 PM PDT 24 |
1555551908 ps |
| T848 |
/workspace/coverage/default/44.sram_ctrl_partial_access.2848092317 |
|
|
Aug 04 05:45:31 PM PDT 24 |
Aug 04 05:46:37 PM PDT 24 |
186903210 ps |
| T849 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3387325685 |
|
|
Aug 04 05:43:18 PM PDT 24 |
Aug 04 05:46:54 PM PDT 24 |
1290530363 ps |
| T850 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.845447652 |
|
|
Aug 04 05:44:13 PM PDT 24 |
Aug 04 05:46:17 PM PDT 24 |
3798993125 ps |
| T851 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2422635050 |
|
|
Aug 04 05:42:37 PM PDT 24 |
Aug 04 05:45:28 PM PDT 24 |
7034446185 ps |
| T852 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.7706424 |
|
|
Aug 04 05:44:00 PM PDT 24 |
Aug 04 05:44:22 PM PDT 24 |
193763263 ps |
| T853 |
/workspace/coverage/default/16.sram_ctrl_executable.1185795097 |
|
|
Aug 04 05:43:32 PM PDT 24 |
Aug 04 05:44:57 PM PDT 24 |
8660778298 ps |
| T854 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.1625266159 |
|
|
Aug 04 05:45:40 PM PDT 24 |
Aug 04 05:45:51 PM PDT 24 |
884541852 ps |
| T855 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3616692699 |
|
|
Aug 04 05:43:21 PM PDT 24 |
Aug 04 05:45:48 PM PDT 24 |
371468285 ps |
| T856 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.158337258 |
|
|
Aug 04 05:44:54 PM PDT 24 |
Aug 04 05:44:57 PM PDT 24 |
126037458 ps |
| T857 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3022729802 |
|
|
Aug 04 05:45:39 PM PDT 24 |
Aug 04 05:45:45 PM PDT 24 |
1920092335 ps |
| T858 |
/workspace/coverage/default/18.sram_ctrl_bijection.2064318128 |
|
|
Aug 04 05:43:28 PM PDT 24 |
Aug 04 05:44:17 PM PDT 24 |
2920839179 ps |
| T859 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3038820135 |
|
|
Aug 04 05:43:36 PM PDT 24 |
Aug 04 05:44:48 PM PDT 24 |
273337687 ps |
| T860 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4229768332 |
|
|
Aug 04 05:45:03 PM PDT 24 |
Aug 04 05:50:40 PM PDT 24 |
171132843652 ps |
| T861 |
/workspace/coverage/default/0.sram_ctrl_partial_access.27973396 |
|
|
Aug 04 05:42:52 PM PDT 24 |
Aug 04 05:42:57 PM PDT 24 |
56189371 ps |
| T862 |
/workspace/coverage/default/42.sram_ctrl_alert_test.2883681385 |
|
|
Aug 04 05:45:22 PM PDT 24 |
Aug 04 05:45:22 PM PDT 24 |
16550529 ps |
| T863 |
/workspace/coverage/default/27.sram_ctrl_partial_access.3527927150 |
|
|
Aug 04 05:44:02 PM PDT 24 |
Aug 04 05:44:04 PM PDT 24 |
281857488 ps |
| T864 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2032384731 |
|
|
Aug 04 05:43:32 PM PDT 24 |
Aug 04 05:44:32 PM PDT 24 |
3933346834 ps |
| T865 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.3496458861 |
|
|
Aug 04 05:44:15 PM PDT 24 |
Aug 04 05:44:16 PM PDT 24 |
82815733 ps |
| T866 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.4153545319 |
|
|
Aug 04 05:43:17 PM PDT 24 |
Aug 04 05:45:48 PM PDT 24 |
1586131348 ps |
| T867 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.196695177 |
|
|
Aug 04 05:43:28 PM PDT 24 |
Aug 04 06:00:09 PM PDT 24 |
5957255250 ps |
| T868 |
/workspace/coverage/default/15.sram_ctrl_executable.693927454 |
|
|
Aug 04 05:43:30 PM PDT 24 |
Aug 04 05:56:33 PM PDT 24 |
13467668447 ps |
| T869 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2449879475 |
|
|
Aug 04 05:45:26 PM PDT 24 |
Aug 04 05:45:29 PM PDT 24 |
262082353 ps |
| T870 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.859789611 |
|
|
Aug 04 05:43:37 PM PDT 24 |
Aug 04 05:49:18 PM PDT 24 |
1848208965 ps |
| T871 |
/workspace/coverage/default/27.sram_ctrl_alert_test.4143544334 |
|
|
Aug 04 05:44:09 PM PDT 24 |
Aug 04 05:44:10 PM PDT 24 |
51632962 ps |
| T872 |
/workspace/coverage/default/46.sram_ctrl_regwen.2793779315 |
|
|
Aug 04 05:45:49 PM PDT 24 |
Aug 04 05:54:38 PM PDT 24 |
1996914670 ps |
| T873 |
/workspace/coverage/default/47.sram_ctrl_partial_access.727704905 |
|
|
Aug 04 05:45:51 PM PDT 24 |
Aug 04 05:47:41 PM PDT 24 |
2397326554 ps |
| T874 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1409423656 |
|
|
Aug 04 05:43:28 PM PDT 24 |
Aug 04 05:43:34 PM PDT 24 |
790213399 ps |
| T875 |
/workspace/coverage/default/15.sram_ctrl_partial_access.1186177398 |
|
|
Aug 04 05:43:28 PM PDT 24 |
Aug 04 05:43:43 PM PDT 24 |
1593223202 ps |
| T876 |
/workspace/coverage/default/21.sram_ctrl_bijection.84944603 |
|
|
Aug 04 05:43:31 PM PDT 24 |
Aug 04 05:44:35 PM PDT 24 |
8383965411 ps |
| T877 |
/workspace/coverage/default/17.sram_ctrl_regwen.3158609871 |
|
|
Aug 04 05:43:31 PM PDT 24 |
Aug 04 05:58:09 PM PDT 24 |
8097566361 ps |
| T878 |
/workspace/coverage/default/26.sram_ctrl_alert_test.1694541957 |
|
|
Aug 04 05:44:06 PM PDT 24 |
Aug 04 05:44:06 PM PDT 24 |
153817459 ps |
| T879 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.2116411247 |
|
|
Aug 04 05:44:02 PM PDT 24 |
Aug 04 05:44:08 PM PDT 24 |
2031866226 ps |
| T880 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1377438671 |
|
|
Aug 04 05:43:28 PM PDT 24 |
Aug 04 05:43:45 PM PDT 24 |
320383622 ps |
| T881 |
/workspace/coverage/default/33.sram_ctrl_executable.313073081 |
|
|
Aug 04 05:44:25 PM PDT 24 |
Aug 04 05:57:38 PM PDT 24 |
20641238016 ps |
| T882 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.3115148717 |
|
|
Aug 04 05:45:37 PM PDT 24 |
Aug 04 05:45:41 PM PDT 24 |
180618356 ps |
| T883 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3159134375 |
|
|
Aug 04 05:45:23 PM PDT 24 |
Aug 04 05:56:34 PM PDT 24 |
13231653371 ps |
| T884 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3012818036 |
|
|
Aug 04 05:43:22 PM PDT 24 |
Aug 04 05:50:05 PM PDT 24 |
91243922144 ps |
| T885 |
/workspace/coverage/default/28.sram_ctrl_stress_all.1850640180 |
|
|
Aug 04 05:44:10 PM PDT 24 |
Aug 04 06:13:41 PM PDT 24 |
33393210943 ps |
| T886 |
/workspace/coverage/default/11.sram_ctrl_partial_access.2453098815 |
|
|
Aug 04 05:43:31 PM PDT 24 |
Aug 04 05:45:50 PM PDT 24 |
1697255666 ps |
| T33 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1699476959 |
|
|
Aug 04 05:43:27 PM PDT 24 |
Aug 04 05:43:30 PM PDT 24 |
516440528 ps |
| T887 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.3199652639 |
|
|
Aug 04 05:45:05 PM PDT 24 |
Aug 04 05:45:11 PM PDT 24 |
52828232 ps |
| T888 |
/workspace/coverage/default/42.sram_ctrl_smoke.2761014277 |
|
|
Aug 04 05:45:18 PM PDT 24 |
Aug 04 05:46:34 PM PDT 24 |
520989382 ps |
| T889 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.3515982261 |
|
|
Aug 04 05:45:55 PM PDT 24 |
Aug 04 05:46:06 PM PDT 24 |
682503384 ps |
| T890 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1639166645 |
|
|
Aug 04 05:45:38 PM PDT 24 |
Aug 04 05:46:25 PM PDT 24 |
214510527 ps |
| T891 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.3830892497 |
|
|
Aug 04 05:45:11 PM PDT 24 |
Aug 04 05:45:12 PM PDT 24 |
41553492 ps |
| T892 |
/workspace/coverage/default/26.sram_ctrl_executable.1864932821 |
|
|
Aug 04 05:43:59 PM PDT 24 |
Aug 04 05:49:03 PM PDT 24 |
13944275137 ps |
| T893 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.1870800214 |
|
|
Aug 04 05:43:35 PM PDT 24 |
Aug 04 05:43:38 PM PDT 24 |
168759501 ps |
| T894 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.2884400418 |
|
|
Aug 04 05:44:44 PM PDT 24 |
Aug 04 05:44:56 PM PDT 24 |
2636609029 ps |
| T132 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.606406677 |
|
|
Aug 04 05:45:47 PM PDT 24 |
Aug 04 05:46:13 PM PDT 24 |
3260080536 ps |
| T895 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.461663940 |
|
|
Aug 04 05:44:45 PM PDT 24 |
Aug 04 05:45:05 PM PDT 24 |
159878055 ps |
| T896 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.1670067235 |
|
|
Aug 04 05:42:44 PM PDT 24 |
Aug 04 05:42:48 PM PDT 24 |
67247610 ps |
| T897 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.610964225 |
|
|
Aug 04 05:44:11 PM PDT 24 |
Aug 04 05:46:33 PM PDT 24 |
8247279386 ps |
| T898 |
/workspace/coverage/default/10.sram_ctrl_smoke.2913239285 |
|
|
Aug 04 05:43:31 PM PDT 24 |
Aug 04 05:43:41 PM PDT 24 |
1135033067 ps |
| T899 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.3391786478 |
|
|
Aug 04 05:44:54 PM PDT 24 |
Aug 04 05:48:34 PM PDT 24 |
2397274160 ps |
| T900 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.1251269130 |
|
|
Aug 04 05:43:27 PM PDT 24 |
Aug 04 05:43:33 PM PDT 24 |
152265986 ps |
| T901 |
/workspace/coverage/default/33.sram_ctrl_stress_all.1879861071 |
|
|
Aug 04 05:44:27 PM PDT 24 |
Aug 04 06:41:59 PM PDT 24 |
64915736776 ps |
| T902 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.852218220 |
|
|
Aug 04 05:45:05 PM PDT 24 |
Aug 04 05:48:10 PM PDT 24 |
1886137611 ps |
| T903 |
/workspace/coverage/default/7.sram_ctrl_partial_access.274225630 |
|
|
Aug 04 05:43:21 PM PDT 24 |
Aug 04 05:44:54 PM PDT 24 |
2104105047 ps |
| T904 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.3117476047 |
|
|
Aug 04 05:44:54 PM PDT 24 |
Aug 04 05:45:05 PM PDT 24 |
13133523055 ps |
| T905 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.4085715932 |
|
|
Aug 04 05:43:29 PM PDT 24 |
Aug 04 05:44:35 PM PDT 24 |
1932913098 ps |
| T906 |
/workspace/coverage/default/48.sram_ctrl_bijection.3943645148 |
|
|
Aug 04 05:45:57 PM PDT 24 |
Aug 04 05:46:29 PM PDT 24 |
3478689106 ps |
| T907 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.12594571 |
|
|
Aug 04 05:44:11 PM PDT 24 |
Aug 04 05:44:21 PM PDT 24 |
87391368 ps |
| T908 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3383554553 |
|
|
Aug 04 05:42:42 PM PDT 24 |
Aug 04 05:42:43 PM PDT 24 |
81149856 ps |
| T909 |
/workspace/coverage/default/3.sram_ctrl_bijection.3809633810 |
|
|
Aug 04 05:42:49 PM PDT 24 |
Aug 04 05:43:25 PM PDT 24 |
1100715547 ps |
| T910 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2020112501 |
|
|
Aug 04 05:45:05 PM PDT 24 |
Aug 04 05:45:26 PM PDT 24 |
85040357 ps |
| T911 |
/workspace/coverage/default/19.sram_ctrl_partial_access.1360606150 |
|
|
Aug 04 05:43:31 PM PDT 24 |
Aug 04 05:43:47 PM PDT 24 |
4802311001 ps |
| T912 |
/workspace/coverage/default/12.sram_ctrl_alert_test.4055277717 |
|
|
Aug 04 05:43:32 PM PDT 24 |
Aug 04 05:43:34 PM PDT 24 |
12603905 ps |
| T913 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2254040498 |
|
|
Aug 04 05:45:29 PM PDT 24 |
Aug 04 05:50:24 PM PDT 24 |
16297214191 ps |
| T914 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2781580630 |
|
|
Aug 04 05:44:13 PM PDT 24 |
Aug 04 05:45:17 PM PDT 24 |
358175791 ps |
| T915 |
/workspace/coverage/default/15.sram_ctrl_regwen.1369926336 |
|
|
Aug 04 05:43:33 PM PDT 24 |
Aug 04 05:53:51 PM PDT 24 |
58402068392 ps |
| T916 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2126349470 |
|
|
Aug 04 05:45:23 PM PDT 24 |
Aug 04 05:47:47 PM PDT 24 |
231711885 ps |
| T917 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.3629603942 |
|
|
Aug 04 05:44:47 PM PDT 24 |
Aug 04 06:07:41 PM PDT 24 |
12664378831 ps |
| T918 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1192709866 |
|
|
Aug 04 05:43:25 PM PDT 24 |
Aug 04 05:47:15 PM PDT 24 |
9218510167 ps |
| T919 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.823008189 |
|
|
Aug 04 05:45:55 PM PDT 24 |
Aug 04 05:46:02 PM PDT 24 |
887015742 ps |
| T920 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2808268568 |
|
|
Aug 04 05:43:29 PM PDT 24 |
Aug 04 05:45:07 PM PDT 24 |
741341225 ps |
| T921 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1123468307 |
|
|
Aug 04 05:43:27 PM PDT 24 |
Aug 04 05:43:28 PM PDT 24 |
36937530 ps |
| T922 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1605138836 |
|
|
Aug 04 05:43:35 PM PDT 24 |
Aug 04 05:45:44 PM PDT 24 |
139734164 ps |
| T923 |
/workspace/coverage/default/35.sram_ctrl_executable.2164410042 |
|
|
Aug 04 05:44:39 PM PDT 24 |
Aug 04 05:58:59 PM PDT 24 |
7520028083 ps |
| T924 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.539864548 |
|
|
Aug 04 05:43:27 PM PDT 24 |
Aug 04 05:43:28 PM PDT 24 |
27766246 ps |
| T925 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.255333810 |
|
|
Aug 04 05:43:24 PM PDT 24 |
Aug 04 05:51:32 PM PDT 24 |
20346226255 ps |
| T926 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.1669507926 |
|
|
Aug 04 05:43:33 PM PDT 24 |
Aug 04 05:43:34 PM PDT 24 |
47659584 ps |
| T927 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2629311700 |
|
|
Aug 04 05:43:23 PM PDT 24 |
Aug 04 05:55:50 PM PDT 24 |
2017322704 ps |
| T928 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2042216823 |
|
|
Aug 04 05:44:05 PM PDT 24 |
Aug 04 05:48:23 PM PDT 24 |
2660365204 ps |
| T929 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.19696673 |
|
|
Aug 04 05:45:21 PM PDT 24 |
Aug 04 05:48:18 PM PDT 24 |
1944288815 ps |
| T930 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3406061978 |
|
|
Aug 04 05:43:31 PM PDT 24 |
Aug 04 05:43:32 PM PDT 24 |
46041016 ps |
| T931 |
/workspace/coverage/default/36.sram_ctrl_alert_test.497734945 |
|
|
Aug 04 05:44:50 PM PDT 24 |
Aug 04 05:44:51 PM PDT 24 |
40662512 ps |
| T932 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3032116613 |
|
|
Aug 04 05:44:46 PM PDT 24 |
Aug 04 05:47:25 PM PDT 24 |
22739076435 ps |
| T933 |
/workspace/coverage/default/9.sram_ctrl_smoke.3887043245 |
|
|
Aug 04 05:43:26 PM PDT 24 |
Aug 04 05:43:50 PM PDT 24 |
1448057680 ps |
| T934 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4216175457 |
|
|
Aug 04 05:43:30 PM PDT 24 |
Aug 04 06:02:47 PM PDT 24 |
65841473301 ps |
| T935 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.1611221505 |
|
|
Aug 04 05:43:32 PM PDT 24 |
Aug 04 05:43:38 PM PDT 24 |
53836339 ps |
| T69 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3835570903 |
|
|
Aug 04 04:29:07 PM PDT 24 |
Aug 04 04:29:09 PM PDT 24 |
235604748 ps |
| T73 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1763633313 |
|
|
Aug 04 04:29:06 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
30154145 ps |
| T936 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2258005989 |
|
|
Aug 04 04:29:08 PM PDT 24 |
Aug 04 04:29:10 PM PDT 24 |
113914140 ps |
| T74 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2333757420 |
|
|
Aug 04 04:29:11 PM PDT 24 |
Aug 04 04:29:12 PM PDT 24 |
13043554 ps |
| T82 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.997352771 |
|
|
Aug 04 04:29:12 PM PDT 24 |
Aug 04 04:29:13 PM PDT 24 |
20436414 ps |
| T70 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4134007007 |
|
|
Aug 04 04:29:49 PM PDT 24 |
Aug 04 04:29:51 PM PDT 24 |
793602655 ps |
| T124 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1024393391 |
|
|
Aug 04 04:29:23 PM PDT 24 |
Aug 04 04:29:23 PM PDT 24 |
32393747 ps |
| T937 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3313011051 |
|
|
Aug 04 04:29:13 PM PDT 24 |
Aug 04 04:29:16 PM PDT 24 |
169337801 ps |
| T83 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1698230942 |
|
|
Aug 04 04:29:29 PM PDT 24 |
Aug 04 04:29:29 PM PDT 24 |
11228384 ps |
| T938 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3423776737 |
|
|
Aug 04 04:29:09 PM PDT 24 |
Aug 04 04:29:14 PM PDT 24 |
230814007 ps |
| T939 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3262260431 |
|
|
Aug 04 04:29:14 PM PDT 24 |
Aug 04 04:29:19 PM PDT 24 |
115568841 ps |
| T940 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2762827468 |
|
|
Aug 04 04:29:04 PM PDT 24 |
Aug 04 04:29:05 PM PDT 24 |
67845875 ps |
| T71 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2299323757 |
|
|
Aug 04 04:29:02 PM PDT 24 |
Aug 04 04:29:04 PM PDT 24 |
732627603 ps |
| T84 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1133640127 |
|
|
Aug 04 04:29:07 PM PDT 24 |
Aug 04 04:29:08 PM PDT 24 |
57272159 ps |
| T941 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3792273798 |
|
|
Aug 04 04:29:04 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
88257209 ps |
| T85 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3938590857 |
|
|
Aug 04 04:29:10 PM PDT 24 |
Aug 04 04:29:12 PM PDT 24 |
206437805 ps |
| T86 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.173051399 |
|
|
Aug 04 04:29:38 PM PDT 24 |
Aug 04 04:29:41 PM PDT 24 |
410775228 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2522494312 |
|
|
Aug 04 04:28:59 PM PDT 24 |
Aug 04 04:29:01 PM PDT 24 |
93957564 ps |
| T942 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3134106710 |
|
|
Aug 04 04:29:00 PM PDT 24 |
Aug 04 04:29:02 PM PDT 24 |
133025061 ps |
| T142 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1590747992 |
|
|
Aug 04 04:29:01 PM PDT 24 |
Aug 04 04:29:04 PM PDT 24 |
264086932 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3964657472 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:05 PM PDT 24 |
48906548 ps |
| T119 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2375311527 |
|
|
Aug 04 04:29:11 PM PDT 24 |
Aug 04 04:29:11 PM PDT 24 |
37766244 ps |
| T120 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1931830247 |
|
|
Aug 04 04:29:13 PM PDT 24 |
Aug 04 04:29:13 PM PDT 24 |
49237765 ps |
| T88 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.619166558 |
|
|
Aug 04 04:29:16 PM PDT 24 |
Aug 04 04:29:16 PM PDT 24 |
30139635 ps |
| T121 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3285205040 |
|
|
Aug 04 04:29:05 PM PDT 24 |
Aug 04 04:29:06 PM PDT 24 |
13540897 ps |
| T146 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2859044441 |
|
|
Aug 04 04:29:07 PM PDT 24 |
Aug 04 04:29:09 PM PDT 24 |
361542663 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3102439613 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:05 PM PDT 24 |
96069078 ps |
| T122 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3678469517 |
|
|
Aug 04 04:29:00 PM PDT 24 |
Aug 04 04:29:02 PM PDT 24 |
888750589 ps |
| T89 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1447364625 |
|
|
Aug 04 04:29:14 PM PDT 24 |
Aug 04 04:29:16 PM PDT 24 |
223311310 ps |
| T90 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.105580064 |
|
|
Aug 04 04:29:08 PM PDT 24 |
Aug 04 04:29:09 PM PDT 24 |
22706105 ps |
| T945 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.270652665 |
|
|
Aug 04 04:29:06 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
132421417 ps |
| T91 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.339093981 |
|
|
Aug 04 04:29:10 PM PDT 24 |
Aug 04 04:29:17 PM PDT 24 |
798859858 ps |
| T946 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3266209668 |
|
|
Aug 04 04:29:01 PM PDT 24 |
Aug 04 04:29:02 PM PDT 24 |
15853833 ps |
| T103 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1086516777 |
|
|
Aug 04 04:29:01 PM PDT 24 |
Aug 04 04:29:02 PM PDT 24 |
49289007 ps |
| T947 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3098765447 |
|
|
Aug 04 04:29:15 PM PDT 24 |
Aug 04 04:29:16 PM PDT 24 |
28082587 ps |
| T948 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2463064712 |
|
|
Aug 04 04:29:15 PM PDT 24 |
Aug 04 04:29:17 PM PDT 24 |
24780594 ps |
| T149 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2647768977 |
|
|
Aug 04 04:29:06 PM PDT 24 |
Aug 04 04:29:08 PM PDT 24 |
282838949 ps |
| T949 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.958948151 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:04 PM PDT 24 |
30240878 ps |
| T950 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1396827138 |
|
|
Aug 04 04:29:09 PM PDT 24 |
Aug 04 04:29:11 PM PDT 24 |
66692008 ps |
| T951 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.618008752 |
|
|
Aug 04 04:29:04 PM PDT 24 |
Aug 04 04:29:05 PM PDT 24 |
86326268 ps |
| T952 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1902809376 |
|
|
Aug 04 04:29:35 PM PDT 24 |
Aug 04 04:29:36 PM PDT 24 |
25514695 ps |
| T953 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1702894086 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
36267669 ps |
| T147 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3483041295 |
|
|
Aug 04 04:29:38 PM PDT 24 |
Aug 04 04:29:40 PM PDT 24 |
295075303 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2720122136 |
|
|
Aug 04 04:29:00 PM PDT 24 |
Aug 04 04:29:01 PM PDT 24 |
40964124 ps |
| T955 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2040968245 |
|
|
Aug 04 04:29:02 PM PDT 24 |
Aug 04 04:29:03 PM PDT 24 |
26946867 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4160784848 |
|
|
Aug 04 04:29:13 PM PDT 24 |
Aug 04 04:29:14 PM PDT 24 |
18980707 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3055081283 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
336095556 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3764891018 |
|
|
Aug 04 04:29:01 PM PDT 24 |
Aug 04 04:29:02 PM PDT 24 |
18564741 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2030343480 |
|
|
Aug 04 04:29:04 PM PDT 24 |
Aug 04 04:29:05 PM PDT 24 |
17929107 ps |
| T152 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3906735715 |
|
|
Aug 04 04:29:11 PM PDT 24 |
Aug 04 04:29:12 PM PDT 24 |
143868225 ps |
| T960 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3645036031 |
|
|
Aug 04 04:29:19 PM PDT 24 |
Aug 04 04:29:21 PM PDT 24 |
51171834 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1331384515 |
|
|
Aug 04 04:28:58 PM PDT 24 |
Aug 04 04:29:02 PM PDT 24 |
131584896 ps |
| T962 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3105785994 |
|
|
Aug 04 04:29:08 PM PDT 24 |
Aug 04 04:29:09 PM PDT 24 |
84382846 ps |
| T963 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1127697562 |
|
|
Aug 04 04:29:12 PM PDT 24 |
Aug 04 04:29:17 PM PDT 24 |
972980003 ps |
| T964 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1582044390 |
|
|
Aug 04 04:29:30 PM PDT 24 |
Aug 04 04:29:33 PM PDT 24 |
115013935 ps |
| T965 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2405374333 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:05 PM PDT 24 |
35980517 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.743112357 |
|
|
Aug 04 04:29:09 PM PDT 24 |
Aug 04 04:29:11 PM PDT 24 |
42806067 ps |
| T967 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.563872622 |
|
|
Aug 04 04:29:10 PM PDT 24 |
Aug 04 04:29:11 PM PDT 24 |
118745127 ps |
| T104 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2982331778 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
421767684 ps |
| T968 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3472769241 |
|
|
Aug 04 04:29:02 PM PDT 24 |
Aug 04 04:29:03 PM PDT 24 |
50902272 ps |
| T969 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2449384286 |
|
|
Aug 04 04:29:13 PM PDT 24 |
Aug 04 04:29:14 PM PDT 24 |
16539735 ps |
| T105 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1194544601 |
|
|
Aug 04 04:29:04 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
751031599 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3106175517 |
|
|
Aug 04 04:30:18 PM PDT 24 |
Aug 04 04:30:21 PM PDT 24 |
831732809 ps |
| T971 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3358612630 |
|
|
Aug 04 04:29:06 PM PDT 24 |
Aug 04 04:29:08 PM PDT 24 |
135144075 ps |
| T106 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2538201038 |
|
|
Aug 04 04:29:24 PM PDT 24 |
Aug 04 04:29:26 PM PDT 24 |
612657696 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.473250001 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:04 PM PDT 24 |
25761645 ps |
| T973 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.820102984 |
|
|
Aug 04 04:29:11 PM PDT 24 |
Aug 04 04:29:12 PM PDT 24 |
25485048 ps |
| T107 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2720521520 |
|
|
Aug 04 04:29:06 PM PDT 24 |
Aug 04 04:29:18 PM PDT 24 |
965143351 ps |
| T117 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3408890613 |
|
|
Aug 04 04:29:14 PM PDT 24 |
Aug 04 04:29:15 PM PDT 24 |
17611168 ps |
| T974 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.175841378 |
|
|
Aug 04 04:29:14 PM PDT 24 |
Aug 04 04:29:15 PM PDT 24 |
14012736 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3981259068 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
1976888665 ps |
| T112 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.27546075 |
|
|
Aug 04 04:29:27 PM PDT 24 |
Aug 04 04:29:29 PM PDT 24 |
1130485846 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3856707595 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:04 PM PDT 24 |
296069056 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3611414214 |
|
|
Aug 04 04:29:05 PM PDT 24 |
Aug 04 04:29:11 PM PDT 24 |
53919843 ps |
| T978 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1318756375 |
|
|
Aug 04 04:29:16 PM PDT 24 |
Aug 04 04:29:17 PM PDT 24 |
31420775 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1239041079 |
|
|
Aug 04 04:29:36 PM PDT 24 |
Aug 04 04:29:40 PM PDT 24 |
1424007550 ps |
| T148 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1045069878 |
|
|
Aug 04 04:29:06 PM PDT 24 |
Aug 04 04:29:09 PM PDT 24 |
216715550 ps |
| T980 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3742681452 |
|
|
Aug 04 04:29:18 PM PDT 24 |
Aug 04 04:29:20 PM PDT 24 |
74438103 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2713319112 |
|
|
Aug 04 04:29:10 PM PDT 24 |
Aug 04 04:29:12 PM PDT 24 |
133155145 ps |
| T982 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.884281104 |
|
|
Aug 04 04:29:07 PM PDT 24 |
Aug 04 04:29:08 PM PDT 24 |
290500569 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.231347278 |
|
|
Aug 04 04:29:01 PM PDT 24 |
Aug 04 04:29:02 PM PDT 24 |
40033300 ps |
| T984 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1879566214 |
|
|
Aug 04 04:29:15 PM PDT 24 |
Aug 04 04:29:16 PM PDT 24 |
32524556 ps |
| T985 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1515176396 |
|
|
Aug 04 04:29:44 PM PDT 24 |
Aug 04 04:29:46 PM PDT 24 |
329784128 ps |
| T986 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1260674132 |
|
|
Aug 04 04:29:07 PM PDT 24 |
Aug 04 04:29:11 PM PDT 24 |
4027558193 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1651760026 |
|
|
Aug 04 04:28:58 PM PDT 24 |
Aug 04 04:28:59 PM PDT 24 |
52192654 ps |
| T988 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.712652241 |
|
|
Aug 04 04:29:07 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
45475124 ps |
| T989 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3768388926 |
|
|
Aug 04 04:29:01 PM PDT 24 |
Aug 04 04:29:04 PM PDT 24 |
545621623 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4015831678 |
|
|
Aug 04 04:29:12 PM PDT 24 |
Aug 04 04:29:13 PM PDT 24 |
133160215 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.913602677 |
|
|
Aug 04 04:29:10 PM PDT 24 |
Aug 04 04:29:11 PM PDT 24 |
14601775 ps |
| T113 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3188418381 |
|
|
Aug 04 04:29:07 PM PDT 24 |
Aug 04 04:29:11 PM PDT 24 |
1673123096 ps |
| T992 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1677495679 |
|
|
Aug 04 04:29:03 PM PDT 24 |
Aug 04 04:29:04 PM PDT 24 |
184305827 ps |
| T153 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1581404592 |
|
|
Aug 04 04:29:11 PM PDT 24 |
Aug 04 04:29:13 PM PDT 24 |
404591900 ps |
| T154 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.650725414 |
|
|
Aug 04 04:29:02 PM PDT 24 |
Aug 04 04:29:04 PM PDT 24 |
177574474 ps |
| T993 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3450374197 |
|
|
Aug 04 04:29:31 PM PDT 24 |
Aug 04 04:29:33 PM PDT 24 |
62391807 ps |
| T994 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2352849659 |
|
|
Aug 04 04:29:06 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
35418674 ps |
| T995 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3954514142 |
|
|
Aug 04 04:29:15 PM PDT 24 |
Aug 04 04:29:16 PM PDT 24 |
20717168 ps |
| T996 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3573166745 |
|
|
Aug 04 04:28:59 PM PDT 24 |
Aug 04 04:29:00 PM PDT 24 |
15963656 ps |
| T997 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.846943628 |
|
|
Aug 04 04:29:08 PM PDT 24 |
Aug 04 04:29:12 PM PDT 24 |
395685428 ps |
| T150 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3195344059 |
|
|
Aug 04 04:29:12 PM PDT 24 |
Aug 04 04:29:13 PM PDT 24 |
923105281 ps |
| T998 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.499330957 |
|
|
Aug 04 04:29:12 PM PDT 24 |
Aug 04 04:29:13 PM PDT 24 |
40404492 ps |
| T114 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1490872181 |
|
|
Aug 04 04:29:02 PM PDT 24 |
Aug 04 04:29:03 PM PDT 24 |
15816567 ps |
| T144 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4229476003 |
|
|
Aug 04 04:29:06 PM PDT 24 |
Aug 04 04:29:08 PM PDT 24 |
371015613 ps |
| T151 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2800144225 |
|
|
Aug 04 04:28:56 PM PDT 24 |
Aug 04 04:28:58 PM PDT 24 |
361541290 ps |
| T143 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1266783264 |
|
|
Aug 04 04:29:06 PM PDT 24 |
Aug 04 04:29:08 PM PDT 24 |
225063665 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2071775246 |
|
|
Aug 04 04:29:00 PM PDT 24 |
Aug 04 04:29:01 PM PDT 24 |
52762412 ps |
| T118 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.890201873 |
|
|
Aug 04 04:28:58 PM PDT 24 |
Aug 04 04:28:58 PM PDT 24 |
47670801 ps |
| T1000 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3065189439 |
|
|
Aug 04 04:29:05 PM PDT 24 |
Aug 04 04:29:05 PM PDT 24 |
34374975 ps |
| T1001 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1480733240 |
|
|
Aug 04 04:29:06 PM PDT 24 |
Aug 04 04:29:07 PM PDT 24 |
18340146 ps |
| T115 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2134074370 |
|
|
Aug 04 04:29:10 PM PDT 24 |
Aug 04 04:29:12 PM PDT 24 |
902626744 ps |
| T1002 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2320118788 |
|
|
Aug 04 04:29:11 PM PDT 24 |
Aug 04 04:29:12 PM PDT 24 |
55928294 ps |