Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	141741914	1			T1	6186		T2	4062		T3	3918
instr_valid_dis	112944122	1			T1	6186		T2	4062		T3	3918
instr_en	22170262	1			T27	143490		T22	303924		T50	151232

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10254442	1			T27	98346		T22	268050		T50	71568
sram_ifetch_valid_disable	111477741	1			T1	6186		T2	4062		T3	3918
sram_ifetch_enable	20009731	1			T27	180128		T22	511752		T50	112210

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	141741914	1			T1	6186		T2	4062		T3	3918
hw_debug_en_valid_off	112338522	1			T1	6186		T2	4062		T3	3918
hw_debug_en_on	19086022	1			T27	109260		T21	20038		T22	363922

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111477741	1			T1	6186		T2	4062		T3	3918
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100681030	1			T1	6186		T2	4062		T3	3918
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8285427	1			T27	19054		T22	78088		T50	24150
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3789258	1			T27	43878		T22	143766		T122	15772
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1493960	1			T27	43878		T22	79578		T122	15772
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1898235	1			T22	19090		T57	41258		T126	21900
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4321264	1			T27	8990		T22	58092		T50	35902
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1488646	1			T22	26920		T122	37898		T128	50010
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2063864	1			T22	11172		T50	35902		T122	13164
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6943810	1			T27	19004		T21	20038		T22	108938
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2940842	1			T27	19004		T22	78388		T50	46314
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3146603	1			T22	30550		T50	12612		T122	14840

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9018858	1			T27	104558		T22	129382		T50	55514
lc_exec_en	7820948	1			T27	81266		T22	196892		T50	71732
valid_exec_dis	109066171	1			T1	6186		T2	4062		T3	3918
invalid_exec_dis	30264173	1			T27	278474		T22	779802		T50	183778