Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Total tests in report: 1019

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
69.23	69.23	89.92	89.92	67.77	67.77	89.81	89.81	23.81	23.81	78.02	78.02	93.07	93.07	42.23	42.23	/workspace/coverage/default/15.sram_ctrl_multiple_keys.420863261
89.40	20.17	96.19	6.27	82.70	14.93	93.79	3.99	90.48	66.67	88.89	10.87	95.87	2.80	77.88	35.65	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.65371626
92.90	3.50	97.54	1.36	86.85	4.15	94.14	0.35	100.00	9.52	92.51	3.62	95.87	0.00	83.36	5.48	/workspace/coverage/default/20.sram_ctrl_stress_all.418835358
94.34	1.44	98.73	1.19	87.80	0.95	96.84	2.70	100.00	0.00	94.69	2.17	96.02	0.15	86.29	2.93	/workspace/coverage/default/46.sram_ctrl_executable.1887643035
95.28	0.94	99.07	0.34	89.81	2.01	97.95	1.11	100.00	0.00	96.14	1.45	96.76	0.74	87.20	0.91	/workspace/coverage/default/0.sram_ctrl_sec_cm.2555885124
96.00	0.73	99.07	0.00	90.17	0.36	97.95	0.00	100.00	0.00	96.14	0.00	96.76	0.00	91.96	4.75	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3882146738
96.31	0.31	99.07	0.00	90.17	0.00	97.95	0.00	100.00	0.00	96.14	0.00	96.90	0.15	93.97	2.01	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3496023790
96.57	0.26	99.07	0.00	90.40	0.24	98.02	0.07	100.00	0.00	96.14	0.00	98.23	1.33	94.15	0.18	/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.554072097
96.76	0.19	99.07	0.00	90.64	0.24	98.02	0.00	100.00	0.00	96.14	0.00	98.23	0.00	95.25	1.10	/workspace/coverage/default/10.sram_ctrl_stress_all.574221337
96.92	0.15	99.07	0.00	90.64	0.00	98.02	0.00	100.00	0.00	96.14	0.00	99.12	0.88	95.43	0.18	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3193006195
97.05	0.14	99.15	0.08	90.64	0.00	98.89	0.87	100.00	0.00	96.14	0.00	99.12	0.00	95.43	0.00	/workspace/coverage/default/17.sram_ctrl_ram_cfg.4197226556
97.18	0.13	99.15	0.00	90.64	0.00	99.41	0.52	100.00	0.00	96.14	0.00	99.12	0.00	95.80	0.37	/workspace/coverage/default/5.sram_ctrl_lc_escalation.3756321634
97.28	0.10	99.15	0.00	90.64	0.00	99.41	0.00	100.00	0.00	96.14	0.00	99.12	0.00	96.53	0.73	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.627386626
97.35	0.07	99.15	0.00	91.00	0.36	99.51	0.10	100.00	0.00	96.14	0.00	99.12	0.00	96.53	0.00	/workspace/coverage/default/24.sram_ctrl_alert_test.4148786274
97.40	0.05	99.15	0.00	91.00	0.00	99.51	0.00	100.00	0.00	96.14	0.00	99.12	0.00	96.89	0.37	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3151272259
97.45	0.05	99.15	0.00	91.00	0.00	99.65	0.14	100.00	0.00	96.14	0.00	99.12	0.00	97.07	0.18	/workspace/coverage/default/37.sram_ctrl_regwen.1124988197
97.47	0.03	99.15	0.00	91.00	0.00	99.65	0.00	100.00	0.00	96.14	0.00	99.12	0.00	97.26	0.18	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1140888101
97.50	0.03	99.15	0.00	91.00	0.00	99.65	0.00	100.00	0.00	96.14	0.00	99.12	0.00	97.44	0.18	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1601707823
97.51	0.01	99.15	0.00	91.00	0.00	99.72	0.07	100.00	0.00	96.14	0.00	99.12	0.00	97.44	0.00	/workspace/coverage/default/16.sram_ctrl_stress_all.2513025377

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.846465533
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.780137724
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1161546152
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4110681674
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.299215942
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4100618022
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3123777790
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2012123309
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.230232729
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2278992702
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3598017950
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1266289374
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1179101835
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4051272087
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1917368051
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.872415008
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.969733103
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1858162153
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1230709263
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3917665932
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.934414784
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3073688452
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1551034587
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1116993373
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.595748420
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.920147311
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.718024563
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.981643320
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2484313960
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1887183195
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3915902730
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.594520142
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.461892215
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.668320800
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3496232970
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3782165106
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1006328981
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1472432187
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.300004708
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4279533411
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3633820644
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3573064210
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3678122234
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3747022872
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3514994902
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2135011480
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.887488225
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2762409426
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.415622776
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1796728268
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4150063210
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4263491979
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.433458497
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1182043039
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.314129836
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.345247000
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3567078425
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1122889878
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1804957444
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1971067771
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1606540741
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.607094710
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.277808941
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3322384277
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.766601148
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1911445998
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3762246915
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.192730233
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2293825689
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.121283525
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2637354033
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3629704483
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1874977756
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.609561200
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4058235625
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1769789704
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.165271296
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2978208962
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3902335958
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.917571353
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.690973172
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1443191403
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2211553813
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4214650887
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3743318162
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1068152336
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.334563326
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.795023373
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.820117466
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1414597673
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2213937720
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3697461309
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2075506980
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.498686504
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3680711985
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2419309542
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.208486492
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2558008791
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.322479945
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.206887026
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1036016312
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.125851867
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1830954139
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3999833051
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2244564586
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2123722838
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3639339960
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3752113606
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2975550107
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4089905597
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.335386524
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2770717904
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1244814393
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4220892462
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1989076874
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2498226330
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4140067306
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2116618514
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3918428993
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1156691602
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2913182561
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2654468231
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1251473237
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2231388462
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.232189080
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3306856826
/workspace/coverage/default/0.sram_ctrl_alert_test.4078534802
/workspace/coverage/default/0.sram_ctrl_bijection.1877360619
/workspace/coverage/default/0.sram_ctrl_executable.4132516975
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2471150875
/workspace/coverage/default/0.sram_ctrl_max_throughput.2715094343
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1995438493
/workspace/coverage/default/0.sram_ctrl_mem_walk.1352865747
/workspace/coverage/default/0.sram_ctrl_multiple_keys.4272807767
/workspace/coverage/default/0.sram_ctrl_partial_access.3205307150
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1887795338
/workspace/coverage/default/0.sram_ctrl_ram_cfg.325281891
/workspace/coverage/default/0.sram_ctrl_regwen.1958700654
/workspace/coverage/default/0.sram_ctrl_smoke.4196823080
/workspace/coverage/default/0.sram_ctrl_stress_all.2670304253
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3631886770
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1997626207
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1449901476
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3019695961
/workspace/coverage/default/1.sram_ctrl_alert_test.4267239917
/workspace/coverage/default/1.sram_ctrl_bijection.1319523918
/workspace/coverage/default/1.sram_ctrl_executable.3488978941
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3524929639
/workspace/coverage/default/1.sram_ctrl_max_throughput.3007996337
/workspace/coverage/default/1.sram_ctrl_mem_walk.636966051
/workspace/coverage/default/1.sram_ctrl_multiple_keys.33995610
/workspace/coverage/default/1.sram_ctrl_partial_access.2495179919
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3899317341
/workspace/coverage/default/1.sram_ctrl_ram_cfg.4132859144
/workspace/coverage/default/1.sram_ctrl_regwen.3225435567
/workspace/coverage/default/1.sram_ctrl_sec_cm.1437909108
/workspace/coverage/default/1.sram_ctrl_smoke.2901810129
/workspace/coverage/default/1.sram_ctrl_stress_all.934304603
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1528410765
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3793125642
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1653911937
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.729910070
/workspace/coverage/default/10.sram_ctrl_alert_test.2273040991
/workspace/coverage/default/10.sram_ctrl_bijection.2688361611
/workspace/coverage/default/10.sram_ctrl_executable.650187130
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3660322482
/workspace/coverage/default/10.sram_ctrl_max_throughput.3257753702
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.862715109
/workspace/coverage/default/10.sram_ctrl_mem_walk.1229088765
/workspace/coverage/default/10.sram_ctrl_multiple_keys.662190505
/workspace/coverage/default/10.sram_ctrl_partial_access.986562180
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1525704608
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3152173298
/workspace/coverage/default/10.sram_ctrl_regwen.1788261520
/workspace/coverage/default/10.sram_ctrl_smoke.2187341449
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2791023506
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2576272319
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2791892819
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2890204933
/workspace/coverage/default/11.sram_ctrl_alert_test.2081565956
/workspace/coverage/default/11.sram_ctrl_bijection.2700579169
/workspace/coverage/default/11.sram_ctrl_executable.3808204277
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1300630763
/workspace/coverage/default/11.sram_ctrl_max_throughput.2951319582
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.369081001
/workspace/coverage/default/11.sram_ctrl_mem_walk.3416909143
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2660205186
/workspace/coverage/default/11.sram_ctrl_partial_access.1226615347
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2323028318
/workspace/coverage/default/11.sram_ctrl_regwen.1655496670
/workspace/coverage/default/11.sram_ctrl_smoke.586491032
/workspace/coverage/default/11.sram_ctrl_stress_all.1196540947
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4021936209
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1780313364
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3220643427
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/workspace/coverage/default/43.sram_ctrl_alert_test.2174104415
/workspace/coverage/default/43.sram_ctrl_bijection.150605940
/workspace/coverage/default/43.sram_ctrl_executable.4032600691
/workspace/coverage/default/43.sram_ctrl_lc_escalation.4199851913
/workspace/coverage/default/43.sram_ctrl_max_throughput.2028738267
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1051748508
/workspace/coverage/default/43.sram_ctrl_mem_walk.3403165669
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2605213770
/workspace/coverage/default/43.sram_ctrl_partial_access.3473921283
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3270538171
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3101375019
/workspace/coverage/default/43.sram_ctrl_regwen.1550186320
/workspace/coverage/default/43.sram_ctrl_smoke.2236066163
/workspace/coverage/default/43.sram_ctrl_stress_all.3250434569
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3074265652
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1461874957
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3617309179
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.286895702
/workspace/coverage/default/44.sram_ctrl_alert_test.886019788
/workspace/coverage/default/44.sram_ctrl_bijection.2065564156
/workspace/coverage/default/44.sram_ctrl_executable.704484447
/workspace/coverage/default/44.sram_ctrl_lc_escalation.521231197
/workspace/coverage/default/44.sram_ctrl_max_throughput.3285021353
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.606004555
/workspace/coverage/default/44.sram_ctrl_mem_walk.4140473240
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3729744686
/workspace/coverage/default/44.sram_ctrl_partial_access.4063573540
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2103630886
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2018282318
/workspace/coverage/default/44.sram_ctrl_regwen.534382047
/workspace/coverage/default/44.sram_ctrl_smoke.467848454
/workspace/coverage/default/44.sram_ctrl_stress_all.1531076478
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1760279888
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3300284280
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1246494527
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1187178584
/workspace/coverage/default/45.sram_ctrl_alert_test.2575286849
/workspace/coverage/default/45.sram_ctrl_bijection.3009619089
/workspace/coverage/default/45.sram_ctrl_executable.1498070126
/workspace/coverage/default/45.sram_ctrl_lc_escalation.545787804
/workspace/coverage/default/45.sram_ctrl_max_throughput.4134593942
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.130789235
/workspace/coverage/default/45.sram_ctrl_mem_walk.854377842
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3927816174
/workspace/coverage/default/45.sram_ctrl_partial_access.676958290
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.556687781
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1700021224
/workspace/coverage/default/45.sram_ctrl_regwen.2684618279
/workspace/coverage/default/45.sram_ctrl_smoke.1865021134
/workspace/coverage/default/45.sram_ctrl_stress_all.558688081
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.646712592
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2556316579
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3226407259
/workspace/coverage/default/46.sram_ctrl_alert_test.60284375
/workspace/coverage/default/46.sram_ctrl_bijection.1080490374
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2308525418
/workspace/coverage/default/46.sram_ctrl_max_throughput.3690408774
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3689412797
/workspace/coverage/default/46.sram_ctrl_mem_walk.513277461
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1573930564
/workspace/coverage/default/46.sram_ctrl_partial_access.1975337873
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1314029178
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1955304830
/workspace/coverage/default/46.sram_ctrl_regwen.2022475463
/workspace/coverage/default/46.sram_ctrl_smoke.2642483561
/workspace/coverage/default/46.sram_ctrl_stress_all.490415874
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4111720950
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1617299219
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.206400819
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1367860444
/workspace/coverage/default/47.sram_ctrl_alert_test.3715942148
/workspace/coverage/default/47.sram_ctrl_bijection.1995287102
/workspace/coverage/default/47.sram_ctrl_executable.563424071
/workspace/coverage/default/47.sram_ctrl_lc_escalation.872182808
/workspace/coverage/default/47.sram_ctrl_max_throughput.22646564
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1927878640
/workspace/coverage/default/47.sram_ctrl_mem_walk.4192003388
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1333207215
/workspace/coverage/default/47.sram_ctrl_partial_access.2237193486
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3854541638
/workspace/coverage/default/47.sram_ctrl_ram_cfg.622961935
/workspace/coverage/default/47.sram_ctrl_regwen.3023715051
/workspace/coverage/default/47.sram_ctrl_smoke.214222221
/workspace/coverage/default/47.sram_ctrl_stress_all.1812070952
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.4008161588
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.810269930
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1144996293
/workspace/coverage/default/48.sram_ctrl_alert_test.2719684139
/workspace/coverage/default/48.sram_ctrl_bijection.1268600666
/workspace/coverage/default/48.sram_ctrl_executable.2975069459
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3532750582
/workspace/coverage/default/48.sram_ctrl_max_throughput.3474640979
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1629347472
/workspace/coverage/default/48.sram_ctrl_mem_walk.4080278021
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3401193623
/workspace/coverage/default/48.sram_ctrl_partial_access.2658285024
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1991757211
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1167684173
/workspace/coverage/default/48.sram_ctrl_regwen.2589145460
/workspace/coverage/default/48.sram_ctrl_smoke.3807850677
/workspace/coverage/default/48.sram_ctrl_stress_all.730410278
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1336604803
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1457073193
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.51888938
/workspace/coverage/default/49.sram_ctrl_alert_test.3788962741
/workspace/coverage/default/49.sram_ctrl_bijection.2397694969
/workspace/coverage/default/49.sram_ctrl_executable.3495350061
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2917828821
/workspace/coverage/default/49.sram_ctrl_max_throughput.983596868
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1350654847
/workspace/coverage/default/49.sram_ctrl_mem_walk.2450316469
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1391099562
/workspace/coverage/default/49.sram_ctrl_partial_access.1824947640
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2701947616
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1740705911
/workspace/coverage/default/49.sram_ctrl_regwen.1782937367
/workspace/coverage/default/49.sram_ctrl_smoke.2952902027
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1715558436
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1179155183
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.953128461
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.224101532
/workspace/coverage/default/5.sram_ctrl_alert_test.4082889789
/workspace/coverage/default/5.sram_ctrl_bijection.3157716289
/workspace/coverage/default/5.sram_ctrl_executable.2411658833
/workspace/coverage/default/5.sram_ctrl_max_throughput.3089797110
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2528126749
/workspace/coverage/default/5.sram_ctrl_mem_walk.2481879686
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1592790755
/workspace/coverage/default/5.sram_ctrl_partial_access.862334138
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.253079527
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2120965192
/workspace/coverage/default/5.sram_ctrl_regwen.1630701108
/workspace/coverage/default/5.sram_ctrl_smoke.1574005461
/workspace/coverage/default/5.sram_ctrl_stress_all.2802346275
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1964498636
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1102998319
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3437766583
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2541182199
/workspace/coverage/default/6.sram_ctrl_alert_test.3597392847
/workspace/coverage/default/6.sram_ctrl_bijection.2713397412
/workspace/coverage/default/6.sram_ctrl_executable.3497268331
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1969491685
/workspace/coverage/default/6.sram_ctrl_max_throughput.4194702971
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.348611236
/workspace/coverage/default/6.sram_ctrl_mem_walk.1886556648
/workspace/coverage/default/6.sram_ctrl_multiple_keys.970032568
/workspace/coverage/default/6.sram_ctrl_partial_access.2241996797
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2382055609
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1281381882
/workspace/coverage/default/6.sram_ctrl_regwen.4196497094
/workspace/coverage/default/6.sram_ctrl_smoke.2356217147
/workspace/coverage/default/6.sram_ctrl_stress_all.1461357315
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1200764282
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1025520544
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2247403725
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1108194823
/workspace/coverage/default/7.sram_ctrl_alert_test.1968372831
/workspace/coverage/default/7.sram_ctrl_bijection.2870771776
/workspace/coverage/default/7.sram_ctrl_executable.1038279381
/workspace/coverage/default/7.sram_ctrl_lc_escalation.99086326
/workspace/coverage/default/7.sram_ctrl_max_throughput.2571519161
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2984453197
/workspace/coverage/default/7.sram_ctrl_mem_walk.1525192421
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1284838276
/workspace/coverage/default/7.sram_ctrl_partial_access.700441904
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3790717711
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2946563195
/workspace/coverage/default/7.sram_ctrl_regwen.3000327361
/workspace/coverage/default/7.sram_ctrl_smoke.1496156344
/workspace/coverage/default/7.sram_ctrl_stress_all.226857066
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2557680270
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.471097243
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.953308834
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.4278936078
/workspace/coverage/default/8.sram_ctrl_alert_test.2327577113
/workspace/coverage/default/8.sram_ctrl_bijection.4093246095
/workspace/coverage/default/8.sram_ctrl_executable.3450405650
/workspace/coverage/default/8.sram_ctrl_lc_escalation.538542685
/workspace/coverage/default/8.sram_ctrl_max_throughput.1631902306
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2701375784
/workspace/coverage/default/8.sram_ctrl_mem_walk.3277955144
/workspace/coverage/default/8.sram_ctrl_multiple_keys.558205795
/workspace/coverage/default/8.sram_ctrl_partial_access.3768195576
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3258359522
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1309068125
/workspace/coverage/default/8.sram_ctrl_regwen.1372432510
/workspace/coverage/default/8.sram_ctrl_smoke.4278952866
/workspace/coverage/default/8.sram_ctrl_stress_all.3130757148
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.989103870
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3607568904
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2845463663
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.353128715
/workspace/coverage/default/9.sram_ctrl_alert_test.2060534802
/workspace/coverage/default/9.sram_ctrl_bijection.718253499
/workspace/coverage/default/9.sram_ctrl_executable.1111635824
/workspace/coverage/default/9.sram_ctrl_lc_escalation.383946640
/workspace/coverage/default/9.sram_ctrl_max_throughput.2361544333
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2730043786
/workspace/coverage/default/9.sram_ctrl_mem_walk.3719340137
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2046374084
/workspace/coverage/default/9.sram_ctrl_partial_access.2049914445
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.508020450
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1718096432
/workspace/coverage/default/9.sram_ctrl_regwen.2266403664
/workspace/coverage/default/9.sram_ctrl_smoke.74353973
/workspace/coverage/default/9.sram_ctrl_stress_all.332428255
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3931436030
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1468770069
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1294852129

Total test records in report: 1019

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/6.sram_ctrl_max_throughput.4194702971	Aug 05 05:50:07 PM PDT 24	Aug 05 05:50:19 PM PDT 24	70826555 ps
T2	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3444660415	Aug 05 05:52:22 PM PDT 24	Aug 05 05:52:27 PM PDT 24	613385717 ps
T3	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.348611236	Aug 05 05:49:55 PM PDT 24	Aug 05 05:50:01 PM PDT 24	179944173 ps
T4	/workspace/coverage/default/19.sram_ctrl_multiple_keys.3088890220	Aug 05 05:50:49 PM PDT 24	Aug 05 05:53:12 PM PDT 24	12489338312 ps
T9	/workspace/coverage/default/20.sram_ctrl_ram_cfg.2349591650	Aug 05 05:50:38 PM PDT 24	Aug 05 05:50:39 PM PDT 24	88180064 ps
T10	/workspace/coverage/default/45.sram_ctrl_max_throughput.4134593942	Aug 05 05:52:56 PM PDT 24	Aug 05 05:54:40 PM PDT 24	127895311 ps
T11	/workspace/coverage/default/18.sram_ctrl_smoke.596033356	Aug 05 05:50:38 PM PDT 24	Aug 05 05:50:49 PM PDT 24	700727684 ps
T12	/workspace/coverage/default/44.sram_ctrl_smoke.467848454	Aug 05 05:52:44 PM PDT 24	Aug 05 05:52:53 PM PDT 24	697962178 ps
T13	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.357163204	Aug 05 05:50:33 PM PDT 24	Aug 05 05:50:37 PM PDT 24	143463589 ps
T14	/workspace/coverage/default/15.sram_ctrl_multiple_keys.420863261	Aug 05 05:50:21 PM PDT 24	Aug 05 06:00:42 PM PDT 24	9692384240 ps
T8	/workspace/coverage/default/0.sram_ctrl_sec_cm.2555885124	Aug 05 05:50:01 PM PDT 24	Aug 05 05:50:04 PM PDT 24	974023035 ps
T27	/workspace/coverage/default/46.sram_ctrl_executable.1887643035	Aug 05 05:53:01 PM PDT 24	Aug 05 06:05:36 PM PDT 24	3563561507 ps
T34	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3122583259	Aug 05 05:50:18 PM PDT 24	Aug 05 05:54:02 PM PDT 24	2228506631 ps
T29	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2407936449	Aug 05 05:51:24 PM PDT 24	Aug 05 06:08:17 PM PDT 24	7374640044 ps
T28	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2240753139	Aug 05 05:52:16 PM PDT 24	Aug 05 05:54:31 PM PDT 24	618132115 ps
T35	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.471097243	Aug 05 05:50:07 PM PDT 24	Aug 05 05:52:34 PM PDT 24	1560991864 ps
T36	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.4186296852	Aug 05 05:50:31 PM PDT 24	Aug 05 05:52:55 PM PDT 24	146853020 ps
T5	/workspace/coverage/default/29.sram_ctrl_lc_escalation.1035908538	Aug 05 05:51:18 PM PDT 24	Aug 05 05:51:29 PM PDT 24	2103602868 ps
T26	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.65371626	Aug 05 05:50:46 PM PDT 24	Aug 05 05:51:15 PM PDT 24	927602793 ps
T6	/workspace/coverage/default/49.sram_ctrl_lc_escalation.2917828821	Aug 05 05:53:32 PM PDT 24	Aug 05 05:53:35 PM PDT 24	308189249 ps
T21	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2557680270	Aug 05 05:50:11 PM PDT 24	Aug 05 05:55:22 PM PDT 24	2903571691 ps
T37	/workspace/coverage/default/23.sram_ctrl_access_during_key_req.2685411303	Aug 05 05:50:49 PM PDT 24	Aug 05 06:09:20 PM PDT 24	5377716982 ps
T61	/workspace/coverage/default/36.sram_ctrl_bijection.3311957307	Aug 05 05:51:46 PM PDT 24	Aug 05 05:52:47 PM PDT 24	919488925 ps
T22	/workspace/coverage/default/10.sram_ctrl_stress_all.574221337	Aug 05 05:50:09 PM PDT 24	Aug 05 07:05:25 PM PDT 24	258493086779 ps
T50	/workspace/coverage/default/9.sram_ctrl_regwen.2266403664	Aug 05 05:50:11 PM PDT 24	Aug 05 06:07:25 PM PDT 24	10750240042 ps
T7	/workspace/coverage/default/30.sram_ctrl_stress_all.2971644739	Aug 05 05:51:26 PM PDT 24	Aug 05 06:14:20 PM PDT 24	16093633023 ps
T52	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1412662388	Aug 05 05:49:57 PM PDT 24	Aug 05 05:50:37 PM PDT 24	439032537 ps
T62	/workspace/coverage/default/47.sram_ctrl_partial_access.2237193486	Aug 05 05:53:11 PM PDT 24	Aug 05 05:53:23 PM PDT 24	229439230 ps
T91	/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1993461895	Aug 05 05:49:54 PM PDT 24	Aug 05 05:54:19 PM PDT 24	10921858558 ps
T92	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3496023790	Aug 05 05:50:11 PM PDT 24	Aug 05 05:53:14 PM PDT 24	15994274205 ps
T134	/workspace/coverage/default/16.sram_ctrl_smoke.2460275479	Aug 05 05:50:35 PM PDT 24	Aug 05 05:52:38 PM PDT 24	4946082247 ps
T30	/workspace/coverage/default/40.sram_ctrl_ram_cfg.3340088266	Aug 05 05:52:20 PM PDT 24	Aug 05 05:52:21 PM PDT 24	37156153 ps
T122	/workspace/coverage/default/25.sram_ctrl_executable.3288021539	Aug 05 05:50:54 PM PDT 24	Aug 05 06:13:46 PM PDT 24	20118837141 ps
T137	/workspace/coverage/default/25.sram_ctrl_max_throughput.2074641138	Aug 05 05:50:56 PM PDT 24	Aug 05 05:51:46 PM PDT 24	106393113 ps
T53	/workspace/coverage/default/30.sram_ctrl_partial_access.1254107797	Aug 05 05:51:18 PM PDT 24	Aug 05 05:51:20 PM PDT 24	295059736 ps
T76	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3193006195	Aug 05 05:50:06 PM PDT 24	Aug 05 05:50:09 PM PDT 24	100851308 ps
T19	/workspace/coverage/default/2.sram_ctrl_sec_cm.2829531387	Aug 05 05:50:01 PM PDT 24	Aug 05 05:50:04 PM PDT 24	769654047 ps
T133	/workspace/coverage/default/40.sram_ctrl_multiple_keys.3340906985	Aug 05 05:52:14 PM PDT 24	Aug 05 05:55:55 PM PDT 24	803192362 ps
T51	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1426663592	Aug 05 05:50:46 PM PDT 24	Aug 05 05:52:41 PM PDT 24	282256497 ps
T138	/workspace/coverage/default/46.sram_ctrl_max_throughput.3690408774	Aug 05 05:53:00 PM PDT 24	Aug 05 05:53:06 PM PDT 24	78484229 ps
T93	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2918566715	Aug 05 05:50:49 PM PDT 24	Aug 05 05:55:37 PM PDT 24	11690752347 ps
T40	/workspace/coverage/default/2.sram_ctrl_mem_walk.25496340	Aug 05 05:50:03 PM PDT 24	Aug 05 05:50:09 PM PDT 24	683424722 ps
T132	/workspace/coverage/default/38.sram_ctrl_multiple_keys.2493975849	Aug 05 05:51:59 PM PDT 24	Aug 05 06:03:29 PM PDT 24	34554567420 ps
T57	/workspace/coverage/default/6.sram_ctrl_regwen.4196497094	Aug 05 05:50:06 PM PDT 24	Aug 05 06:04:28 PM PDT 24	158817983439 ps
T139	/workspace/coverage/default/18.sram_ctrl_max_throughput.4228889691	Aug 05 05:50:34 PM PDT 24	Aug 05 05:50:55 PM PDT 24	103470959 ps
T15	/workspace/coverage/default/14.sram_ctrl_alert_test.2348978474	Aug 05 05:50:40 PM PDT 24	Aug 05 05:50:41 PM PDT 24	37913693 ps
T41	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.4213351114	Aug 05 05:50:13 PM PDT 24	Aug 05 05:50:19 PM PDT 24	762338021 ps
T42	/workspace/coverage/default/5.sram_ctrl_mem_walk.2481879686	Aug 05 05:49:58 PM PDT 24	Aug 05 05:50:04 PM PDT 24	236918197 ps
T130	/workspace/coverage/default/34.sram_ctrl_partial_access.1509961610	Aug 05 05:51:35 PM PDT 24	Aug 05 05:52:16 PM PDT 24	143913524 ps
T127	/workspace/coverage/default/37.sram_ctrl_multiple_keys.301730005	Aug 05 05:51:50 PM PDT 24	Aug 05 05:54:56 PM PDT 24	8636534075 ps
T94	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1697007404	Aug 05 05:50:48 PM PDT 24	Aug 05 05:55:38 PM PDT 24	48633953395 ps
T140	/workspace/coverage/default/0.sram_ctrl_smoke.4196823080	Aug 05 05:49:39 PM PDT 24	Aug 05 05:49:52 PM PDT 24	498608347 ps
T38	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1108194823	Aug 05 05:50:18 PM PDT 24	Aug 05 05:54:53 PM PDT 24	1034982497 ps
T24	/workspace/coverage/default/5.sram_ctrl_lc_escalation.3756321634	Aug 05 05:50:04 PM PDT 24	Aug 05 05:50:10 PM PDT 24	1244871101 ps
T95	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1025520544	Aug 05 05:50:09 PM PDT 24	Aug 05 05:53:15 PM PDT 24	2004032903 ps
T31	/workspace/coverage/default/15.sram_ctrl_ram_cfg.1709871162	Aug 05 05:50:46 PM PDT 24	Aug 05 05:50:47 PM PDT 24	41396413 ps
T141	/workspace/coverage/default/43.sram_ctrl_ram_cfg.3101375019	Aug 05 05:52:44 PM PDT 24	Aug 05 05:52:45 PM PDT 24	77420428 ps
T125	/workspace/coverage/default/9.sram_ctrl_executable.1111635824	Aug 05 05:50:05 PM PDT 24	Aug 05 06:08:53 PM PDT 24	3102311637 ps
T142	/workspace/coverage/default/47.sram_ctrl_smoke.214222221	Aug 05 05:53:05 PM PDT 24	Aug 05 05:53:14 PM PDT 24	420878252 ps
T16	/workspace/coverage/default/7.sram_ctrl_alert_test.1968372831	Aug 05 05:50:16 PM PDT 24	Aug 05 05:50:17 PM PDT 24	48633405 ps
T96	/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1887795338	Aug 05 05:49:53 PM PDT 24	Aug 05 05:56:50 PM PDT 24	11311564625 ps
T143	/workspace/coverage/default/23.sram_ctrl_max_throughput.1499221332	Aug 05 05:50:54 PM PDT 24	Aug 05 05:50:58 PM PDT 24	50195548 ps
T135	/workspace/coverage/default/18.sram_ctrl_multiple_keys.2863154018	Aug 05 05:50:38 PM PDT 24	Aug 05 06:10:17 PM PDT 24	3216414156 ps
T97	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1920113835	Aug 05 05:50:31 PM PDT 24	Aug 05 05:55:02 PM PDT 24	2788488532 ps
T23	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2866881763	Aug 05 05:50:31 PM PDT 24	Aug 05 05:51:16 PM PDT 24	18371113697 ps
T63	/workspace/coverage/default/19.sram_ctrl_regwen.1262319754	Aug 05 05:50:37 PM PDT 24	Aug 05 05:57:09 PM PDT 24	369228950 ps
T144	/workspace/coverage/default/16.sram_ctrl_partial_access.630970840	Aug 05 05:50:33 PM PDT 24	Aug 05 05:51:06 PM PDT 24	493918668 ps
T145	/workspace/coverage/default/4.sram_ctrl_partial_access.3441813808	Aug 05 05:50:06 PM PDT 24	Aug 05 05:50:15 PM PDT 24	72620536 ps
T43	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2258906899	Aug 05 05:51:05 PM PDT 24	Aug 05 05:52:07 PM PDT 24	6338719757 ps
T17	/workspace/coverage/default/30.sram_ctrl_alert_test.3579921124	Aug 05 05:51:23 PM PDT 24	Aug 05 05:51:24 PM PDT 24	15321752 ps
T126	/workspace/coverage/default/30.sram_ctrl_regwen.2643546511	Aug 05 05:51:24 PM PDT 24	Aug 05 06:06:35 PM PDT 24	75938258339 ps
T146	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2845463663	Aug 05 05:50:12 PM PDT 24	Aug 05 05:50:13 PM PDT 24	38561479 ps
T147	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3265771320	Aug 05 05:51:28 PM PDT 24	Aug 05 05:51:29 PM PDT 24	535225050 ps
T136	/workspace/coverage/default/42.sram_ctrl_bijection.349314334	Aug 05 05:52:25 PM PDT 24	Aug 05 05:53:24 PM PDT 24	960068414 ps
T148	/workspace/coverage/default/44.sram_ctrl_regwen.534382047	Aug 05 05:52:56 PM PDT 24	Aug 05 06:00:30 PM PDT 24	12152175271 ps
T149	/workspace/coverage/default/12.sram_ctrl_max_throughput.1939960176	Aug 05 05:50:23 PM PDT 24	Aug 05 05:51:49 PM PDT 24	471225333 ps
T39	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1760279888	Aug 05 05:52:50 PM PDT 24	Aug 05 05:54:23 PM PDT 24	2267637119 ps
T150	/workspace/coverage/default/11.sram_ctrl_multiple_keys.2660205186	Aug 05 05:50:13 PM PDT 24	Aug 05 06:02:50 PM PDT 24	2662765025 ps
T151	/workspace/coverage/default/33.sram_ctrl_smoke.3750203782	Aug 05 05:51:28 PM PDT 24	Aug 05 05:51:48 PM PDT 24	9080861432 ps
T25	/workspace/coverage/default/20.sram_ctrl_stress_all.418835358	Aug 05 05:50:40 PM PDT 24	Aug 05 06:34:40 PM PDT 24	28986171696 ps
T128	/workspace/coverage/default/49.sram_ctrl_executable.3495350061	Aug 05 05:53:33 PM PDT 24	Aug 05 06:03:55 PM PDT 24	36344161033 ps
T129	/workspace/coverage/default/26.sram_ctrl_lc_escalation.1548739845	Aug 05 05:50:57 PM PDT 24	Aug 05 05:51:04 PM PDT 24	440899672 ps
T152	/workspace/coverage/default/20.sram_ctrl_lc_escalation.3477979939	Aug 05 05:50:36 PM PDT 24	Aug 05 05:50:38 PM PDT 24	80363081 ps
T153	/workspace/coverage/default/43.sram_ctrl_lc_escalation.4199851913	Aug 05 05:52:44 PM PDT 24	Aug 05 05:52:51 PM PDT 24	1341702140 ps
T154	/workspace/coverage/default/47.sram_ctrl_stress_all.1812070952	Aug 05 05:53:18 PM PDT 24	Aug 05 06:23:50 PM PDT 24	5166103073 ps
T155	/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.953128461	Aug 05 05:53:32 PM PDT 24	Aug 05 05:53:35 PM PDT 24	87236892 ps
T107	/workspace/coverage/default/27.sram_ctrl_stress_all.2574673284	Aug 05 05:51:09 PM PDT 24	Aug 05 06:02:28 PM PDT 24	145315078695 ps
T156	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.953308834	Aug 05 05:50:07 PM PDT 24	Aug 05 05:50:48 PM PDT 24	1553732354 ps
T157	/workspace/coverage/default/1.sram_ctrl_smoke.2901810129	Aug 05 05:49:53 PM PDT 24	Aug 05 05:50:08 PM PDT 24	863670730 ps
T158	/workspace/coverage/default/39.sram_ctrl_multiple_keys.4199435415	Aug 05 05:52:06 PM PDT 24	Aug 05 05:58:53 PM PDT 24	1347914100 ps
T159	/workspace/coverage/default/40.sram_ctrl_regwen.3885217320	Aug 05 05:52:21 PM PDT 24	Aug 05 06:00:45 PM PDT 24	3469789292 ps
T131	/workspace/coverage/default/29.sram_ctrl_stress_all.1888529053	Aug 05 05:51:17 PM PDT 24	Aug 05 06:15:25 PM PDT 24	23401799138 ps
T160	/workspace/coverage/default/33.sram_ctrl_regwen.3922460876	Aug 05 05:51:34 PM PDT 24	Aug 05 06:10:25 PM PDT 24	5692634832 ps
T98	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.369278691	Aug 05 05:52:32 PM PDT 24	Aug 05 06:03:33 PM PDT 24	25797143277 ps
T161	/workspace/coverage/default/17.sram_ctrl_max_throughput.2306644059	Aug 05 05:50:35 PM PDT 24	Aug 05 05:50:42 PM PDT 24	1002011881 ps
T162	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1461874957	Aug 05 05:52:42 PM PDT 24	Aug 05 05:57:41 PM PDT 24	11892826141 ps
T163	/workspace/coverage/default/2.sram_ctrl_ram_cfg.2720709805	Aug 05 05:49:49 PM PDT 24	Aug 05 05:49:50 PM PDT 24	100290647 ps
T164	/workspace/coverage/default/18.sram_ctrl_bijection.1106418577	Aug 05 05:50:28 PM PDT 24	Aug 05 05:51:01 PM PDT 24	7863382437 ps
T44	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3631886770	Aug 05 05:50:06 PM PDT 24	Aug 05 05:57:08 PM PDT 24	1549598751 ps
T18	/workspace/coverage/default/11.sram_ctrl_alert_test.2081565956	Aug 05 05:50:13 PM PDT 24	Aug 05 05:50:14 PM PDT 24	16168028 ps
T165	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1566088170	Aug 05 05:51:38 PM PDT 24	Aug 05 05:52:55 PM PDT 24	536164496 ps
T166	/workspace/coverage/default/20.sram_ctrl_multiple_keys.4116289701	Aug 05 05:50:36 PM PDT 24	Aug 05 06:03:19 PM PDT 24	10080786874 ps
T167	/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3854541638	Aug 05 05:53:10 PM PDT 24	Aug 05 05:58:39 PM PDT 24	9006918466 ps
T168	/workspace/coverage/default/45.sram_ctrl_lc_escalation.545787804	Aug 05 05:52:56 PM PDT 24	Aug 05 05:53:04 PM PDT 24	1033468937 ps
T169	/workspace/coverage/default/17.sram_ctrl_regwen.1360766772	Aug 05 05:50:38 PM PDT 24	Aug 05 06:06:19 PM PDT 24	47097901120 ps
T170	/workspace/coverage/default/34.sram_ctrl_smoke.2139884481	Aug 05 05:51:39 PM PDT 24	Aug 05 05:51:46 PM PDT 24	422824520 ps
T171	/workspace/coverage/default/15.sram_ctrl_bijection.1614586941	Aug 05 05:50:30 PM PDT 24	Aug 05 05:51:05 PM PDT 24	1630112057 ps
T172	/workspace/coverage/default/1.sram_ctrl_multiple_keys.33995610	Aug 05 05:49:48 PM PDT 24	Aug 05 06:06:00 PM PDT 24	4357964257 ps
T77	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1688611464	Aug 05 05:52:22 PM PDT 24	Aug 05 06:10:43 PM PDT 24	2873980303 ps
T173	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1873625537	Aug 05 05:51:32 PM PDT 24	Aug 05 05:53:09 PM PDT 24	3648780834 ps
T78	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3556521929	Aug 05 05:50:21 PM PDT 24	Aug 05 06:04:22 PM PDT 24	5421037358 ps
T174	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.353128715	Aug 05 05:50:07 PM PDT 24	Aug 05 05:59:49 PM PDT 24	2893640583 ps
T175	/workspace/coverage/default/49.sram_ctrl_bijection.2397694969	Aug 05 05:53:26 PM PDT 24	Aug 05 05:54:08 PM PDT 24	674792739 ps
T176	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.2131506957	Aug 05 05:51:12 PM PDT 24	Aug 05 05:56:18 PM PDT 24	2987900569 ps
T177	/workspace/coverage/default/36.sram_ctrl_multiple_keys.111665127	Aug 05 05:51:47 PM PDT 24	Aug 05 06:03:12 PM PDT 24	2087597402 ps
T178	/workspace/coverage/default/27.sram_ctrl_executable.1733530545	Aug 05 05:51:07 PM PDT 24	Aug 05 06:05:36 PM PDT 24	79945111500 ps
T179	/workspace/coverage/default/41.sram_ctrl_ram_cfg.4100904410	Aug 05 05:52:26 PM PDT 24	Aug 05 05:52:27 PM PDT 24	87019615 ps
T180	/workspace/coverage/default/9.sram_ctrl_partial_access.2049914445	Aug 05 05:50:12 PM PDT 24	Aug 05 05:50:51 PM PDT 24	1666215598 ps
T181	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.715065412	Aug 05 05:51:35 PM PDT 24	Aug 05 06:00:42 PM PDT 24	23632221667 ps
T182	/workspace/coverage/default/11.sram_ctrl_max_throughput.2951319582	Aug 05 05:50:31 PM PDT 24	Aug 05 05:52:40 PM PDT 24	259706072 ps
T183	/workspace/coverage/default/12.sram_ctrl_smoke.1853293870	Aug 05 05:50:16 PM PDT 24	Aug 05 05:51:50 PM PDT 24	1991519137 ps
T184	/workspace/coverage/default/18.sram_ctrl_lc_escalation.2698415622	Aug 05 05:50:44 PM PDT 24	Aug 05 05:50:46 PM PDT 24	494706232 ps
T185	/workspace/coverage/default/44.sram_ctrl_lc_escalation.521231197	Aug 05 05:52:52 PM PDT 24	Aug 05 05:53:03 PM PDT 24	4060280301 ps
T186	/workspace/coverage/default/15.sram_ctrl_mem_walk.1089038071	Aug 05 05:50:23 PM PDT 24	Aug 05 05:50:31 PM PDT 24	267507249 ps
T123	/workspace/coverage/default/2.sram_ctrl_regwen.150944121	Aug 05 05:50:07 PM PDT 24	Aug 05 06:02:58 PM PDT 24	18483617868 ps
T187	/workspace/coverage/default/33.sram_ctrl_bijection.1209417874	Aug 05 05:51:30 PM PDT 24	Aug 05 05:52:30 PM PDT 24	12025651458 ps
T188	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3792577104	Aug 05 05:51:36 PM PDT 24	Aug 05 05:56:43 PM PDT 24	6240181730 ps
T189	/workspace/coverage/default/26.sram_ctrl_partial_access.4197256519	Aug 05 05:50:56 PM PDT 24	Aug 05 05:52:18 PM PDT 24	371971129 ps
T190	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1294852129	Aug 05 05:50:07 PM PDT 24	Aug 05 05:51:28 PM PDT 24	153874011 ps
T191	/workspace/coverage/default/11.sram_ctrl_partial_access.1226615347	Aug 05 05:50:14 PM PDT 24	Aug 05 05:51:07 PM PDT 24	1610951356 ps
T124	/workspace/coverage/default/37.sram_ctrl_regwen.1124988197	Aug 05 05:51:59 PM PDT 24	Aug 05 06:17:13 PM PDT 24	26780651494 ps
T192	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1076110503	Aug 05 05:50:35 PM PDT 24	Aug 05 05:54:55 PM PDT 24	3395182196 ps
T193	/workspace/coverage/default/14.sram_ctrl_stress_all.276242365	Aug 05 05:50:28 PM PDT 24	Aug 05 06:14:23 PM PDT 24	19120738504 ps
T194	/workspace/coverage/default/15.sram_ctrl_stress_all.1043567222	Aug 05 05:50:25 PM PDT 24	Aug 05 07:10:32 PM PDT 24	40741679175 ps
T195	/workspace/coverage/default/7.sram_ctrl_stress_all.226857066	Aug 05 05:50:09 PM PDT 24	Aug 05 06:18:45 PM PDT 24	106141017178 ps
T196	/workspace/coverage/default/24.sram_ctrl_alert_test.4148786274	Aug 05 05:50:56 PM PDT 24	Aug 05 05:50:57 PM PDT 24	15489242 ps
T197	/workspace/coverage/default/45.sram_ctrl_partial_access.676958290	Aug 05 05:52:55 PM PDT 24	Aug 05 05:53:13 PM PDT 24	3289071654 ps
T198	/workspace/coverage/default/9.sram_ctrl_smoke.74353973	Aug 05 05:50:08 PM PDT 24	Aug 05 05:50:18 PM PDT 24	552992787 ps
T199	/workspace/coverage/default/21.sram_ctrl_ram_cfg.140839599	Aug 05 05:50:35 PM PDT 24	Aug 05 05:50:35 PM PDT 24	45258351 ps
T200	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3319535334	Aug 05 05:51:56 PM PDT 24	Aug 05 05:53:49 PM PDT 24	283984993 ps
T58	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1565485888	Aug 05 05:50:34 PM PDT 24	Aug 05 05:51:49 PM PDT 24	857751020 ps
T201	/workspace/coverage/default/5.sram_ctrl_bijection.3157716289	Aug 05 05:50:00 PM PDT 24	Aug 05 05:50:22 PM PDT 24	2397635503 ps
T202	/workspace/coverage/default/31.sram_ctrl_mem_walk.3637049748	Aug 05 05:51:26 PM PDT 24	Aug 05 05:51:31 PM PDT 24	240144775 ps
T203	/workspace/coverage/default/23.sram_ctrl_mem_walk.222748909	Aug 05 05:50:48 PM PDT 24	Aug 05 05:50:53 PM PDT 24	75669161 ps
T204	/workspace/coverage/default/44.sram_ctrl_partial_access.4063573540	Aug 05 05:52:56 PM PDT 24	Aug 05 05:53:14 PM PDT 24	1155255803 ps
T205	/workspace/coverage/default/18.sram_ctrl_mem_walk.4095349635	Aug 05 05:50:34 PM PDT 24	Aug 05 05:50:45 PM PDT 24	681540978 ps
T206	/workspace/coverage/default/10.sram_ctrl_partial_access.986562180	Aug 05 05:50:12 PM PDT 24	Aug 05 05:50:32 PM PDT 24	1105052635 ps
T45	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2746664914	Aug 05 05:50:31 PM PDT 24	Aug 05 05:50:34 PM PDT 24	57180048 ps
T207	/workspace/coverage/default/7.sram_ctrl_smoke.1496156344	Aug 05 05:50:14 PM PDT 24	Aug 05 05:50:26 PM PDT 24	4549207593 ps
T208	/workspace/coverage/default/13.sram_ctrl_ram_cfg.2620427755	Aug 05 05:50:30 PM PDT 24	Aug 05 05:50:31 PM PDT 24	30562983 ps
T209	/workspace/coverage/default/35.sram_ctrl_max_throughput.141895219	Aug 05 05:51:39 PM PDT 24	Aug 05 05:51:44 PM PDT 24	95362597 ps
T210	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.301999794	Aug 05 05:49:52 PM PDT 24	Aug 05 05:51:46 PM PDT 24	613768362 ps
T211	/workspace/coverage/default/13.sram_ctrl_partial_access.3590923262	Aug 05 05:50:32 PM PDT 24	Aug 05 05:50:47 PM PDT 24	955106227 ps
T212	/workspace/coverage/default/40.sram_ctrl_smoke.1609993952	Aug 05 05:52:16 PM PDT 24	Aug 05 05:53:18 PM PDT 24	557153519 ps
T213	/workspace/coverage/default/23.sram_ctrl_smoke.3401146234	Aug 05 05:50:47 PM PDT 24	Aug 05 05:50:54 PM PDT 24	168319645 ps
T214	/workspace/coverage/default/28.sram_ctrl_smoke.2069816111	Aug 05 05:51:06 PM PDT 24	Aug 05 05:51:09 PM PDT 24	92298204 ps
T215	/workspace/coverage/default/37.sram_ctrl_partial_access.3737668284	Aug 05 05:51:54 PM PDT 24	Aug 05 05:52:01 PM PDT 24	442787778 ps
T216	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2382055609	Aug 05 05:50:06 PM PDT 24	Aug 05 05:55:34 PM PDT 24	4428690203 ps
T217	/workspace/coverage/default/33.sram_ctrl_multiple_keys.696968254	Aug 05 05:51:28 PM PDT 24	Aug 05 05:54:48 PM PDT 24	1970595738 ps
T218	/workspace/coverage/default/4.sram_ctrl_regwen.843540584	Aug 05 05:49:58 PM PDT 24	Aug 05 06:06:17 PM PDT 24	10273268927 ps
T219	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.172474229	Aug 05 05:50:42 PM PDT 24	Aug 05 05:56:25 PM PDT 24	1411683927 ps
T220	/workspace/coverage/default/1.sram_ctrl_executable.3488978941	Aug 05 05:50:01 PM PDT 24	Aug 05 06:13:07 PM PDT 24	80391513267 ps
T221	/workspace/coverage/default/8.sram_ctrl_regwen.1372432510	Aug 05 05:50:13 PM PDT 24	Aug 05 06:00:52 PM PDT 24	2697936195 ps
T46	/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3931436030	Aug 05 05:50:11 PM PDT 24	Aug 05 05:52:25 PM PDT 24	5899280496 ps
T222	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.512583130	Aug 05 05:50:27 PM PDT 24	Aug 05 05:53:00 PM PDT 24	320428238 ps
T223	/workspace/coverage/default/43.sram_ctrl_regwen.1550186320	Aug 05 05:52:44 PM PDT 24	Aug 05 06:08:05 PM PDT 24	2182843288 ps
T224	/workspace/coverage/default/7.sram_ctrl_ram_cfg.2946563195	Aug 05 05:50:14 PM PDT 24	Aug 05 05:50:14 PM PDT 24	85271640 ps
T225	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.639770487	Aug 05 05:50:29 PM PDT 24	Aug 05 05:57:05 PM PDT 24	7287398869 ps
T226	/workspace/coverage/default/41.sram_ctrl_mem_walk.1003858154	Aug 05 05:52:26 PM PDT 24	Aug 05 05:52:39 PM PDT 24	1278760287 ps
T227	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.2217212492	Aug 05 05:51:34 PM PDT 24	Aug 05 05:55:56 PM PDT 24	378672476 ps
T228	/workspace/coverage/default/8.sram_ctrl_stress_all.3130757148	Aug 05 05:50:11 PM PDT 24	Aug 05 06:21:23 PM PDT 24	26931763632 ps
T229	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.810269930	Aug 05 05:53:09 PM PDT 24	Aug 05 05:54:33 PM PDT 24	129580411 ps
T230	/workspace/coverage/default/24.sram_ctrl_stress_all.3512989818	Aug 05 05:50:57 PM PDT 24	Aug 05 06:28:13 PM PDT 24	45556905417 ps
T231	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.814398658	Aug 05 05:51:59 PM PDT 24	Aug 05 05:53:56 PM PDT 24	2185398180 ps
T232	/workspace/coverage/default/29.sram_ctrl_regwen.3363383621	Aug 05 05:51:20 PM PDT 24	Aug 05 06:12:24 PM PDT 24	4241962395 ps
T233	/workspace/coverage/default/19.sram_ctrl_smoke.600365618	Aug 05 05:50:33 PM PDT 24	Aug 05 05:50:47 PM PDT 24	227781710 ps
T234	/workspace/coverage/default/32.sram_ctrl_alert_test.202578163	Aug 05 05:51:34 PM PDT 24	Aug 05 05:51:35 PM PDT 24	21118891 ps
T235	/workspace/coverage/default/17.sram_ctrl_ram_cfg.4197226556	Aug 05 05:50:29 PM PDT 24	Aug 05 05:50:30 PM PDT 24	100223485 ps
T236	/workspace/coverage/default/34.sram_ctrl_lc_escalation.3949179351	Aug 05 05:51:35 PM PDT 24	Aug 05 05:51:37 PM PDT 24	195508533 ps
T237	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1991757211	Aug 05 05:53:19 PM PDT 24	Aug 05 05:58:33 PM PDT 24	17227378412 ps
T238	/workspace/coverage/default/35.sram_ctrl_mem_walk.192407768	Aug 05 05:51:47 PM PDT 24	Aug 05 05:51:58 PM PDT 24	451250922 ps
T239	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3148399427	Aug 05 05:50:40 PM PDT 24	Aug 05 05:51:42 PM PDT 24	138621190 ps
T240	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2672574821	Aug 05 05:52:10 PM PDT 24	Aug 05 05:52:16 PM PDT 24	579957130 ps
T241	/workspace/coverage/default/37.sram_ctrl_alert_test.42277066	Aug 05 05:52:01 PM PDT 24	Aug 05 05:52:02 PM PDT 24	17503213 ps
T242	/workspace/coverage/default/39.sram_ctrl_lc_escalation.3282101326	Aug 05 05:52:10 PM PDT 24	Aug 05 05:52:14 PM PDT 24	441846830 ps
T243	/workspace/coverage/default/22.sram_ctrl_ram_cfg.698167744	Aug 05 05:50:46 PM PDT 24	Aug 05 05:50:47 PM PDT 24	43681933 ps
T244	/workspace/coverage/default/25.sram_ctrl_lc_escalation.768393247	Aug 05 05:50:50 PM PDT 24	Aug 05 05:50:55 PM PDT 24	1735278851 ps
T245	/workspace/coverage/default/38.sram_ctrl_ram_cfg.2121276354	Aug 05 05:52:05 PM PDT 24	Aug 05 05:52:05 PM PDT 24	46634592 ps
T246	/workspace/coverage/default/28.sram_ctrl_max_throughput.1712132957	Aug 05 05:51:06 PM PDT 24	Aug 05 05:53:39 PM PDT 24	512569012 ps
T247	/workspace/coverage/default/34.sram_ctrl_alert_test.3433962206	Aug 05 05:51:38 PM PDT 24	Aug 05 05:51:39 PM PDT 24	133516897 ps
T248	/workspace/coverage/default/23.sram_ctrl_alert_test.1552363582	Aug 05 05:50:56 PM PDT 24	Aug 05 05:50:57 PM PDT 24	31403876 ps
T249	/workspace/coverage/default/3.sram_ctrl_lc_escalation.1972015510	Aug 05 05:49:47 PM PDT 24	Aug 05 05:49:53 PM PDT 24	1603164385 ps
T250	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.1835895021	Aug 05 05:51:35 PM PDT 24	Aug 05 06:10:31 PM PDT 24	5015442558 ps
T251	/workspace/coverage/default/31.sram_ctrl_ram_cfg.3936227540	Aug 05 05:51:28 PM PDT 24	Aug 05 05:51:29 PM PDT 24	48149455 ps
T252	/workspace/coverage/default/39.sram_ctrl_stress_all.2056306158	Aug 05 05:52:12 PM PDT 24	Aug 05 06:27:18 PM PDT 24	30230020771 ps
T253	/workspace/coverage/default/48.sram_ctrl_regwen.2589145460	Aug 05 05:53:22 PM PDT 24	Aug 05 06:03:52 PM PDT 24	1364294830 ps
T254	/workspace/coverage/default/16.sram_ctrl_stress_all.2513025377	Aug 05 05:50:45 PM PDT 24	Aug 05 05:58:57 PM PDT 24	36092676878 ps
T255	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2103630886	Aug 05 05:52:50 PM PDT 24	Aug 05 05:58:45 PM PDT 24	5033216273 ps
T256	/workspace/coverage/default/25.sram_ctrl_alert_test.3257778440	Aug 05 05:50:56 PM PDT 24	Aug 05 05:50:57 PM PDT 24	34915859 ps
T257	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2593734458	Aug 05 05:51:29 PM PDT 24	Aug 05 05:55:50 PM PDT 24	5349022187 ps
T258	/workspace/coverage/default/16.sram_ctrl_regwen.232134592	Aug 05 05:50:33 PM PDT 24	Aug 05 05:57:58 PM PDT 24	5265451994 ps
T259	/workspace/coverage/default/41.sram_ctrl_alert_test.3984745060	Aug 05 05:52:26 PM PDT 24	Aug 05 05:52:27 PM PDT 24	15515621 ps
T260	/workspace/coverage/default/16.sram_ctrl_ram_cfg.250814070	Aug 05 05:50:33 PM PDT 24	Aug 05 05:50:34 PM PDT 24	92843618 ps
T261	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2305214921	Aug 05 05:52:45 PM PDT 24	Aug 05 05:57:33 PM PDT 24	999463069 ps
T59	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2666954815	Aug 05 05:52:12 PM PDT 24	Aug 05 05:52:26 PM PDT 24	4072429631 ps
T262	/workspace/coverage/default/39.sram_ctrl_smoke.2296180290	Aug 05 05:52:06 PM PDT 24	Aug 05 05:52:16 PM PDT 24	170508843 ps
T263	/workspace/coverage/default/22.sram_ctrl_regwen.1340246477	Aug 05 05:50:44 PM PDT 24	Aug 05 06:00:41 PM PDT 24	4918328311 ps
T264	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1102998319	Aug 05 05:50:09 PM PDT 24	Aug 05 05:53:24 PM PDT 24	19236248242 ps
T265	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.3039292152	Aug 05 05:50:42 PM PDT 24	Aug 05 05:50:48 PM PDT 24	160387178 ps
T266	/workspace/coverage/default/13.sram_ctrl_multiple_keys.4245851075	Aug 05 05:50:16 PM PDT 24	Aug 05 05:57:18 PM PDT 24	17368126385 ps
T267	/workspace/coverage/default/0.sram_ctrl_alert_test.4078534802	Aug 05 05:50:07 PM PDT 24	Aug 05 05:50:08 PM PDT 24	10958258 ps
T268	/workspace/coverage/default/48.sram_ctrl_bijection.1268600666	Aug 05 05:53:20 PM PDT 24	Aug 05 05:53:57 PM PDT 24	4431399728 ps
T269	/workspace/coverage/default/15.sram_ctrl_max_throughput.1109973145	Aug 05 05:50:26 PM PDT 24	Aug 05 05:50:28 PM PDT 24	50543925 ps
T270	/workspace/coverage/default/46.sram_ctrl_mem_walk.513277461	Aug 05 05:53:07 PM PDT 24	Aug 05 05:53:11 PM PDT 24	288465280 ps
T60	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1234951855	Aug 05 05:50:22 PM PDT 24	Aug 05 05:53:32 PM PDT 24	8108216624 ps
T271	/workspace/coverage/default/32.sram_ctrl_bijection.3438496061	Aug 05 05:51:35 PM PDT 24	Aug 05 05:52:42 PM PDT 24	4291021269 ps
T272	/workspace/coverage/default/3.sram_ctrl_partial_access.4270403705	Aug 05 05:49:57 PM PDT 24	Aug 05 05:50:47 PM PDT 24	1543695216 ps
T100	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2092206894	Aug 05 05:50:58 PM PDT 24	Aug 05 05:51:57 PM PDT 24	1919449306 ps
T273	/workspace/coverage/default/35.sram_ctrl_lc_escalation.2208338299	Aug 05 05:51:39 PM PDT 24	Aug 05 05:51:46 PM PDT 24	495459548 ps
T274	/workspace/coverage/default/34.sram_ctrl_executable.2633985248	Aug 05 05:51:40 PM PDT 24	Aug 05 05:55:48 PM PDT 24	1251238653 ps
T275	/workspace/coverage/default/3.sram_ctrl_multiple_keys.3738189077	Aug 05 05:50:06 PM PDT 24	Aug 05 06:03:19 PM PDT 24	9841245385 ps
T276	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.4278936078	Aug 05 05:50:17 PM PDT 24	Aug 05 06:10:43 PM PDT 24	17431973704 ps
T101	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3115612478	Aug 05 05:52:01 PM PDT 24	Aug 05 05:52:44 PM PDT 24	2880582170 ps
T277	/workspace/coverage/default/35.sram_ctrl_stress_all.1170084891	Aug 05 05:51:46 PM PDT 24	Aug 05 06:11:47 PM PDT 24	97281178220 ps
T278	/workspace/coverage/default/39.sram_ctrl_alert_test.81365174	Aug 05 05:52:16 PM PDT 24	Aug 05 05:52:17 PM PDT 24	46198675 ps
T279	/workspace/coverage/default/4.sram_ctrl_mem_walk.2775805853	Aug 05 05:50:05 PM PDT 24	Aug 05 05:50:10 PM PDT 24	345102974 ps
T280	/workspace/coverage/default/3.sram_ctrl_executable.1875629402	Aug 05 05:49:48 PM PDT 24	Aug 05 06:03:54 PM PDT 24	12360495791 ps
T281	/workspace/coverage/default/12.sram_ctrl_executable.644920261	Aug 05 05:50:28 PM PDT 24	Aug 05 06:10:04 PM PDT 24	37566694848 ps
T282	/workspace/coverage/default/46.sram_ctrl_alert_test.60284375	Aug 05 05:53:12 PM PDT 24	Aug 05 05:53:12 PM PDT 24	36829572 ps
T283	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1977204773	Aug 05 05:52:10 PM PDT 24	Aug 05 05:56:20 PM PDT 24	9943425652 ps
T284	/workspace/coverage/default/20.sram_ctrl_mem_walk.112826397	Aug 05 05:50:41 PM PDT 24	Aug 05 05:50:47 PM PDT 24	861387518 ps
T285	/workspace/coverage/default/43.sram_ctrl_bijection.150605940	Aug 05 05:52:42 PM PDT 24	Aug 05 05:53:48 PM PDT 24	3167389462 ps
T286	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.845917677	Aug 05 05:50:51 PM PDT 24	Aug 05 05:54:15 PM PDT 24	8884539228 ps
T287	/workspace/coverage/default/42.sram_ctrl_mem_walk.1590117062	Aug 05 05:52:40 PM PDT 24	Aug 05 05:52:49 PM PDT 24	139503017 ps
T288	/workspace/coverage/default/22.sram_ctrl_executable.2898143246	Aug 05 05:50:41 PM PDT 24	Aug 05 06:10:15 PM PDT 24	15489476977 ps
T102	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3402315778	Aug 05 05:50:50 PM PDT 24	Aug 05 05:51:00 PM PDT 24	743901202 ps
T289	/workspace/coverage/default/7.sram_ctrl_executable.1038279381	Aug 05 05:50:05 PM PDT 24	Aug 05 06:00:29 PM PDT 24	89765808936 ps
T290	/workspace/coverage/default/39.sram_ctrl_max_throughput.4096767550	Aug 05 05:52:08 PM PDT 24	Aug 05 05:53:57 PM PDT 24	121903863 ps
T291	/workspace/coverage/default/27.sram_ctrl_mem_walk.985637795	Aug 05 05:51:09 PM PDT 24	Aug 05 05:51:14 PM PDT 24	226520207 ps
T292	/workspace/coverage/default/31.sram_ctrl_alert_test.3703497486	Aug 05 05:51:31 PM PDT 24	Aug 05 05:51:32 PM PDT 24	50581480 ps
T293	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.130789235	Aug 05 05:52:56 PM PDT 24	Aug 05 05:53:00 PM PDT 24	347624458 ps
T294	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1184051014	Aug 05 05:52:10 PM PDT 24	Aug 05 06:00:16 PM PDT 24	1981945504 ps
T295	/workspace/coverage/default/0.sram_ctrl_stress_all.2670304253	Aug 05 05:49:54 PM PDT 24	Aug 05 06:11:49 PM PDT 24	119772752814 ps
T296	/workspace/coverage/default/2.sram_ctrl_executable.907203704	Aug 05 05:50:01 PM PDT 24	Aug 05 06:05:16 PM PDT 24	12827734373 ps
T297	/workspace/coverage/default/11.sram_ctrl_mem_walk.3416909143	Aug 05 05:50:15 PM PDT 24	Aug 05 05:50:21 PM PDT 24	700156050 ps
T298	/workspace/coverage/default/33.sram_ctrl_mem_walk.1179626886	Aug 05 05:51:36 PM PDT 24	Aug 05 05:51:45 PM PDT 24	541243448 ps
T299	/workspace/coverage/default/40.sram_ctrl_partial_access.2726961436	Aug 05 05:52:16 PM PDT 24	Aug 05 05:52:18 PM PDT 24	204935698 ps
T300	/workspace/coverage/default/26.sram_ctrl_stress_all.4229989627	Aug 05 05:51:08 PM PDT 24	Aug 05 06:48:40 PM PDT 24	42328158337 ps
T301	/workspace/coverage/default/9.sram_ctrl_alert_test.2060534802	Aug 05 05:50:18 PM PDT 24	Aug 05 05:50:19 PM PDT 24	17213889 ps
T302	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3747878099	Aug 05 05:51:45 PM PDT 24	Aug 05 05:51:50 PM PDT 24	243323595 ps