Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43028189	1			T1	3093		T2	127		T3	88
triple_byte_access	2503399	1			T2	231		T3	242		T4	617
halfword_access	3756253	1			T2	455		T3	416		T4	858
byte_access	5020172	1			T2	781		T3	805		T4	1154
zero_access	1263271	1			T2	437		T3	408		T4	275

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27739342

1

T1

1570

T2

885

T3

866

auto[1]

27831942

1

T1

1523

T2

1146

T3

1093

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21470655	1			T1	1570		T2	7		T3	4
auto[0]	triple_byte_access	1249228	1			T2	37		T3	28		T4	301
auto[0]	halfword_access	1874671	1			T2	138		T3	125		T4	440
auto[0]	byte_access	2509118	1			T2	378		T3	401		T4	593
auto[0]	zero_access	635670	1			T2	325		T3	308		T4	136
auto[1]	word_access	21557534	1			T1	1523		T2	120		T3	84
auto[1]	triple_byte_access	1254171	1			T2	194		T3	214		T4	316
auto[1]	halfword_access	1881582	1			T2	317		T3	291		T4	418
auto[1]	byte_access	2511054	1			T2	403		T3	404		T4	561
auto[1]	zero_access	627601	1			T2	112		T3	100		T4	139