Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	140890568	1			T1	139638		T2	3816		T3	10940
instr_valid_dis	112235747	1			T1	139638		T2	3816		T3	10940
instr_en	18465591	1			T4	38692		T6	497356		T8	73360

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10517379	1			T4	18620		T6	145396		T8	73360
sram_ifetch_valid_disable	109442427	1			T1	139638		T2	3816		T3	10940
sram_ifetch_enable	20930762	1			T13	21850		T6	229096		T8	35684

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	140890568	1			T1	139638		T2	3816		T3	10940
hw_debug_en_valid_off	110597361	1			T1	139638		T2	3816		T3	10940
hw_debug_en_on	20688148	1			T4	72		T6	519432		T8	56536

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109442427	1			T1	139638		T2	3816		T3	10940
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	98208983	1			T1	139638		T2	3816		T3	10940
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7211769	1			T4	20072		T6	224080		T19	233562
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4672376	1			T4	18620		T19	50830		T21	68958
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1969250	1			T21	4772		T131	41804		T135	41858
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1665082	1			T4	18620		T21	64186		T130	57278
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3887685	1			T6	45852		T8	43766		T19	11722
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2004090	1			T6	42018		T21	55352		T135	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1172194	1			T6	3834		T8	43766		T19	2170
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7836566	1			T4	72		T6	400468		T8	12770
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3369208	1			T8	12770		T134	86		T21	59038
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2808538	1			T4	72		T6	47840		T19	30102

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7527364	1			T6	229096		T19	286552		T21	163578
lc_exec_en	8963897	1			T6	73112		T19	453556		T21	70816
valid_exec_dis	107251354	1			T1	139638		T2	3816		T3	10940
invalid_exec_dis	31448141	1			T4	18620		T13	21850		T6	374492