Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42300765	1			T1	63437		T2	95		T3	5002
triple_byte_access	2436871	1			T1	1309		T2	249		T3	99
halfword_access	3656937	1			T1	1883		T2	411		T3	151
byte_access	4880920	1			T1	2571		T2	737		T3	183
zero_access	1227099	1			T1	619		T2	416		T3	35

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27200352

1

T1

35086

T2

823

T3

2729

auto[1]

27302240

1

T1

34733

T2

1085

T3

2741

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21104790	1			T1	31856		T2	6		T3	2476
auto[0]	triple_byte_access	1215202	1			T1	628		T2	34		T3	54
auto[0]	halfword_access	1824022	1			T1	963		T2	115		T3	82
auto[0]	byte_access	2438493	1			T1	1309		T2	358		T3	102
auto[0]	zero_access	617845	1			T1	330		T2	310		T3	15
auto[1]	word_access	21195975	1			T1	31581		T2	89		T3	2526
auto[1]	triple_byte_access	1221669	1			T1	681		T2	215		T3	45
auto[1]	halfword_access	1832915	1			T1	920		T2	296		T3	69
auto[1]	byte_access	2442427	1			T1	1262		T2	379		T3	81
auto[1]	zero_access	609254	1			T1	289		T2	106		T3	20