Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	149972290	1			T1	3142		T2	5780		T3	242558
instr_valid_dis	116626077	1			T1	3142		T2	5780		T3	59940
instr_en	23101751	1			T7	454992		T16	160070		T55	129762

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12516842	1			T3	30744		T7	139516		T22	28594
sram_ifetch_valid_disable	114336211	1			T1	3142		T2	5780		T3	135008
sram_ifetch_enable	23119237	1			T3	76806		T7	580084		T22	61060

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	149972290	1			T1	3142		T2	5780		T3	242558
hw_debug_en_valid_off	115091743	1			T1	3142		T2	5780		T3	81686
hw_debug_en_on	23141399	1			T3	136996		T7	521158		T22	15666

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114336211	1			T1	3142		T2	5780		T3	135008
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102237765	1			T1	3142		T2	5780		T3	59940
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8177600	1			T7	157540		T16	44426		T55	57552
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4473120	1			T7	139516		T22	8952		T16	36376
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1748908	1			T7	48056		T22	8952		T71	114692
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2061164	1			T7	42518		T16	36376		T55	19004
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5379274	1			T3	30744		T55	97428		T71	68590
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2332672	1			T55	31272		T71	68590		T80	59034
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2097150	1			T55	53206		T152	37214		T153	10280
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8868836	1			T3	65574		T7	260122		T16	36762
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4210178	1			T7	165866		T57	62830		T71	99916
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3209318	1			T7	94256		T16	36762		T57	13368

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9683961	1			T7	254934		T16	79268		T57	87162
lc_exec_en	8893289	1			T3	40678		T7	261036		T22	15666
valid_exec_dis	109734649	1			T1	3142		T2	5780		T3	64356
invalid_exec_dis	35636079	1			T3	107550		T7	719600		T22	89654