| T797 |
/workspace/coverage/default/48.sram_ctrl_smoke.1549648945 |
|
|
Aug 07 06:09:45 PM PDT 24 |
Aug 07 06:09:49 PM PDT 24 |
208238386 ps |
| T798 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2635801772 |
|
|
Aug 07 06:03:51 PM PDT 24 |
Aug 07 06:08:13 PM PDT 24 |
120146453362 ps |
| T799 |
/workspace/coverage/default/35.sram_ctrl_regwen.1968326817 |
|
|
Aug 07 06:07:29 PM PDT 24 |
Aug 07 06:09:07 PM PDT 24 |
2346053205 ps |
| T800 |
/workspace/coverage/default/46.sram_ctrl_executable.2131750663 |
|
|
Aug 07 06:09:32 PM PDT 24 |
Aug 07 06:23:55 PM PDT 24 |
49549530290 ps |
| T801 |
/workspace/coverage/default/34.sram_ctrl_bijection.181691554 |
|
|
Aug 07 06:07:09 PM PDT 24 |
Aug 07 06:08:04 PM PDT 24 |
1393251396 ps |
| T802 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.1087436078 |
|
|
Aug 07 06:04:02 PM PDT 24 |
Aug 07 06:04:28 PM PDT 24 |
180313453 ps |
| T803 |
/workspace/coverage/default/9.sram_ctrl_stress_all.103062001 |
|
|
Aug 07 06:04:14 PM PDT 24 |
Aug 07 06:53:28 PM PDT 24 |
10003330996 ps |
| T804 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.758614235 |
|
|
Aug 07 06:06:52 PM PDT 24 |
Aug 07 06:06:53 PM PDT 24 |
373412526 ps |
| T805 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1110250017 |
|
|
Aug 07 06:06:47 PM PDT 24 |
Aug 07 06:08:34 PM PDT 24 |
2854805570 ps |
| T806 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2801968568 |
|
|
Aug 07 06:05:00 PM PDT 24 |
Aug 07 06:17:10 PM PDT 24 |
2638633303 ps |
| T807 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.284195444 |
|
|
Aug 07 06:05:00 PM PDT 24 |
Aug 07 06:18:07 PM PDT 24 |
17460035300 ps |
| T808 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3464915148 |
|
|
Aug 07 06:10:20 PM PDT 24 |
Aug 07 06:55:18 PM PDT 24 |
163168351584 ps |
| T809 |
/workspace/coverage/default/20.sram_ctrl_bijection.584927385 |
|
|
Aug 07 06:05:11 PM PDT 24 |
Aug 07 06:05:48 PM PDT 24 |
583340034 ps |
| T810 |
/workspace/coverage/default/40.sram_ctrl_partial_access.2125951907 |
|
|
Aug 07 06:08:15 PM PDT 24 |
Aug 07 06:09:37 PM PDT 24 |
2479188995 ps |
| T811 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.1931728318 |
|
|
Aug 07 06:04:50 PM PDT 24 |
Aug 07 06:04:56 PM PDT 24 |
97081851 ps |
| T812 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1818682180 |
|
|
Aug 07 06:07:33 PM PDT 24 |
Aug 07 06:31:29 PM PDT 24 |
178623942762 ps |
| T813 |
/workspace/coverage/default/38.sram_ctrl_regwen.736437149 |
|
|
Aug 07 06:07:59 PM PDT 24 |
Aug 07 06:09:17 PM PDT 24 |
771522088 ps |
| T814 |
/workspace/coverage/default/10.sram_ctrl_executable.3947464085 |
|
|
Aug 07 06:04:30 PM PDT 24 |
Aug 07 06:19:03 PM PDT 24 |
4662443262 ps |
| T815 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1539576454 |
|
|
Aug 07 06:04:47 PM PDT 24 |
Aug 07 06:15:58 PM PDT 24 |
8701750970 ps |
| T816 |
/workspace/coverage/default/28.sram_ctrl_alert_test.3109092716 |
|
|
Aug 07 06:06:17 PM PDT 24 |
Aug 07 06:06:18 PM PDT 24 |
28260705 ps |
| T817 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2658173959 |
|
|
Aug 07 06:03:55 PM PDT 24 |
Aug 07 06:03:55 PM PDT 24 |
13172061 ps |
| T818 |
/workspace/coverage/default/32.sram_ctrl_regwen.2126395016 |
|
|
Aug 07 06:06:51 PM PDT 24 |
Aug 07 06:07:27 PM PDT 24 |
3123222742 ps |
| T46 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1050753850 |
|
|
Aug 07 06:06:43 PM PDT 24 |
Aug 07 06:08:01 PM PDT 24 |
2554305389 ps |
| T819 |
/workspace/coverage/default/2.sram_ctrl_regwen.2416071299 |
|
|
Aug 07 06:03:31 PM PDT 24 |
Aug 07 06:27:15 PM PDT 24 |
14565345253 ps |
| T820 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.715429472 |
|
|
Aug 07 06:05:23 PM PDT 24 |
Aug 07 06:05:28 PM PDT 24 |
76953450 ps |
| T25 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.644669969 |
|
|
Aug 07 06:03:40 PM PDT 24 |
Aug 07 06:03:43 PM PDT 24 |
273030145 ps |
| T821 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1526981432 |
|
|
Aug 07 06:04:20 PM PDT 24 |
Aug 07 06:04:28 PM PDT 24 |
3607741554 ps |
| T822 |
/workspace/coverage/default/39.sram_ctrl_executable.3157416934 |
|
|
Aug 07 06:08:09 PM PDT 24 |
Aug 07 06:30:43 PM PDT 24 |
14325615862 ps |
| T823 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1908410875 |
|
|
Aug 07 06:06:22 PM PDT 24 |
Aug 07 06:06:23 PM PDT 24 |
81633768 ps |
| T824 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2903889548 |
|
|
Aug 07 06:05:16 PM PDT 24 |
Aug 07 06:05:20 PM PDT 24 |
425930988 ps |
| T825 |
/workspace/coverage/default/28.sram_ctrl_bijection.1513756602 |
|
|
Aug 07 06:06:13 PM PDT 24 |
Aug 07 06:07:02 PM PDT 24 |
2999459955 ps |
| T826 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1693781982 |
|
|
Aug 07 06:03:45 PM PDT 24 |
Aug 07 06:03:53 PM PDT 24 |
688184822 ps |
| T827 |
/workspace/coverage/default/43.sram_ctrl_bijection.105114880 |
|
|
Aug 07 06:08:43 PM PDT 24 |
Aug 07 06:09:36 PM PDT 24 |
2868572781 ps |
| T828 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.431806371 |
|
|
Aug 07 06:04:02 PM PDT 24 |
Aug 07 06:21:56 PM PDT 24 |
25517131315 ps |
| T829 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.2329407987 |
|
|
Aug 07 06:05:36 PM PDT 24 |
Aug 07 06:05:44 PM PDT 24 |
1394850799 ps |
| T830 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2646724981 |
|
|
Aug 07 06:07:26 PM PDT 24 |
Aug 07 06:07:53 PM PDT 24 |
91432152 ps |
| T831 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1028864807 |
|
|
Aug 07 06:07:15 PM PDT 24 |
Aug 07 06:07:32 PM PDT 24 |
112202351 ps |
| T26 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.1917537612 |
|
|
Aug 07 06:03:30 PM PDT 24 |
Aug 07 06:03:33 PM PDT 24 |
254723987 ps |
| T832 |
/workspace/coverage/default/23.sram_ctrl_executable.2569933501 |
|
|
Aug 07 06:05:34 PM PDT 24 |
Aug 07 06:08:52 PM PDT 24 |
2637152552 ps |
| T102 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.1359362810 |
|
|
Aug 07 06:07:14 PM PDT 24 |
Aug 07 06:07:17 PM PDT 24 |
295005930 ps |
| T833 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2127317977 |
|
|
Aug 07 06:07:53 PM PDT 24 |
Aug 07 06:13:21 PM PDT 24 |
5230857665 ps |
| T834 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4158637083 |
|
|
Aug 07 06:06:34 PM PDT 24 |
Aug 07 06:10:16 PM PDT 24 |
5205678885 ps |
| T835 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2958871227 |
|
|
Aug 07 06:07:00 PM PDT 24 |
Aug 07 06:07:15 PM PDT 24 |
150816656 ps |
| T836 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1229131343 |
|
|
Aug 07 06:05:00 PM PDT 24 |
Aug 07 06:09:12 PM PDT 24 |
11536086577 ps |
| T837 |
/workspace/coverage/default/44.sram_ctrl_regwen.3938966968 |
|
|
Aug 07 06:08:57 PM PDT 24 |
Aug 07 06:24:19 PM PDT 24 |
12167634070 ps |
| T838 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.487666852 |
|
|
Aug 07 06:07:00 PM PDT 24 |
Aug 07 06:25:49 PM PDT 24 |
5302520355 ps |
| T839 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1941783357 |
|
|
Aug 07 06:03:56 PM PDT 24 |
Aug 07 06:04:00 PM PDT 24 |
685623596 ps |
| T840 |
/workspace/coverage/default/14.sram_ctrl_regwen.3430131688 |
|
|
Aug 07 06:04:45 PM PDT 24 |
Aug 07 06:21:59 PM PDT 24 |
15643304301 ps |
| T841 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1128335478 |
|
|
Aug 07 06:05:20 PM PDT 24 |
Aug 07 06:05:30 PM PDT 24 |
1078269301 ps |
| T842 |
/workspace/coverage/default/47.sram_ctrl_executable.1819579399 |
|
|
Aug 07 06:09:39 PM PDT 24 |
Aug 07 06:24:35 PM PDT 24 |
11974966298 ps |
| T843 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2091657009 |
|
|
Aug 07 06:08:39 PM PDT 24 |
Aug 07 06:08:47 PM PDT 24 |
2560231019 ps |
| T844 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2566529264 |
|
|
Aug 07 06:08:48 PM PDT 24 |
Aug 07 06:09:08 PM PDT 24 |
1773087722 ps |
| T845 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1880628307 |
|
|
Aug 07 06:03:39 PM PDT 24 |
Aug 07 06:14:12 PM PDT 24 |
9037929374 ps |
| T846 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3909038235 |
|
|
Aug 07 06:06:59 PM PDT 24 |
Aug 07 06:12:54 PM PDT 24 |
908028876 ps |
| T847 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.944156128 |
|
|
Aug 07 06:09:11 PM PDT 24 |
Aug 07 06:09:18 PM PDT 24 |
1526021331 ps |
| T848 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.3235005862 |
|
|
Aug 07 06:05:31 PM PDT 24 |
Aug 07 06:27:59 PM PDT 24 |
4957185181 ps |
| T849 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.1031950026 |
|
|
Aug 07 06:09:29 PM PDT 24 |
Aug 07 06:09:32 PM PDT 24 |
44686312 ps |
| T850 |
/workspace/coverage/default/46.sram_ctrl_smoke.3794458252 |
|
|
Aug 07 06:09:21 PM PDT 24 |
Aug 07 06:09:29 PM PDT 24 |
133203174 ps |
| T851 |
/workspace/coverage/default/41.sram_ctrl_partial_access.3401962382 |
|
|
Aug 07 06:08:24 PM PDT 24 |
Aug 07 06:10:23 PM PDT 24 |
398693719 ps |
| T852 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.672919674 |
|
|
Aug 07 06:06:27 PM PDT 24 |
Aug 07 06:09:43 PM PDT 24 |
7898816417 ps |
| T853 |
/workspace/coverage/default/24.sram_ctrl_executable.3631957717 |
|
|
Aug 07 06:05:46 PM PDT 24 |
Aug 07 06:22:33 PM PDT 24 |
79678277570 ps |
| T854 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.4043632247 |
|
|
Aug 07 06:06:14 PM PDT 24 |
Aug 07 06:06:20 PM PDT 24 |
398670065 ps |
| T855 |
/workspace/coverage/default/49.sram_ctrl_bijection.2018650650 |
|
|
Aug 07 06:10:09 PM PDT 24 |
Aug 07 06:11:25 PM PDT 24 |
8889627631 ps |
| T856 |
/workspace/coverage/default/33.sram_ctrl_stress_all.3079994194 |
|
|
Aug 07 06:07:13 PM PDT 24 |
Aug 07 06:53:00 PM PDT 24 |
123306052278 ps |
| T857 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3223056431 |
|
|
Aug 07 06:09:56 PM PDT 24 |
Aug 07 06:35:45 PM PDT 24 |
7164720140 ps |
| T858 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1412671297 |
|
|
Aug 07 06:07:21 PM PDT 24 |
Aug 07 06:11:51 PM PDT 24 |
2738043283 ps |
| T859 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2709806260 |
|
|
Aug 07 06:09:45 PM PDT 24 |
Aug 07 06:09:46 PM PDT 24 |
71305426 ps |
| T860 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2233535708 |
|
|
Aug 07 06:09:41 PM PDT 24 |
Aug 07 06:09:43 PM PDT 24 |
248290544 ps |
| T861 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1962531534 |
|
|
Aug 07 06:10:08 PM PDT 24 |
Aug 07 06:10:20 PM PDT 24 |
314788908 ps |
| T862 |
/workspace/coverage/default/49.sram_ctrl_executable.337092094 |
|
|
Aug 07 06:10:09 PM PDT 24 |
Aug 07 06:27:38 PM PDT 24 |
55675627808 ps |
| T863 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3504336559 |
|
|
Aug 07 06:03:40 PM PDT 24 |
Aug 07 06:10:49 PM PDT 24 |
18570696681 ps |
| T864 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.3976594979 |
|
|
Aug 07 06:07:26 PM PDT 24 |
Aug 07 06:07:32 PM PDT 24 |
1387325479 ps |
| T865 |
/workspace/coverage/default/26.sram_ctrl_alert_test.3514569430 |
|
|
Aug 07 06:06:05 PM PDT 24 |
Aug 07 06:06:06 PM PDT 24 |
32789931 ps |
| T866 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1075449666 |
|
|
Aug 07 06:08:09 PM PDT 24 |
Aug 07 06:08:10 PM PDT 24 |
14994226 ps |
| T867 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1586757298 |
|
|
Aug 07 06:04:01 PM PDT 24 |
Aug 07 06:11:44 PM PDT 24 |
7924213195 ps |
| T868 |
/workspace/coverage/default/43.sram_ctrl_executable.1001399757 |
|
|
Aug 07 06:08:49 PM PDT 24 |
Aug 07 06:13:14 PM PDT 24 |
10543662709 ps |
| T869 |
/workspace/coverage/default/17.sram_ctrl_alert_test.3024280097 |
|
|
Aug 07 06:05:02 PM PDT 24 |
Aug 07 06:05:03 PM PDT 24 |
26214062 ps |
| T870 |
/workspace/coverage/default/14.sram_ctrl_smoke.1925830469 |
|
|
Aug 07 06:04:42 PM PDT 24 |
Aug 07 06:04:50 PM PDT 24 |
853395722 ps |
| T871 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.79155200 |
|
|
Aug 07 06:03:49 PM PDT 24 |
Aug 07 06:03:51 PM PDT 24 |
47418567 ps |
| T872 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2053866451 |
|
|
Aug 07 06:07:20 PM PDT 24 |
Aug 07 06:09:08 PM PDT 24 |
2480839120 ps |
| T873 |
/workspace/coverage/default/32.sram_ctrl_executable.3559648101 |
|
|
Aug 07 06:06:51 PM PDT 24 |
Aug 07 06:14:01 PM PDT 24 |
2193204334 ps |
| T874 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.957635805 |
|
|
Aug 07 06:05:51 PM PDT 24 |
Aug 07 06:05:52 PM PDT 24 |
29197044 ps |
| T875 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3388370938 |
|
|
Aug 07 06:04:50 PM PDT 24 |
Aug 07 06:08:32 PM PDT 24 |
11775086358 ps |
| T876 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.2561206789 |
|
|
Aug 07 06:03:55 PM PDT 24 |
Aug 07 06:15:42 PM PDT 24 |
5209317939 ps |
| T877 |
/workspace/coverage/default/39.sram_ctrl_stress_all.2930941887 |
|
|
Aug 07 06:08:08 PM PDT 24 |
Aug 07 07:42:54 PM PDT 24 |
177981723857 ps |
| T878 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3537335931 |
|
|
Aug 07 06:04:40 PM PDT 24 |
Aug 07 06:07:46 PM PDT 24 |
7324268379 ps |
| T879 |
/workspace/coverage/default/40.sram_ctrl_smoke.3769744232 |
|
|
Aug 07 06:08:08 PM PDT 24 |
Aug 07 06:09:36 PM PDT 24 |
125654333 ps |
| T880 |
/workspace/coverage/default/20.sram_ctrl_alert_test.67973544 |
|
|
Aug 07 06:05:26 PM PDT 24 |
Aug 07 06:05:26 PM PDT 24 |
22087218 ps |
| T881 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1142136774 |
|
|
Aug 07 06:03:56 PM PDT 24 |
Aug 07 06:03:57 PM PDT 24 |
64197958 ps |
| T882 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.3125545549 |
|
|
Aug 07 06:04:50 PM PDT 24 |
Aug 07 06:04:59 PM PDT 24 |
7413810254 ps |
| T883 |
/workspace/coverage/default/8.sram_ctrl_alert_test.3243851386 |
|
|
Aug 07 06:04:01 PM PDT 24 |
Aug 07 06:04:02 PM PDT 24 |
167842820 ps |
| T884 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3922158912 |
|
|
Aug 07 06:04:32 PM PDT 24 |
Aug 07 06:07:09 PM PDT 24 |
19667355471 ps |
| T885 |
/workspace/coverage/default/10.sram_ctrl_regwen.1261450529 |
|
|
Aug 07 06:04:15 PM PDT 24 |
Aug 07 06:25:22 PM PDT 24 |
14251609673 ps |
| T886 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2916146611 |
|
|
Aug 07 06:03:37 PM PDT 24 |
Aug 07 06:03:48 PM PDT 24 |
461986117 ps |
| T887 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.4012997706 |
|
|
Aug 07 06:04:54 PM PDT 24 |
Aug 07 06:05:00 PM PDT 24 |
76856374 ps |
| T888 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.4263626828 |
|
|
Aug 07 06:08:49 PM PDT 24 |
Aug 07 06:12:42 PM PDT 24 |
9879542603 ps |
| T889 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.451955638 |
|
|
Aug 07 06:07:26 PM PDT 24 |
Aug 07 06:07:31 PM PDT 24 |
63361982 ps |
| T890 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2589725368 |
|
|
Aug 07 06:05:27 PM PDT 24 |
Aug 07 06:06:29 PM PDT 24 |
466380962 ps |
| T891 |
/workspace/coverage/default/17.sram_ctrl_bijection.2879998984 |
|
|
Aug 07 06:04:57 PM PDT 24 |
Aug 07 06:05:19 PM PDT 24 |
3107606199 ps |
| T892 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.418771586 |
|
|
Aug 07 06:08:07 PM PDT 24 |
Aug 07 06:08:16 PM PDT 24 |
491280449 ps |
| T125 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1728153927 |
|
|
Aug 07 06:05:01 PM PDT 24 |
Aug 07 06:05:08 PM PDT 24 |
2051315901 ps |
| T893 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2030977512 |
|
|
Aug 07 06:05:17 PM PDT 24 |
Aug 07 06:05:20 PM PDT 24 |
292343723 ps |
| T894 |
/workspace/coverage/default/2.sram_ctrl_stress_all.1473539898 |
|
|
Aug 07 06:03:44 PM PDT 24 |
Aug 07 07:07:43 PM PDT 24 |
59010798035 ps |
| T895 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2721740540 |
|
|
Aug 07 06:05:57 PM PDT 24 |
Aug 07 06:08:11 PM PDT 24 |
1225953869 ps |
| T896 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.808738983 |
|
|
Aug 07 06:05:35 PM PDT 24 |
Aug 07 06:07:25 PM PDT 24 |
144166155 ps |
| T897 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2965357199 |
|
|
Aug 07 06:04:29 PM PDT 24 |
Aug 07 06:18:46 PM PDT 24 |
7287672596 ps |
| T898 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.2545801561 |
|
|
Aug 07 06:05:45 PM PDT 24 |
Aug 07 06:05:51 PM PDT 24 |
304369734 ps |
| T899 |
/workspace/coverage/default/15.sram_ctrl_partial_access.343161815 |
|
|
Aug 07 06:04:52 PM PDT 24 |
Aug 07 06:06:32 PM PDT 24 |
647422393 ps |
| T900 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2132150502 |
|
|
Aug 07 06:07:35 PM PDT 24 |
Aug 07 06:10:53 PM PDT 24 |
8540142838 ps |
| T901 |
/workspace/coverage/default/0.sram_ctrl_regwen.1078054299 |
|
|
Aug 07 06:03:24 PM PDT 24 |
Aug 07 06:23:16 PM PDT 24 |
193190011529 ps |
| T902 |
/workspace/coverage/default/49.sram_ctrl_regwen.3219362124 |
|
|
Aug 07 06:10:07 PM PDT 24 |
Aug 07 06:13:33 PM PDT 24 |
1047762746 ps |
| T903 |
/workspace/coverage/default/40.sram_ctrl_regwen.1636444320 |
|
|
Aug 07 06:08:18 PM PDT 24 |
Aug 07 06:29:40 PM PDT 24 |
9962684503 ps |
| T904 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.4073093536 |
|
|
Aug 07 06:05:18 PM PDT 24 |
Aug 07 06:05:23 PM PDT 24 |
198508775 ps |
| T905 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3614427567 |
|
|
Aug 07 06:03:41 PM PDT 24 |
Aug 07 06:08:20 PM PDT 24 |
10770788831 ps |
| T906 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2547857083 |
|
|
Aug 07 06:03:46 PM PDT 24 |
Aug 07 06:03:51 PM PDT 24 |
325519837 ps |
| T907 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2401313658 |
|
|
Aug 07 06:06:38 PM PDT 24 |
Aug 07 06:10:42 PM PDT 24 |
40710437344 ps |
| T908 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.535967937 |
|
|
Aug 07 06:05:52 PM PDT 24 |
Aug 07 06:05:58 PM PDT 24 |
746554613 ps |
| T909 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.2187815595 |
|
|
Aug 07 06:05:16 PM PDT 24 |
Aug 07 06:05:17 PM PDT 24 |
44444929 ps |
| T910 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1476173039 |
|
|
Aug 07 06:05:23 PM PDT 24 |
Aug 07 06:18:01 PM PDT 24 |
1566327556 ps |
| T911 |
/workspace/coverage/default/39.sram_ctrl_bijection.1585549036 |
|
|
Aug 07 06:08:03 PM PDT 24 |
Aug 07 06:08:45 PM PDT 24 |
2605216363 ps |
| T912 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.514817372 |
|
|
Aug 07 06:06:31 PM PDT 24 |
Aug 07 06:07:33 PM PDT 24 |
222131880 ps |
| T913 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3799620553 |
|
|
Aug 07 06:08:49 PM PDT 24 |
Aug 07 06:08:50 PM PDT 24 |
57824575 ps |
| T914 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.220343671 |
|
|
Aug 07 06:05:45 PM PDT 24 |
Aug 07 06:11:00 PM PDT 24 |
47239436056 ps |
| T915 |
/workspace/coverage/default/16.sram_ctrl_executable.1461296266 |
|
|
Aug 07 06:04:52 PM PDT 24 |
Aug 07 06:15:49 PM PDT 24 |
33261461419 ps |
| T916 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1994155849 |
|
|
Aug 07 06:05:48 PM PDT 24 |
Aug 07 06:05:49 PM PDT 24 |
79956346 ps |
| T917 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1458818883 |
|
|
Aug 07 06:06:13 PM PDT 24 |
Aug 07 06:06:22 PM PDT 24 |
189697157 ps |
| T918 |
/workspace/coverage/default/3.sram_ctrl_regwen.2932909041 |
|
|
Aug 07 06:03:52 PM PDT 24 |
Aug 07 06:24:48 PM PDT 24 |
30280707394 ps |
| T919 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2181167295 |
|
|
Aug 07 06:09:23 PM PDT 24 |
Aug 07 06:19:25 PM PDT 24 |
5061080131 ps |
| T920 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1772824188 |
|
|
Aug 07 06:06:51 PM PDT 24 |
Aug 07 06:15:17 PM PDT 24 |
48459616723 ps |
| T921 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1840548572 |
|
|
Aug 07 06:03:54 PM PDT 24 |
Aug 07 06:03:57 PM PDT 24 |
128343050 ps |
| T922 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.88102965 |
|
|
Aug 07 06:07:09 PM PDT 24 |
Aug 07 06:20:36 PM PDT 24 |
92825838510 ps |
| T923 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.3716145145 |
|
|
Aug 07 06:05:46 PM PDT 24 |
Aug 07 06:06:24 PM PDT 24 |
360731258 ps |
| T924 |
/workspace/coverage/default/8.sram_ctrl_bijection.2662947959 |
|
|
Aug 07 06:04:01 PM PDT 24 |
Aug 07 06:04:25 PM PDT 24 |
1383367619 ps |
| T925 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.1498505799 |
|
|
Aug 07 06:04:15 PM PDT 24 |
Aug 07 06:04:25 PM PDT 24 |
180062969 ps |
| T926 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.3400742801 |
|
|
Aug 07 06:07:20 PM PDT 24 |
Aug 07 06:08:32 PM PDT 24 |
1453177246 ps |
| T927 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.561676509 |
|
|
Aug 07 06:06:52 PM PDT 24 |
Aug 07 06:13:20 PM PDT 24 |
1658100606 ps |
| T928 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3456331864 |
|
|
Aug 07 06:04:56 PM PDT 24 |
Aug 07 06:11:53 PM PDT 24 |
17099146079 ps |
| T929 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.293073804 |
|
|
Aug 07 05:50:31 PM PDT 24 |
Aug 07 05:50:33 PM PDT 24 |
64611016 ps |
| T126 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3076269488 |
|
|
Aug 07 05:50:37 PM PDT 24 |
Aug 07 05:50:38 PM PDT 24 |
238689914 ps |
| T136 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2230538796 |
|
|
Aug 07 05:50:41 PM PDT 24 |
Aug 07 05:50:46 PM PDT 24 |
653729826 ps |
| T77 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3639420457 |
|
|
Aug 07 05:50:32 PM PDT 24 |
Aug 07 05:50:34 PM PDT 24 |
206370342 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2709117619 |
|
|
Aug 07 05:50:28 PM PDT 24 |
Aug 07 05:50:32 PM PDT 24 |
1831656711 ps |
| T73 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1599149486 |
|
|
Aug 07 05:50:38 PM PDT 24 |
Aug 07 05:50:40 PM PDT 24 |
408718354 ps |
| T111 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2465289217 |
|
|
Aug 07 05:50:44 PM PDT 24 |
Aug 07 05:50:45 PM PDT 24 |
40906753 ps |
| T930 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2445574214 |
|
|
Aug 07 05:50:39 PM PDT 24 |
Aug 07 05:50:42 PM PDT 24 |
275371044 ps |
| T85 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.647709124 |
|
|
Aug 07 05:50:46 PM PDT 24 |
Aug 07 05:50:47 PM PDT 24 |
14646333 ps |
| T86 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.993926535 |
|
|
Aug 07 05:50:41 PM PDT 24 |
Aug 07 05:50:44 PM PDT 24 |
403802226 ps |
| T74 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.335264471 |
|
|
Aug 07 05:50:38 PM PDT 24 |
Aug 07 05:50:39 PM PDT 24 |
98325022 ps |
| T931 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2882247161 |
|
|
Aug 07 05:50:42 PM PDT 24 |
Aug 07 05:50:43 PM PDT 24 |
16196978 ps |
| T112 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3582398643 |
|
|
Aug 07 05:50:31 PM PDT 24 |
Aug 07 05:50:32 PM PDT 24 |
178906274 ps |
| T932 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.855586198 |
|
|
Aug 07 05:50:30 PM PDT 24 |
Aug 07 05:50:33 PM PDT 24 |
84214799 ps |
| T87 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1248904345 |
|
|
Aug 07 05:50:48 PM PDT 24 |
Aug 07 05:50:49 PM PDT 24 |
44306412 ps |
| T933 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.307978673 |
|
|
Aug 07 05:50:32 PM PDT 24 |
Aug 07 05:50:37 PM PDT 24 |
244831672 ps |
| T119 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3667427344 |
|
|
Aug 07 05:50:30 PM PDT 24 |
Aug 07 05:50:30 PM PDT 24 |
19155507 ps |
| T934 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1619018246 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:51 PM PDT 24 |
169525718 ps |
| T75 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2567859911 |
|
|
Aug 07 05:50:21 PM PDT 24 |
Aug 07 05:50:22 PM PDT 24 |
145934651 ps |
| T88 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3396047015 |
|
|
Aug 07 05:50:40 PM PDT 24 |
Aug 07 05:50:41 PM PDT 24 |
23399528 ps |
| T89 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1928100623 |
|
|
Aug 07 05:50:42 PM PDT 24 |
Aug 07 05:50:45 PM PDT 24 |
816231323 ps |
| T90 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1829773122 |
|
|
Aug 07 05:50:31 PM PDT 24 |
Aug 07 05:50:33 PM PDT 24 |
896117429 ps |
| T935 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.979367290 |
|
|
Aug 07 05:50:46 PM PDT 24 |
Aug 07 05:50:48 PM PDT 24 |
44060556 ps |
| T137 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.725694069 |
|
|
Aug 07 05:50:52 PM PDT 24 |
Aug 07 05:50:54 PM PDT 24 |
324741249 ps |
| T113 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2875978691 |
|
|
Aug 07 05:50:28 PM PDT 24 |
Aug 07 05:50:29 PM PDT 24 |
11918244 ps |
| T936 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1760672425 |
|
|
Aug 07 05:50:32 PM PDT 24 |
Aug 07 05:50:33 PM PDT 24 |
22032059 ps |
| T937 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2837962413 |
|
|
Aug 07 05:50:29 PM PDT 24 |
Aug 07 05:50:30 PM PDT 24 |
57688680 ps |
| T938 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3305692177 |
|
|
Aug 07 05:50:44 PM PDT 24 |
Aug 07 05:50:45 PM PDT 24 |
27473845 ps |
| T939 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3496296116 |
|
|
Aug 07 05:50:30 PM PDT 24 |
Aug 07 05:50:31 PM PDT 24 |
115171127 ps |
| T940 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1908792889 |
|
|
Aug 07 05:50:25 PM PDT 24 |
Aug 07 05:50:26 PM PDT 24 |
97941106 ps |
| T941 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1474239024 |
|
|
Aug 07 05:50:35 PM PDT 24 |
Aug 07 05:50:35 PM PDT 24 |
36320090 ps |
| T942 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4179832606 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:47 PM PDT 24 |
23587668 ps |
| T91 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1407040508 |
|
|
Aug 07 05:50:32 PM PDT 24 |
Aug 07 05:50:33 PM PDT 24 |
43385804 ps |
| T943 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.122489978 |
|
|
Aug 07 05:50:44 PM PDT 24 |
Aug 07 05:50:45 PM PDT 24 |
158066914 ps |
| T944 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2467144362 |
|
|
Aug 07 05:50:46 PM PDT 24 |
Aug 07 05:50:47 PM PDT 24 |
19561952 ps |
| T92 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1914109681 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:49 PM PDT 24 |
1215870791 ps |
| T945 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.369091065 |
|
|
Aug 07 05:50:33 PM PDT 24 |
Aug 07 05:50:36 PM PDT 24 |
122149041 ps |
| T93 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3552842917 |
|
|
Aug 07 05:50:50 PM PDT 24 |
Aug 07 05:50:51 PM PDT 24 |
38851367 ps |
| T946 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2535151178 |
|
|
Aug 07 05:50:27 PM PDT 24 |
Aug 07 05:50:28 PM PDT 24 |
91541396 ps |
| T947 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1292314375 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:49 PM PDT 24 |
42844273 ps |
| T143 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.987462706 |
|
|
Aug 07 05:50:40 PM PDT 24 |
Aug 07 05:50:42 PM PDT 24 |
1138991944 ps |
| T948 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1423439993 |
|
|
Aug 07 05:50:37 PM PDT 24 |
Aug 07 05:50:38 PM PDT 24 |
53332824 ps |
| T949 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2038848284 |
|
|
Aug 07 05:50:46 PM PDT 24 |
Aug 07 05:50:48 PM PDT 24 |
256996565 ps |
| T94 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3685914753 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:47 PM PDT 24 |
323657203 ps |
| T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2082002528 |
|
|
Aug 07 05:50:37 PM PDT 24 |
Aug 07 05:50:38 PM PDT 24 |
168885111 ps |
| T95 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2881231264 |
|
|
Aug 07 05:50:27 PM PDT 24 |
Aug 07 05:50:29 PM PDT 24 |
43965592 ps |
| T103 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3302609720 |
|
|
Aug 07 05:50:27 PM PDT 24 |
Aug 07 05:50:28 PM PDT 24 |
39952660 ps |
| T951 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2872645990 |
|
|
Aug 07 05:50:37 PM PDT 24 |
Aug 07 05:50:39 PM PDT 24 |
348779440 ps |
| T144 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2228706872 |
|
|
Aug 07 05:50:32 PM PDT 24 |
Aug 07 05:50:33 PM PDT 24 |
81537167 ps |
| T952 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2883071557 |
|
|
Aug 07 05:50:37 PM PDT 24 |
Aug 07 05:50:38 PM PDT 24 |
27269035 ps |
| T953 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4004574604 |
|
|
Aug 07 05:50:40 PM PDT 24 |
Aug 07 05:50:41 PM PDT 24 |
25420653 ps |
| T954 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2658187828 |
|
|
Aug 07 05:50:40 PM PDT 24 |
Aug 07 05:50:42 PM PDT 24 |
33537584 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1257278450 |
|
|
Aug 07 05:50:31 PM PDT 24 |
Aug 07 05:50:32 PM PDT 24 |
58820802 ps |
| T956 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2054143511 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:46 PM PDT 24 |
35948008 ps |
| T957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.322580364 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:48 PM PDT 24 |
259076657 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1434087244 |
|
|
Aug 07 05:50:33 PM PDT 24 |
Aug 07 05:50:35 PM PDT 24 |
28656441 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1544789862 |
|
|
Aug 07 05:50:49 PM PDT 24 |
Aug 07 05:50:51 PM PDT 24 |
108648247 ps |
| T960 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2289615130 |
|
|
Aug 07 05:50:38 PM PDT 24 |
Aug 07 05:50:40 PM PDT 24 |
108747480 ps |
| T141 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2517969944 |
|
|
Aug 07 05:50:27 PM PDT 24 |
Aug 07 05:50:29 PM PDT 24 |
170538337 ps |
| T142 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.936394902 |
|
|
Aug 07 05:50:44 PM PDT 24 |
Aug 07 05:50:46 PM PDT 24 |
664636825 ps |
| T146 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2826978063 |
|
|
Aug 07 05:50:47 PM PDT 24 |
Aug 07 05:50:49 PM PDT 24 |
328469730 ps |
| T961 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1582377267 |
|
|
Aug 07 05:50:31 PM PDT 24 |
Aug 07 05:50:33 PM PDT 24 |
82461702 ps |
| T138 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2405585062 |
|
|
Aug 07 05:50:39 PM PDT 24 |
Aug 07 05:50:41 PM PDT 24 |
1565149270 ps |
| T962 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1173340923 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:47 PM PDT 24 |
573560456 ps |
| T963 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1421303475 |
|
|
Aug 07 05:50:29 PM PDT 24 |
Aug 07 05:50:31 PM PDT 24 |
75060294 ps |
| T964 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2934399069 |
|
|
Aug 07 05:50:39 PM PDT 24 |
Aug 07 05:50:41 PM PDT 24 |
841908147 ps |
| T139 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3751177786 |
|
|
Aug 07 05:50:53 PM PDT 24 |
Aug 07 05:50:54 PM PDT 24 |
183739138 ps |
| T965 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.322420377 |
|
|
Aug 07 05:50:44 PM PDT 24 |
Aug 07 05:50:48 PM PDT 24 |
282517515 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2591744933 |
|
|
Aug 07 05:50:32 PM PDT 24 |
Aug 07 05:50:33 PM PDT 24 |
50816789 ps |
| T967 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1145724266 |
|
|
Aug 07 05:50:41 PM PDT 24 |
Aug 07 05:50:42 PM PDT 24 |
31315955 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.828267908 |
|
|
Aug 07 05:50:49 PM PDT 24 |
Aug 07 05:50:53 PM PDT 24 |
926072354 ps |
| T969 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2824286661 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:46 PM PDT 24 |
19871896 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1318600594 |
|
|
Aug 07 05:50:27 PM PDT 24 |
Aug 07 05:50:29 PM PDT 24 |
41188015 ps |
| T971 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1873788311 |
|
|
Aug 07 05:50:43 PM PDT 24 |
Aug 07 05:50:45 PM PDT 24 |
41180456 ps |
| T140 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.898189543 |
|
|
Aug 07 05:50:30 PM PDT 24 |
Aug 07 05:50:32 PM PDT 24 |
269417576 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3602584863 |
|
|
Aug 07 05:50:28 PM PDT 24 |
Aug 07 05:50:29 PM PDT 24 |
38351017 ps |
| T973 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3576693086 |
|
|
Aug 07 05:50:46 PM PDT 24 |
Aug 07 05:50:46 PM PDT 24 |
17771855 ps |
| T145 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2850115073 |
|
|
Aug 07 05:50:37 PM PDT 24 |
Aug 07 05:50:39 PM PDT 24 |
627192153 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1988087641 |
|
|
Aug 07 05:50:23 PM PDT 24 |
Aug 07 05:50:23 PM PDT 24 |
22376794 ps |
| T975 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1136368997 |
|
|
Aug 07 05:50:30 PM PDT 24 |
Aug 07 05:50:33 PM PDT 24 |
364100045 ps |
| T104 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2598118422 |
|
|
Aug 07 05:50:33 PM PDT 24 |
Aug 07 05:50:34 PM PDT 24 |
15018482 ps |
| T149 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2084527218 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:47 PM PDT 24 |
262166661 ps |
| T976 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3015193882 |
|
|
Aug 07 05:50:36 PM PDT 24 |
Aug 07 05:50:38 PM PDT 24 |
42055461 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2758307590 |
|
|
Aug 07 05:50:28 PM PDT 24 |
Aug 07 05:50:30 PM PDT 24 |
19921445 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1689342361 |
|
|
Aug 07 05:50:32 PM PDT 24 |
Aug 07 05:50:35 PM PDT 24 |
132339155 ps |
| T979 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3918575213 |
|
|
Aug 07 05:50:43 PM PDT 24 |
Aug 07 05:50:48 PM PDT 24 |
1554133104 ps |
| T980 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1885630456 |
|
|
Aug 07 05:50:44 PM PDT 24 |
Aug 07 05:50:46 PM PDT 24 |
203646438 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3780786088 |
|
|
Aug 07 05:50:36 PM PDT 24 |
Aug 07 05:50:36 PM PDT 24 |
37882609 ps |
| T982 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1479928175 |
|
|
Aug 07 05:50:48 PM PDT 24 |
Aug 07 05:50:52 PM PDT 24 |
1037222009 ps |
| T983 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4276524036 |
|
|
Aug 07 05:50:30 PM PDT 24 |
Aug 07 05:50:31 PM PDT 24 |
49483009 ps |
| T984 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1636270149 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:47 PM PDT 24 |
167541883 ps |
| T147 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2048839928 |
|
|
Aug 07 05:50:38 PM PDT 24 |
Aug 07 05:50:41 PM PDT 24 |
208542785 ps |
| T985 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2294606125 |
|
|
Aug 07 05:50:37 PM PDT 24 |
Aug 07 05:50:39 PM PDT 24 |
158357156 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2219128756 |
|
|
Aug 07 05:50:33 PM PDT 24 |
Aug 07 05:50:34 PM PDT 24 |
23216917 ps |
| T986 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.899287760 |
|
|
Aug 07 05:50:40 PM PDT 24 |
Aug 07 05:50:42 PM PDT 24 |
148059716 ps |
| T987 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2314240509 |
|
|
Aug 07 05:50:46 PM PDT 24 |
Aug 07 05:50:49 PM PDT 24 |
45486194 ps |
| T988 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.356376634 |
|
|
Aug 07 05:50:36 PM PDT 24 |
Aug 07 05:50:37 PM PDT 24 |
20040710 ps |
| T989 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1675839878 |
|
|
Aug 07 05:50:37 PM PDT 24 |
Aug 07 05:50:38 PM PDT 24 |
67445915 ps |
| T148 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3116076800 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:48 PM PDT 24 |
252840682 ps |
| T106 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1833621901 |
|
|
Aug 07 05:50:47 PM PDT 24 |
Aug 07 05:50:50 PM PDT 24 |
3893287082 ps |
| T990 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1093421197 |
|
|
Aug 07 05:50:38 PM PDT 24 |
Aug 07 05:50:38 PM PDT 24 |
77725384 ps |
| T991 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.14596346 |
|
|
Aug 07 05:50:38 PM PDT 24 |
Aug 07 05:50:40 PM PDT 24 |
223785255 ps |
| T107 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3907220214 |
|
|
Aug 07 05:50:27 PM PDT 24 |
Aug 07 05:50:28 PM PDT 24 |
65666920 ps |
| T992 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1860163382 |
|
|
Aug 07 05:50:48 PM PDT 24 |
Aug 07 05:50:49 PM PDT 24 |
55585197 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2170505807 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:46 PM PDT 24 |
77977400 ps |
| T994 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3591622433 |
|
|
Aug 07 05:50:45 PM PDT 24 |
Aug 07 05:50:49 PM PDT 24 |
1604361561 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2429981292 |
|
|
Aug 07 05:50:30 PM PDT 24 |
Aug 07 05:50:32 PM PDT 24 |
237806285 ps |
| T108 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3182557854 |
|
|
Aug 07 05:50:48 PM PDT 24 |
Aug 07 05:50:52 PM PDT 24 |
1684320701 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2377669158 |
|
|
Aug 07 05:50:36 PM PDT 24 |
Aug 07 05:50:37 PM PDT 24 |
32812691 ps |
| T997 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3393437023 |
|
|
Aug 07 05:50:46 PM PDT 24 |
Aug 07 05:50:47 PM PDT 24 |
28526529 ps |
| T998 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.901393915 |
|
|
Aug 07 05:50:35 PM PDT 24 |
Aug 07 05:50:36 PM PDT 24 |
43266598 ps |
| T999 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.651408647 |
|
|
Aug 07 05:50:41 PM PDT 24 |
Aug 07 05:50:44 PM PDT 24 |
472353423 ps |
| T1000 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1663092998 |
|
|
Aug 07 05:50:46 PM PDT 24 |
Aug 07 05:50:47 PM PDT 24 |
19099970 ps |