Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13923166	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59115716

1

T1

16384

T2

657858

T3

200871

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36410645	1			T1	8192		T2	358868		T3	110874
values[0x0]	16920921	1			T1	4117		T2	173956		T3	53025
values[0x1]	19707316	1			T1	4075		T2	184856		T3	57114

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6935856	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66103026

1

T1

16384

T2

687943

T3

210959

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	257210	1			T1	56		T2	2797		T3	926
valid_sources[0x01]	265389	1			T1	63		T2	2811		T3	725
valid_sources[0x02]	318416	1			T1	72		T2	2780		T3	909
valid_sources[0x03]	310826	1			T1	66		T2	2857		T3	779
valid_sources[0x04]	316099	1			T1	65		T2	2911		T3	1081
valid_sources[0x05]	258631	1			T1	59		T2	2813		T3	944
valid_sources[0x06]	266566	1			T1	60		T2	2782		T3	752
valid_sources[0x07]	276060	1			T1	63		T2	2774		T3	732
valid_sources[0x08]	302050	1			T1	57		T2	2885		T3	1070
valid_sources[0x09]	278302	1			T1	68		T2	2730		T3	1140
valid_sources[0x0a]	278565	1			T1	64		T2	2751		T3	1057
valid_sources[0x0b]	301954	1			T1	69		T2	2817		T3	785
valid_sources[0x0c]	272899	1			T1	61		T2	2785		T3	922
valid_sources[0x0d]	259455	1			T1	70		T2	2834		T3	776
valid_sources[0x0e]	308179	1			T1	63		T2	2791		T3	933
valid_sources[0x0f]	266441	1			T1	62		T2	2762		T3	964
valid_sources[0x10]	270602	1			T1	74		T2	2710		T3	985
valid_sources[0x11]	297929	1			T1	56		T2	2745		T3	1078
valid_sources[0x12]	285963	1			T1	65		T2	2825		T3	727
valid_sources[0x13]	261219	1			T1	68		T2	2783		T3	895
valid_sources[0x14]	287966	1			T1	74		T2	2731		T3	1021
valid_sources[0x15]	258540	1			T1	60		T2	2868		T3	651
valid_sources[0x16]	268877	1			T1	64		T2	2802		T3	783
valid_sources[0x17]	263221	1			T1	79		T2	2779		T3	853
valid_sources[0x18]	335212	1			T1	50		T2	2785		T3	1148
valid_sources[0x19]	301183	1			T1	60		T2	2802		T3	771
valid_sources[0x1a]	307487	1			T1	65		T2	2829		T3	1028
valid_sources[0x1b]	285422	1			T1	67		T2	2882		T3	763
valid_sources[0x1c]	261572	1			T1	63		T2	2771		T3	798
valid_sources[0x1d]	349997	1			T1	56		T2	2778		T3	948
valid_sources[0x1e]	274562	1			T1	71		T2	2713		T3	887
valid_sources[0x1f]	286674	1			T1	71		T2	2778		T3	607
valid_sources[0x20]	341609	1			T1	59		T2	2814		T3	752
valid_sources[0x21]	260498	1			T1	60		T2	2897		T3	943
valid_sources[0x22]	310237	1			T1	68		T2	2716		T3	872
valid_sources[0x23]	284106	1			T1	67		T2	2809		T3	916
valid_sources[0x24]	275376	1			T1	68		T2	2869		T3	1043
valid_sources[0x25]	281200	1			T1	58		T2	2742		T3	813
valid_sources[0x26]	296251	1			T1	80		T2	2800		T3	1035
valid_sources[0x27]	260474	1			T1	54		T2	2766		T3	949
valid_sources[0x28]	261977	1			T1	60		T2	2741		T3	746
valid_sources[0x29]	277417	1			T1	61		T2	2662		T3	732
valid_sources[0x2a]	277369	1			T1	70		T2	2902		T3	551
valid_sources[0x2b]	307815	1			T1	59		T2	2837		T3	617
valid_sources[0x2c]	268177	1			T1	66		T2	2710		T3	764
valid_sources[0x2d]	268504	1			T1	56		T2	2800		T3	735
valid_sources[0x2e]	282439	1			T1	61		T2	2788		T3	670
valid_sources[0x2f]	273566	1			T1	69		T2	2809		T3	1189
valid_sources[0x30]	266470	1			T1	45		T2	2797		T3	1009
valid_sources[0x31]	290709	1			T1	66		T2	2856		T3	827
valid_sources[0x32]	254222	1			T1	76		T2	2900		T3	1037
valid_sources[0x33]	256726	1			T1	55		T2	2923		T3	754
valid_sources[0x34]	293950	1			T1	76		T2	2790		T3	857
valid_sources[0x35]	274659	1			T1	77		T2	2885		T3	741
valid_sources[0x36]	284750	1			T1	58		T2	2815		T3	849
valid_sources[0x37]	278686	1			T1	60		T2	2814		T3	708
valid_sources[0x38]	260159	1			T1	54		T2	2890		T3	974
valid_sources[0x39]	269755	1			T1	61		T2	2788		T3	827
valid_sources[0x3a]	261771	1			T1	63		T2	2922		T3	966
valid_sources[0x3b]	313457	1			T1	60		T2	2836		T3	742
valid_sources[0x3c]	314323	1			T1	65		T2	2779		T3	824
valid_sources[0x3d]	285710	1			T1	79		T2	2740		T3	711
valid_sources[0x3e]	279418	1			T1	62		T2	2858		T3	879
valid_sources[0x3f]	257990	1			T1	75		T2	2780		T3	804
valid_sources[0x40]	258098	1			T1	75		T2	2712		T3	934
valid_sources[0x41]	268342	1			T1	54		T2	2838		T3	775
valid_sources[0x42]	287973	1			T1	60		T2	2708		T3	869
valid_sources[0x43]	284545	1			T1	46		T2	2821		T3	1058
valid_sources[0x44]	294778	1			T1	64		T2	2771		T3	868
valid_sources[0x45]	303191	1			T1	65		T2	2798		T3	837
valid_sources[0x46]	293897	1			T1	55		T2	2842		T3	1031
valid_sources[0x47]	313197	1			T1	64		T2	2797		T3	743
valid_sources[0x48]	317855	1			T1	69		T2	2767		T3	601
valid_sources[0x49]	294887	1			T1	56		T2	2837		T3	817
valid_sources[0x4a]	267031	1			T1	59		T2	2779		T3	786
valid_sources[0x4b]	285804	1			T1	66		T2	2845		T3	854
valid_sources[0x4c]	332127	1			T1	68		T2	2808		T3	763
valid_sources[0x4d]	302710	1			T1	76		T2	2810		T3	1162
valid_sources[0x4e]	265473	1			T1	68		T2	2860		T3	878
valid_sources[0x4f]	271031	1			T1	63		T2	2873		T3	662
valid_sources[0x50]	285161	1			T1	45		T2	2732		T3	852
valid_sources[0x51]	289653	1			T1	67		T2	2779		T3	1140
valid_sources[0x52]	322657	1			T1	67		T2	2780		T3	819
valid_sources[0x53]	316633	1			T1	74		T2	2754		T3	908
valid_sources[0x54]	262867	1			T1	68		T2	2827		T3	864
valid_sources[0x55]	268846	1			T1	53		T2	2823		T3	855
valid_sources[0x56]	374609	1			T1	65		T2	2869		T3	942
valid_sources[0x57]	308001	1			T1	67		T2	2953		T3	1058
valid_sources[0x58]	269449	1			T1	54		T2	2714		T3	867
valid_sources[0x59]	270146	1			T1	59		T2	2740		T3	818
valid_sources[0x5a]	292532	1			T1	58		T2	2787		T3	1025
valid_sources[0x5b]	280950	1			T1	59		T2	2803		T3	1109
valid_sources[0x5c]	263814	1			T1	54		T2	2763		T3	819
valid_sources[0x5d]	311407	1			T1	77		T2	2840		T3	713
valid_sources[0x5e]	258270	1			T1	72		T2	2766		T3	893
valid_sources[0x5f]	259328	1			T1	74		T2	2853		T3	779
valid_sources[0x60]	287661	1			T1	64		T2	2821		T3	828
valid_sources[0x61]	276800	1			T1	57		T2	2775		T3	801
valid_sources[0x62]	277740	1			T1	64		T2	2775		T3	635
valid_sources[0x63]	268656	1			T1	74		T2	2795		T3	684
valid_sources[0x64]	359433	1			T1	60		T2	2762		T3	762
valid_sources[0x65]	280401	1			T1	63		T2	2749		T3	589
valid_sources[0x66]	262154	1			T1	53		T2	2824		T3	816
valid_sources[0x67]	313382	1			T1	61		T2	2833		T3	776
valid_sources[0x68]	288519	1			T1	48		T2	2902		T3	1128
valid_sources[0x69]	282077	1			T1	80		T2	2868		T3	863
valid_sources[0x6a]	337877	1			T1	72		T2	2868		T3	1067
valid_sources[0x6b]	295747	1			T1	75		T2	2862		T3	768
valid_sources[0x6c]	278101	1			T1	59		T2	2708		T3	1005
valid_sources[0x6d]	272343	1			T1	78		T2	2796		T3	839
valid_sources[0x6e]	275131	1			T1	55		T2	2899		T3	1067
valid_sources[0x6f]	274887	1			T1	67		T2	2894		T3	1096
valid_sources[0x70]	272583	1			T1	66		T2	2768		T3	714
valid_sources[0x71]	261347	1			T1	65		T2	2687		T3	947
valid_sources[0x72]	251420	1			T1	55		T2	2777		T3	651
valid_sources[0x73]	270623	1			T1	66		T2	2693		T3	969
valid_sources[0x74]	254178	1			T1	59		T2	2692		T3	955
valid_sources[0x75]	296358	1			T1	75		T2	2788		T3	1048
valid_sources[0x76]	261501	1			T1	76		T2	2709		T3	774
valid_sources[0x77]	296394	1			T1	65		T2	2768		T3	903
valid_sources[0x78]	274549	1			T1	67		T2	2822		T3	792
valid_sources[0x79]	264617	1			T1	59		T2	2810		T3	735
valid_sources[0x7a]	263022	1			T1	56		T2	2838		T3	848
valid_sources[0x7b]	263140	1			T1	69		T2	2795		T3	795
valid_sources[0x7c]	304561	1			T1	57		T2	2771		T3	806
valid_sources[0x7d]	333135	1			T1	65		T2	2744		T3	768
valid_sources[0x7e]	277947	1			T1	65		T2	2800		T3	667
valid_sources[0x7f]	279390	1			T1	67		T2	2788		T3	731
valid_sources[0x80]	294488	1			T1	51		T2	2722		T3	719

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29452066

1

T1

8192

T2

329013

T3

100733

values[0x0]

all_enables

biggest_size

14832406

1

T1

4117

T2

165021

T3

50074

values[0x1]

all_enables

biggest_size

14831244

1

T1

4075

T2

163824

T3

50064

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36241	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

141637

1

T1

3

T2

67

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51082	1			T2	52		T7	936		T9	417
values[0x0]	60939	1			T1	5		T2	94		T3	8
values[0x1]	65857	1			T1	3		T2	96		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27426	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150452

1

T1

3

T2

92

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	644	1			T3	8		T7	15		T36	1
valid_sources[0x01]	655	1			T7	18		T9	80		T10	1
valid_sources[0x02]	516	1			T2	1		T7	13		T13	3
valid_sources[0x03]	930	1			T2	1		T7	7		T9	3
valid_sources[0x04]	541	1			T2	2		T7	14		T8	1
valid_sources[0x05]	813	1			T3	2		T7	14		T9	57
valid_sources[0x06]	763	1			T2	1		T7	11		T37	1
valid_sources[0x07]	472	1			T7	4		T9	4		T21	15
valid_sources[0x08]	526	1			T7	17		T11	6		T62	2
valid_sources[0x09]	742	1			T2	2		T7	18		T9	1
valid_sources[0x0a]	716	1			T1	1		T2	1		T7	11
valid_sources[0x0b]	703	1			T7	11		T8	1		T9	1
valid_sources[0x0c]	661	1			T2	1		T3	1		T7	18
valid_sources[0x0d]	875	1			T2	2		T7	14		T142	1
valid_sources[0x0e]	1093	1			T2	1		T7	19		T80	2
valid_sources[0x0f]	527	1			T2	1		T7	11		T9	2
valid_sources[0x10]	530	1			T2	1		T7	17		T10	3
valid_sources[0x11]	786	1			T2	3		T7	14		T81	1
valid_sources[0x12]	650	1			T7	19		T21	8		T145	2
valid_sources[0x13]	912	1			T7	9		T9	1		T19	2
valid_sources[0x14]	951	1			T2	1		T7	12		T9	3
valid_sources[0x15]	775	1			T2	2		T7	17		T9	94
valid_sources[0x16]	895	1			T2	4		T7	12		T78	1
valid_sources[0x17]	746	1			T2	1		T7	14		T21	7
valid_sources[0x18]	488	1			T2	2		T7	20		T62	1
valid_sources[0x19]	527	1			T2	1		T7	9		T142	1
valid_sources[0x1a]	644	1			T1	1		T2	1		T7	19
valid_sources[0x1b]	699	1			T7	16		T9	2		T21	13
valid_sources[0x1c]	792	1			T2	1		T7	9		T36	1
valid_sources[0x1d]	579	1			T7	7		T63	14		T21	7
valid_sources[0x1e]	496	1			T2	1		T7	17		T21	11
valid_sources[0x1f]	557	1			T7	15		T76	1		T21	13
valid_sources[0x20]	1026	1			T7	8		T21	13		T146	2
valid_sources[0x21]	798	1			T2	2		T7	16		T10	2
valid_sources[0x22]	489	1			T2	1		T7	12		T9	1
valid_sources[0x23]	783	1			T7	8		T19	1		T21	11
valid_sources[0x24]	676	1			T2	2		T7	11		T36	1
valid_sources[0x25]	1071	1			T2	1		T7	16		T62	1
valid_sources[0x26]	827	1			T2	1		T7	13		T62	1
valid_sources[0x27]	799	1			T7	14		T142	1		T21	10
valid_sources[0x28]	742	1			T2	1		T4	1		T7	18
valid_sources[0x29]	692	1			T2	2		T7	18		T62	1
valid_sources[0x2a]	674	1			T2	1		T7	7		T62	1
valid_sources[0x2b]	662	1			T2	1		T7	8		T19	1
valid_sources[0x2c]	477	1			T2	1		T7	8		T78	1
valid_sources[0x2d]	608	1			T2	1		T7	11		T9	1
valid_sources[0x2e]	650	1			T2	1		T7	14		T21	9
valid_sources[0x2f]	782	1			T2	2		T7	10		T9	2
valid_sources[0x30]	623	1			T2	1		T7	9		T36	1
valid_sources[0x31]	768	1			T2	1		T7	8		T10	5
valid_sources[0x32]	639	1			T7	19		T21	12		T146	1
valid_sources[0x33]	583	1			T2	1		T7	14		T21	10
valid_sources[0x34]	470	1			T2	2		T7	8		T13	2
valid_sources[0x35]	684	1			T2	1		T7	29		T10	1
valid_sources[0x36]	688	1			T2	1		T7	16		T36	1
valid_sources[0x37]	721	1			T7	17		T10	1		T62	1
valid_sources[0x38]	653	1			T2	1		T7	13		T21	4
valid_sources[0x39]	523	1			T2	1		T7	15		T21	14
valid_sources[0x3a]	694	1			T2	2		T7	13		T81	1
valid_sources[0x3b]	636	1			T2	1		T7	19		T19	1
valid_sources[0x3c]	523	1			T2	1		T7	18		T67	4
valid_sources[0x3d]	764	1			T2	5		T7	13		T21	7
valid_sources[0x3e]	666	1			T2	2		T7	10		T9	1
valid_sources[0x3f]	720	1			T7	13		T81	1		T37	1
valid_sources[0x40]	657	1			T2	1		T7	12		T10	1
valid_sources[0x41]	601	1			T7	17		T21	14		T30	2
valid_sources[0x42]	522	1			T7	12		T35	1		T21	11
valid_sources[0x43]	581	1			T3	3		T7	14		T67	15
valid_sources[0x44]	828	1			T7	16		T81	1		T21	10
valid_sources[0x45]	649	1			T7	18		T142	1		T79	2
valid_sources[0x46]	558	1			T2	1		T7	16		T21	10
valid_sources[0x47]	957	1			T7	13		T10	2		T142	1
valid_sources[0x48]	641	1			T2	1		T7	18		T9	2
valid_sources[0x49]	687	1			T7	13		T21	15		T147	1
valid_sources[0x4a]	809	1			T2	1		T7	8		T21	7
valid_sources[0x4b]	683	1			T2	1		T7	12		T142	1
valid_sources[0x4c]	862	1			T2	1		T7	18		T9	297
valid_sources[0x4d]	733	1			T7	18		T76	10		T21	8
valid_sources[0x4e]	1080	1			T7	21		T21	8		T30	2
valid_sources[0x4f]	471	1			T7	17		T62	1		T36	1
valid_sources[0x50]	584	1			T7	14		T10	1		T11	3
valid_sources[0x51]	586	1			T2	1		T3	4		T7	13
valid_sources[0x52]	894	1			T7	16		T8	1		T9	1
valid_sources[0x53]	667	1			T2	2		T7	7		T11	1
valid_sources[0x54]	666	1			T2	3		T7	8		T10	1
valid_sources[0x55]	858	1			T2	3		T7	14		T19	1
valid_sources[0x56]	540	1			T2	1		T7	13		T10	1
valid_sources[0x57]	486	1			T2	1		T7	10		T9	10
valid_sources[0x58]	632	1			T2	2		T7	13		T21	17
valid_sources[0x59]	715	1			T7	12		T9	3		T62	3
valid_sources[0x5a]	907	1			T7	19		T21	15		T68	4
valid_sources[0x5b]	740	1			T7	16		T21	13		T90	3
valid_sources[0x5c]	530	1			T2	2		T7	11		T9	1
valid_sources[0x5d]	599	1			T2	1		T7	20		T13	1
valid_sources[0x5e]	589	1			T7	8		T21	10		T32	1
valid_sources[0x5f]	492	1			T2	1		T7	20		T10	2
valid_sources[0x60]	799	1			T7	9		T9	4		T10	2
valid_sources[0x61]	658	1			T7	11		T62	2		T142	1
valid_sources[0x62]	745	1			T2	1		T7	12		T63	5
valid_sources[0x63]	1014	1			T7	10		T35	1		T21	8
valid_sources[0x64]	861	1			T2	2		T7	16		T19	1
valid_sources[0x65]	938	1			T7	16		T9	2		T81	1
valid_sources[0x66]	491	1			T2	1		T7	12		T21	17
valid_sources[0x67]	724	1			T7	9		T9	2		T21	9
valid_sources[0x68]	996	1			T7	10		T62	1		T21	9
valid_sources[0x69]	566	1			T2	2		T7	11		T21	11
valid_sources[0x6a]	609	1			T7	18		T21	10		T145	13
valid_sources[0x6b]	566	1			T2	1		T7	17		T8	1
valid_sources[0x6c]	510	1			T2	1		T7	15		T142	1
valid_sources[0x6d]	710	1			T2	1		T7	15		T9	1
valid_sources[0x6e]	753	1			T2	1		T7	7		T8	1
valid_sources[0x6f]	576	1			T2	2		T7	23		T21	9
valid_sources[0x70]	876	1			T2	1		T7	14		T9	5
valid_sources[0x71]	545	1			T4	1		T7	14		T62	1
valid_sources[0x72]	634	1			T2	1		T7	12		T21	10
valid_sources[0x73]	804	1			T2	1		T7	14		T11	1
valid_sources[0x74]	809	1			T2	2		T7	15		T9	1
valid_sources[0x75]	588	1			T7	15		T9	1		T148	1
valid_sources[0x76]	601	1			T2	1		T7	11		T62	1
valid_sources[0x77]	708	1			T7	22		T10	1		T34	15
valid_sources[0x78]	1010	1			T2	1		T7	6		T62	1
valid_sources[0x79]	815	1			T2	2		T7	15		T9	1
valid_sources[0x7a]	542	1			T7	19		T9	11		T63	32
valid_sources[0x7b]	797	1			T2	5		T7	18		T5	77
valid_sources[0x7c]	826	1			T7	16		T10	3		T52	1
valid_sources[0x7d]	635	1			T7	16		T11	9		T62	1
valid_sources[0x7e]	504	1			T2	1		T7	13		T76	2
valid_sources[0x7f]	569	1			T2	3		T7	11		T8	1
valid_sources[0x80]	772	1			T2	1		T7	17		T62	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38584

1

T2

19

T7

865

T9

377

values[0x0]

all_enables

biggest_size

52400

1

T1

3

T2

30

T3

1

values[0x1]

all_enables

biggest_size

50653

1

T2

18

T7

1204

T8

1