Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13621218

1

T2

53064

T3

20142

T4

161585

full_word

54094151

1

T1

16384

T2

591225

T3

200871

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67715099	1			T1	16384		T2	644289		T3	221013
auto[TlIntgErrCmd]	94	1			T56	2		T57	3		T58	3
auto[TlIntgErrData]	85	1			T56	3		T57	4		T58	5
auto[TlIntgErrBoth]	91	1			T56	5		T57	3		T58	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31021713

1

T1

8192

T2

287199

T3

110874

auto[1]

36693656

1

T1

8192

T2

357090

T3

110139

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6505106	1			T2	23244		T3	10141		T4	80720
auto[TlIntgErrNone]	partial	auto[1]	7115865	1			T2	29820		T3	10001		T4	80865
auto[TlIntgErrNone]	full_word	auto[0]	24516484	1			T1	8192		T2	263955		T3	100733
auto[TlIntgErrNone]	full_word	auto[1]	29577644	1			T1	8192		T2	327270		T3	100138
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T56	1		T57	1		T131	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T56	1		T57	1		T58	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T57	1		T58	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T57	3		T58	2		T131	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T56	3		T57	1		T58	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T133	1		T134	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T135	1		T134	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T56	2		T57	1		T58	2
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T56	3		T57	1		T131	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T57	1		T131	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T135	2		T133	2		T138	1