Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	718839	1			T2	715		T3	18529		T4	4223
auto[1]	9977135	1			T2	5898		T3	4215		T4	11759
auto[2]	578615	1			T2	414		T3	16932		T4	3035
auto[3]	9839320	1			T2	5666		T3	2498		T4	10563

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13291561	1			T2	9003		T3	32534		T4	487
auto[1]	2054185	1			T2	1350		T3	4601		T4	3106
auto[2]	2060579	1			T2	2084		T3	4482		T4	4095
auto[3]	3707584	1			T2	256		T3	557		T4	21892

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7784595

1

T2

12678

T3

42138

T4

6

auto[1]

13329314

1

T2

15

T3

36

T4

29574

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	271511	1			T2	591		T3	15212		T10	1068
auto[0]	auto[0]	auto[1]	27552	1			T2	61		T3	1568		T10	86
auto[0]	auto[0]	auto[2]	27641	1			T2	57		T3	1585		T10	96
auto[0]	auto[0]	auto[3]	7212	1			T2	6		T3	147		T4	2
auto[0]	auto[1]	auto[0]	2937939	1			T2	4460		T3	2269		T7	420
auto[0]	auto[1]	auto[1]	308481	1			T2	900		T3	1551		T4	1
auto[0]	auto[1]	auto[2]	295089	1			T2	424		T3	238		T7	34
auto[0]	auto[1]	auto[3]	63745	1			T2	109		T3	156		T4	2
auto[0]	auto[2]	auto[0]	228099	1			T3	14067		T10	970		T11	544
auto[0]	auto[2]	auto[1]	23228	1			T3	1376		T10	88		T11	53
auto[0]	auto[2]	auto[2]	27602	1			T2	379		T3	1341		T10	79
auto[0]	auto[2]	auto[3]	6224	1			T2	33		T3	131		T4	1
auto[0]	auto[3]	auto[0]	2896252	1			T2	3944		T3	957		T7	411
auto[0]	auto[3]	auto[1]	290785	1			T2	388		T3	104		T7	40
auto[0]	auto[3]	auto[2]	307743	1			T2	1218		T3	1313		T7	30
auto[0]	auto[3]	auto[3]	65492	1			T2	108		T3	123		T7	3
auto[1]	auto[0]	auto[0]	13036	1			T3	14		T4	143		T11	1
auto[1]	auto[0]	auto[1]	56920	1			T4	652		T78	4194		T144	1
auto[1]	auto[0]	auto[2]	56890	1			T3	3		T4	616		T10	1
auto[1]	auto[0]	auto[3]	258077	1			T4	2810		T78	18763		T143	2184
auto[1]	auto[1]	auto[0]	3469367	1			T2	5		T4	239		T11	1
auto[1]	auto[1]	auto[1]	670041	1			T3	1		T4	1902		T10	1
auto[1]	auto[1]	auto[2]	646219	1			T4	1107		T35	2		T49	2
auto[1]	auto[1]	auto[3]	1586254	1			T4	8508		T104	692		T77	53418
auto[1]	auto[2]	auto[0]	10157	1			T3	15		T10	1		T142	3
auto[1]	auto[2]	auto[1]	44150	1			T3	1		T10	1		T11	1
auto[1]	auto[2]	auto[2]	43131	1			T2	2		T3	1		T4	549
auto[1]	auto[2]	auto[3]	196024	1			T4	2485		T142	1		T78	12332
auto[1]	auto[3]	auto[0]	3465200	1			T2	3		T4	105		T11	1
auto[1]	auto[3]	auto[1]	633028	1			T2	1		T4	551		T49	1
auto[1]	auto[3]	auto[2]	656264	1			T2	4		T3	1		T4	1823
auto[1]	auto[3]	auto[3]	1524556	1			T4	8084		T104	745		T77	53733