Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	316479729	213504	0	0
ctrl_regwen_rd_A	316479729	4532	0	0
exec_rd_A	316479729	4167	0	0
exec_regwen_rd_A	316479729	4340	0	0
readback_rd_A	316479729	3022	0	0
readback_regwen_rd_A	316479729	2743	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316479729	213504	0	0
T7	150190	7238	0	0
T8	65174	0	0	0
T9	51484	2740	0	0
T10	121687	0	0	0
T11	141127	0	0	0
T12	1841	0	0	0
T21	0	2939	0	0
T34	215423	0	0	0
T35	14672	0	0	0
T39	0	2929	0	0
T42	0	7886	0	0
T49	246302	0	0	0
T50	0	3497	0	0
T52	7048	0	0	0
T54	0	6322	0	0
T64	0	1621	0	0
T65	0	7431	0	0
T66	0	1239	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316479729	4532	0	0
T43	0	153	0	0
T111	29573	73	0	0
T112	0	56	0	0
T113	0	165	0	0
T114	0	150	0	0
T115	0	284	0	0
T116	0	95	0	0
T117	0	296	0	0
T118	0	206	0	0
T119	0	298	0	0
T120	2262	0	0	0
T121	176470	0	0	0
T122	11602	0	0	0
T123	94336	0	0	0
T124	14758	0	0	0
T125	115912	0	0	0
T126	182172	0	0	0
T127	519410	0	0	0
T128	10234	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316479729	4167	0	0
T43	0	114	0	0
T111	29573	56	0	0
T112	0	74	0	0
T113	0	143	0	0
T114	0	89	0	0
T115	0	335	0	0
T116	0	114	0	0
T117	0	332	0	0
T118	0	163	0	0
T119	0	251	0	0
T120	2262	0	0	0
T121	176470	0	0	0
T122	11602	0	0	0
T123	94336	0	0	0
T124	14758	0	0	0
T125	115912	0	0	0
T126	182172	0	0	0
T127	519410	0	0	0
T128	10234	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316479729	4340	0	0
T43	0	105	0	0
T111	29573	73	0	0
T112	0	64	0	0
T113	0	107	0	0
T114	0	116	0	0
T115	0	298	0	0
T116	0	104	0	0
T117	0	423	0	0
T118	0	146	0	0
T119	0	351	0	0
T120	2262	0	0	0
T121	176470	0	0	0
T122	11602	0	0	0
T123	94336	0	0	0
T124	14758	0	0	0
T125	115912	0	0	0
T126	182172	0	0	0
T127	519410	0	0	0
T128	10234	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316479729	3022	0	0
T43	0	123	0	0
T111	29573	61	0	0
T112	0	30	0	0
T113	0	105	0	0
T114	0	95	0	0
T115	0	322	0	0
T116	0	72	0	0
T117	0	286	0	0
T118	0	134	0	0
T119	0	323	0	0
T120	2262	0	0	0
T121	176470	0	0	0
T122	11602	0	0	0
T123	94336	0	0	0
T124	14758	0	0	0
T125	115912	0	0	0
T126	182172	0	0	0
T127	519410	0	0	0
T128	10234	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316479729	2743	0	0
T43	0	129	0	0
T111	29573	57	0	0
T112	0	29	0	0
T113	0	130	0	0
T114	0	143	0	0
T115	0	273	0	0
T116	0	83	0	0
T117	0	277	0	0
T118	0	188	0	0
T119	0	296	0	0
T120	2262	0	0	0
T121	176470	0	0	0
T122	11602	0	0	0
T123	94336	0	0	0
T124	14758	0	0	0
T125	115912	0	0	0
T126	182172	0	0	0
T127	519410	0	0	0
T128	10234	0	0	0