Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13852294	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

60949758

1

T1

120

T2

80670

T3

227672

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37288655	1			T1	64		T2	38528		T3	124818
values[0x0]	17372504	1			T1	37		T2	21849		T3	60505
values[0x1]	20140893	1			T1	37		T2	22482		T3	64819

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6903560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67898492

1

T1

127

T2

81765

T3

238898

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	295478	1			T2	304		T3	744		T4	919
valid_sources[0x01]	264084	1			T2	312		T3	952		T4	885
valid_sources[0x02]	294021	1			T2	336		T3	1001		T4	987
valid_sources[0x03]	303732	1			T2	322		T3	803		T4	945
valid_sources[0x04]	309386	1			T2	304		T3	1262		T4	981
valid_sources[0x05]	304941	1			T1	7		T2	325		T3	932
valid_sources[0x06]	275501	1			T2	277		T3	980		T4	1002
valid_sources[0x07]	263486	1			T2	362		T3	924		T4	1013
valid_sources[0x08]	315612	1			T2	307		T3	934		T4	913
valid_sources[0x09]	265534	1			T1	2		T2	338		T3	777
valid_sources[0x0a]	330224	1			T2	351		T3	1049		T4	884
valid_sources[0x0b]	284398	1			T2	328		T3	1038		T4	987
valid_sources[0x0c]	310213	1			T2	308		T3	1088		T4	997
valid_sources[0x0d]	307513	1			T2	329		T3	1225		T4	889
valid_sources[0x0e]	267636	1			T2	313		T3	939		T4	921
valid_sources[0x0f]	368786	1			T1	6		T2	308		T3	848
valid_sources[0x10]	296554	1			T1	1		T2	324		T3	946
valid_sources[0x11]	292500	1			T1	2		T2	300		T3	891
valid_sources[0x12]	326210	1			T2	329		T3	1113		T4	880
valid_sources[0x13]	360540	1			T2	328		T3	905		T4	972
valid_sources[0x14]	302767	1			T2	339		T3	1146		T4	955
valid_sources[0x15]	279313	1			T2	326		T3	1117		T4	948
valid_sources[0x16]	498783	1			T1	1		T2	315		T3	1261
valid_sources[0x17]	255391	1			T2	340		T3	954		T4	873
valid_sources[0x18]	311480	1			T2	296		T3	924		T4	975
valid_sources[0x19]	259084	1			T2	341		T3	889		T4	941
valid_sources[0x1a]	258497	1			T1	1		T2	330		T3	1131
valid_sources[0x1b]	290887	1			T2	324		T3	878		T4	995
valid_sources[0x1c]	303569	1			T1	2		T2	329		T3	935
valid_sources[0x1d]	309126	1			T2	299		T3	1015		T4	970
valid_sources[0x1e]	261480	1			T2	331		T3	1051		T4	929
valid_sources[0x1f]	255477	1			T2	284		T3	1001		T4	902
valid_sources[0x20]	300331	1			T2	332		T3	1005		T4	913
valid_sources[0x21]	314987	1			T2	351		T3	944		T4	908
valid_sources[0x22]	308904	1			T1	3		T2	332		T3	946
valid_sources[0x23]	295873	1			T2	338		T3	1001		T4	959
valid_sources[0x24]	315123	1			T1	9		T2	354		T3	910
valid_sources[0x25]	269547	1			T2	300		T3	901		T4	861
valid_sources[0x26]	262433	1			T1	3		T2	334		T3	1041
valid_sources[0x27]	268522	1			T2	294		T3	974		T4	973
valid_sources[0x28]	314835	1			T2	309		T3	960		T4	892
valid_sources[0x29]	268918	1			T2	338		T3	1069		T4	916
valid_sources[0x2a]	300786	1			T2	330		T3	764		T4	977
valid_sources[0x2b]	336108	1			T2	339		T3	941		T4	885
valid_sources[0x2c]	277463	1			T2	339		T3	849		T4	887
valid_sources[0x2d]	256986	1			T2	299		T3	933		T4	928
valid_sources[0x2e]	342391	1			T2	362		T3	993		T4	917
valid_sources[0x2f]	270144	1			T2	335		T3	900		T4	951
valid_sources[0x30]	292288	1			T2	320		T3	974		T4	892
valid_sources[0x31]	291112	1			T1	8		T2	343		T3	758
valid_sources[0x32]	264713	1			T2	330		T3	959		T4	993
valid_sources[0x33]	267985	1			T1	1		T2	341		T3	970
valid_sources[0x34]	276915	1			T2	355		T3	970		T4	920
valid_sources[0x35]	276284	1			T1	2		T2	287		T3	1122
valid_sources[0x36]	291061	1			T1	2		T2	327		T3	1222
valid_sources[0x37]	260548	1			T1	5		T2	296		T3	941
valid_sources[0x38]	299863	1			T2	326		T3	1070		T4	986
valid_sources[0x39]	366578	1			T2	300		T3	888		T4	936
valid_sources[0x3a]	266163	1			T1	6		T2	327		T3	864
valid_sources[0x3b]	279523	1			T2	302		T3	1111		T4	980
valid_sources[0x3c]	283079	1			T2	292		T3	694		T4	905
valid_sources[0x3d]	266313	1			T2	339		T3	1069		T4	908
valid_sources[0x3e]	264854	1			T2	340		T3	951		T4	914
valid_sources[0x3f]	339901	1			T2	350		T3	1017		T4	927
valid_sources[0x40]	271362	1			T2	303		T3	978		T4	923
valid_sources[0x41]	278969	1			T2	294		T3	926		T4	974
valid_sources[0x42]	299009	1			T1	2		T2	295		T3	1067
valid_sources[0x43]	301935	1			T2	341		T3	895		T4	1010
valid_sources[0x44]	273761	1			T2	321		T3	937		T4	899
valid_sources[0x45]	271130	1			T2	317		T3	968		T4	911
valid_sources[0x46]	374728	1			T2	322		T3	1041		T4	955
valid_sources[0x47]	295224	1			T2	314		T3	1055		T4	915
valid_sources[0x48]	281632	1			T2	321		T3	999		T4	933
valid_sources[0x49]	314422	1			T2	307		T3	880		T4	942
valid_sources[0x4a]	267689	1			T2	316		T3	798		T4	969
valid_sources[0x4b]	407301	1			T2	350		T3	976		T4	848
valid_sources[0x4c]	302317	1			T2	304		T3	1112		T4	927
valid_sources[0x4d]	258896	1			T1	1		T2	314		T3	925
valid_sources[0x4e]	283041	1			T2	346		T3	922		T4	1035
valid_sources[0x4f]	252746	1			T2	284		T3	895		T4	947
valid_sources[0x50]	302128	1			T2	287		T3	1026		T4	944
valid_sources[0x51]	263479	1			T2	318		T3	860		T4	929
valid_sources[0x52]	269217	1			T1	1		T2	305		T3	915
valid_sources[0x53]	273709	1			T2	314		T3	1108		T4	972
valid_sources[0x54]	283609	1			T2	336		T3	921		T4	914
valid_sources[0x55]	307567	1			T2	291		T3	923		T4	929
valid_sources[0x56]	296650	1			T2	311		T3	1046		T4	1033
valid_sources[0x57]	338921	1			T2	296		T3	947		T4	939
valid_sources[0x58]	300902	1			T2	337		T3	1116		T4	939
valid_sources[0x59]	268295	1			T2	318		T3	956		T4	900
valid_sources[0x5a]	268425	1			T2	326		T3	989		T4	888
valid_sources[0x5b]	286945	1			T2	310		T3	945		T4	910
valid_sources[0x5c]	312924	1			T1	3		T2	302		T3	1066
valid_sources[0x5d]	285360	1			T2	299		T3	1002		T4	909
valid_sources[0x5e]	274183	1			T2	297		T3	1021		T4	878
valid_sources[0x5f]	272567	1			T2	294		T3	857		T4	971
valid_sources[0x60]	262370	1			T2	303		T3	983		T4	955
valid_sources[0x61]	253059	1			T1	1		T2	313		T3	1118
valid_sources[0x62]	269250	1			T2	313		T3	1014		T4	901
valid_sources[0x63]	307691	1			T2	334		T3	880		T4	968
valid_sources[0x64]	293839	1			T2	300		T3	967		T4	911
valid_sources[0x65]	257279	1			T2	319		T3	1062		T4	895
valid_sources[0x66]	310940	1			T2	344		T3	1039		T4	972
valid_sources[0x67]	295077	1			T2	308		T3	1047		T4	948
valid_sources[0x68]	294069	1			T2	323		T3	1019		T4	982
valid_sources[0x69]	273735	1			T1	1		T2	306		T3	1064
valid_sources[0x6a]	342055	1			T2	327		T3	966		T4	976
valid_sources[0x6b]	302550	1			T2	343		T3	1084		T4	893
valid_sources[0x6c]	282512	1			T2	300		T3	968		T4	915
valid_sources[0x6d]	300204	1			T1	4		T2	314		T3	916
valid_sources[0x6e]	296911	1			T1	1		T2	328		T3	960
valid_sources[0x6f]	319283	1			T2	302		T3	1049		T4	961
valid_sources[0x70]	309205	1			T2	303		T3	1004		T4	982
valid_sources[0x71]	271948	1			T2	346		T3	979		T4	935
valid_sources[0x72]	296415	1			T1	1		T2	320		T3	982
valid_sources[0x73]	295179	1			T2	325		T3	991		T4	940
valid_sources[0x74]	261620	1			T2	303		T3	857		T4	933
valid_sources[0x75]	319057	1			T2	321		T3	953		T4	937
valid_sources[0x76]	271255	1			T2	363		T3	979		T4	934
valid_sources[0x77]	252833	1			T1	6		T2	333		T3	1061
valid_sources[0x78]	300217	1			T2	322		T3	1081		T4	1013
valid_sources[0x79]	263461	1			T1	3		T2	330		T3	1115
valid_sources[0x7a]	283691	1			T2	336		T3	991		T4	957
valid_sources[0x7b]	341085	1			T2	340		T3	1051		T4	941
valid_sources[0x7c]	274447	1			T2	299		T3	947		T4	943
valid_sources[0x7d]	281170	1			T2	345		T3	877		T4	969
valid_sources[0x7e]	290327	1			T2	357		T3	869		T4	906
valid_sources[0x7f]	265291	1			T2	324		T3	991		T4	947
valid_sources[0x80]	308336	1			T2	305		T3	1109		T4	938

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30368810

1

T1

54

T2

37455

T3

113634

values[0x0]

all_enables

biggest_size

15291617

1

T1

33

T2

21495

T3

57169

values[0x1]

all_enables

biggest_size

15289331

1

T1

33

T2

21720

T3

56869

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35531	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

132515

1

T1

1

T2

6207

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48294	1			T2	1657		T3	17		T26	15
values[0x0]	57553	1			T1	1		T2	2349		T3	34
values[0x1]	62199	1			T2	2593		T3	30		T4	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141155

1

T1

1

T2

6370

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	761	1			T2	60		T22	1		T25	25
valid_sources[0x01]	839	1			T2	147		T6	3		T7	1
valid_sources[0x02]	624	1			T2	107		T67	1		T24	19
valid_sources[0x03]	985	1			T12	2		T67	6		T25	22
valid_sources[0x04]	642	1			T3	1		T22	3		T25	24
valid_sources[0x05]	671	1			T7	2		T67	1		T25	26
valid_sources[0x06]	769	1			T10	1		T7	1		T135	2
valid_sources[0x07]	914	1			T2	49		T7	2		T68	2
valid_sources[0x08]	482	1			T2	12		T3	2		T7	2
valid_sources[0x09]	649	1			T2	22		T6	1		T25	37
valid_sources[0x0a]	673	1			T2	113		T7	2		T24	35
valid_sources[0x0b]	723	1			T2	45		T3	1		T10	2
valid_sources[0x0c]	836	1			T2	75		T67	2		T136	2
valid_sources[0x0d]	513	1			T3	2		T10	1		T22	1
valid_sources[0x0e]	722	1			T2	57		T6	2		T7	3
valid_sources[0x0f]	553	1			T2	18		T81	9		T67	1
valid_sources[0x10]	672	1			T2	43		T3	1		T7	2
valid_sources[0x11]	746	1			T2	3		T4	3		T67	1
valid_sources[0x12]	664	1			T2	1		T26	2		T24	1
valid_sources[0x13]	626	1			T2	1		T6	1		T7	3
valid_sources[0x14]	761	1			T2	19		T10	1		T6	2
valid_sources[0x15]	441	1			T2	1		T135	3		T24	1
valid_sources[0x16]	786	1			T2	185		T26	3		T22	1
valid_sources[0x17]	590	1			T2	1		T3	1		T22	1
valid_sources[0x18]	591	1			T3	1		T26	1		T6	2
valid_sources[0x19]	535	1			T3	1		T4	1		T67	7
valid_sources[0x1a]	846	1			T2	32		T22	2		T40	1
valid_sources[0x1b]	472	1			T26	1		T67	1		T68	3
valid_sources[0x1c]	619	1			T2	64		T22	2		T64	1
valid_sources[0x1d]	792	1			T7	2		T24	12		T25	21
valid_sources[0x1e]	633	1			T7	1		T22	2		T64	1
valid_sources[0x1f]	765	1			T2	102		T7	3		T67	1
valid_sources[0x20]	434	1			T2	4		T22	1		T24	30
valid_sources[0x21]	454	1			T2	3		T22	1		T24	18
valid_sources[0x22]	819	1			T2	71		T3	1		T6	1
valid_sources[0x23]	935	1			T2	9		T27	1		T68	1
valid_sources[0x24]	1070	1			T2	3		T6	1		T7	1
valid_sources[0x25]	724	1			T2	130		T3	3		T7	1
valid_sources[0x26]	991	1			T2	4		T3	1		T6	2
valid_sources[0x27]	625	1			T2	3		T8	1		T80	1
valid_sources[0x28]	704	1			T10	1		T7	2		T68	1
valid_sources[0x29]	512	1			T88	1		T25	13		T137	1
valid_sources[0x2a]	638	1			T2	2		T10	1		T24	43
valid_sources[0x2b]	530	1			T2	5		T22	1		T25	31
valid_sources[0x2c]	769	1			T2	28		T3	1		T80	1
valid_sources[0x2d]	691	1			T2	150		T10	1		T22	1
valid_sources[0x2e]	856	1			T2	124		T67	4		T24	12
valid_sources[0x2f]	593	1			T3	2		T24	5		T25	25
valid_sources[0x30]	618	1			T2	27		T26	1		T22	4
valid_sources[0x31]	678	1			T2	24		T67	1		T68	3
valid_sources[0x32]	872	1			T22	2		T24	28		T133	4
valid_sources[0x33]	686	1			T2	1		T3	2		T68	1
valid_sources[0x34]	652	1			T2	45		T6	2		T80	1
valid_sources[0x35]	502	1			T2	1		T25	30		T138	1
valid_sources[0x36]	545	1			T2	9		T67	1		T25	17
valid_sources[0x37]	634	1			T2	5		T26	8		T25	18
valid_sources[0x38]	797	1			T2	74		T6	1		T7	1
valid_sources[0x39]	651	1			T2	86		T26	2		T22	2
valid_sources[0x3a]	1006	1			T2	3		T4	1		T7	2
valid_sources[0x3b]	703	1			T2	120		T25	17		T137	1
valid_sources[0x3c]	556	1			T2	1		T26	1		T7	2
valid_sources[0x3d]	787	1			T2	143		T7	1		T25	23
valid_sources[0x3e]	777	1			T2	22		T26	1		T6	1
valid_sources[0x3f]	514	1			T2	4		T3	1		T6	1
valid_sources[0x40]	611	1			T26	1		T25	22		T139	5
valid_sources[0x41]	561	1			T2	41		T3	2		T67	3
valid_sources[0x42]	548	1			T2	2		T3	1		T40	1
valid_sources[0x43]	545	1			T2	109		T3	3		T7	1
valid_sources[0x44]	469	1			T4	1		T6	1		T7	1
valid_sources[0x45]	478	1			T7	1		T89	1		T25	26
valid_sources[0x46]	481	1			T10	1		T6	2		T22	1
valid_sources[0x47]	607	1			T3	2		T26	1		T24	40
valid_sources[0x48]	596	1			T2	23		T26	1		T40	4
valid_sources[0x49]	636	1			T2	1		T3	1		T6	1
valid_sources[0x4a]	613	1			T2	4		T68	1		T133	4
valid_sources[0x4b]	697	1			T6	1		T22	1		T25	24
valid_sources[0x4c]	630	1			T2	87		T43	1		T24	8
valid_sources[0x4d]	492	1			T24	1		T25	22		T137	1
valid_sources[0x4e]	671	1			T2	2		T22	3		T68	1
valid_sources[0x4f]	675	1			T2	1		T26	3		T7	5
valid_sources[0x50]	780	1			T10	1		T22	1		T24	25
valid_sources[0x51]	869	1			T2	22		T6	1		T80	1
valid_sources[0x52]	843	1			T2	82		T7	3		T22	1
valid_sources[0x53]	692	1			T2	171		T42	6		T67	2
valid_sources[0x54]	531	1			T2	7		T26	2		T67	2
valid_sources[0x55]	703	1			T2	1		T3	1		T7	1
valid_sources[0x56]	804	1			T22	1		T18	1		T25	35
valid_sources[0x57]	605	1			T2	14		T24	20		T25	22
valid_sources[0x58]	720	1			T6	1		T67	3		T68	2
valid_sources[0x59]	624	1			T3	2		T22	1		T25	24
valid_sources[0x5a]	538	1			T4	1		T7	1		T67	4
valid_sources[0x5b]	942	1			T2	9		T3	1		T10	1
valid_sources[0x5c]	527	1			T26	2		T7	1		T24	17
valid_sources[0x5d]	577	1			T2	1		T11	1		T26	1
valid_sources[0x5e]	695	1			T2	90		T3	1		T4	1
valid_sources[0x5f]	514	1			T2	3		T10	1		T24	2
valid_sources[0x60]	618	1			T2	25		T10	1		T26	2
valid_sources[0x61]	829	1			T2	77		T10	1		T26	1
valid_sources[0x62]	569	1			T4	1		T25	24		T137	1
valid_sources[0x63]	671	1			T7	1		T22	1		T24	2
valid_sources[0x64]	504	1			T26	1		T7	2		T22	2
valid_sources[0x65]	802	1			T26	1		T24	9		T25	25
valid_sources[0x66]	503	1			T22	1		T67	5		T68	1
valid_sources[0x67]	831	1			T2	89		T3	1		T26	2
valid_sources[0x68]	534	1			T3	1		T4	3		T40	3
valid_sources[0x69]	815	1			T2	31		T6	2		T63	1
valid_sources[0x6a]	703	1			T2	20		T6	1		T7	1
valid_sources[0x6b]	559	1			T26	2		T24	4		T25	21
valid_sources[0x6c]	750	1			T2	3		T22	1		T68	1
valid_sources[0x6d]	550	1			T2	1		T7	1		T68	1
valid_sources[0x6e]	604	1			T2	46		T4	1		T26	1
valid_sources[0x6f]	574	1			T2	2		T6	1		T67	1
valid_sources[0x70]	604	1			T2	13		T25	22		T69	4
valid_sources[0x71]	897	1			T6	1		T7	2		T68	1
valid_sources[0x72]	525	1			T3	1		T22	1		T68	1
valid_sources[0x73]	705	1			T2	42		T140	2		T67	2
valid_sources[0x74]	551	1			T22	1		T24	16		T25	22
valid_sources[0x75]	536	1			T22	3		T41	4		T24	21
valid_sources[0x76]	615	1			T2	18		T25	26		T139	1
valid_sources[0x77]	539	1			T10	2		T68	1		T135	1
valid_sources[0x78]	922	1			T7	1		T24	16		T141	1
valid_sources[0x79]	519	1			T2	3		T10	1		T7	1
valid_sources[0x7a]	721	1			T2	1		T10	1		T7	1
valid_sources[0x7b]	538	1			T135	2		T25	16		T142	3
valid_sources[0x7c]	525	1			T7	1		T68	1		T143	28
valid_sources[0x7d]	996	1			T2	34		T61	10		T22	1
valid_sources[0x7e]	501	1			T2	13		T68	1		T24	2
valid_sources[0x7f]	795	1			T2	12		T10	1		T7	1
valid_sources[0x80]	677	1			T2	1		T4	1		T133	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36095

1

T2

1546

T3

11

T26

7

values[0x0]

all_enables

biggest_size

49127

1

T1

1

T2

2297

T3

11

values[0x1]

all_enables

biggest_size

47293

1

T2

2364

T3

2

T9

4