Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13475910

1

T1

18

T2

11227

T3

17998

full_word

55272078

1

T1

120

T2

80491

T3

182171

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68747698	1			T1	138		T2	91718		T3	200169
auto[TlIntgErrCmd]	89	1			T57	4		T58	8		T59	2
auto[TlIntgErrData]	87	1			T57	3		T58	4		T59	5
auto[TlIntgErrBoth]	114	1			T57	3		T58	8		T59	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31166390

1

T1

64

T2

39080

T3

74845

auto[1]

37581598

1

T1

74

T2

52638

T3

125324

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6398443	1			T1	10		T2	2712		T3	6712
auto[TlIntgErrNone]	partial	auto[1]	7077207	1			T1	8		T2	8515		T3	11286
auto[TlIntgErrNone]	full_word	auto[0]	24767834	1			T1	54		T2	36368		T3	68133
auto[TlIntgErrNone]	full_word	auto[1]	30504214	1			T1	66		T2	44123		T3	114038
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T57	1		T58	2		T59	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T57	3		T58	4		T59	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T58	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T58	1		T127	2		T128	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T57	2		T58	1		T59	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T57	1		T58	2		T59	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T59	1		T124	3		T121	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T58	1		T129	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T58	7		T59	1		T124	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T57	3		T58	1		T59	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T126	1		T127	1		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T124	1		T120	1		T123	1