Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	705471	1			T1	3		T4	6116		T8	2343
auto[1]	10531472	1			T1	4		T2	8451		T3	5279
auto[2]	588215	1			T4	3933		T8	1814		T10	24
auto[3]	10420191	1			T1	2		T2	8341		T3	5136

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14385554	1			T1	6		T2	13997		T3	8611
auto[1]	2128308	1			T1	1		T2	1304		T3	892
auto[2]	2140671	1			T1	2		T2	1347		T3	836
auto[3]	3590816	1			T2	144		T3	76		T4	192

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8330175

1

T1

9

T2

16773

T3

10407

auto[1]

13915174

1

T2

19

T3

8

T4

8

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	254389	1			T1	2		T4	5035		T8	1
auto[0]	auto[0]	auto[1]	26411	1			T4	521		T10	2		T26	151
auto[0]	auto[0]	auto[2]	26273	1			T1	1		T4	521		T10	1
auto[0]	auto[0]	auto[3]	7900	1			T4	36		T26	16		T81	43
auto[0]	auto[1]	auto[0]	3181443	1			T1	4		T2	7091		T3	4344
auto[0]	auto[1]	auto[1]	328609	1			T2	623		T3	457		T4	593
auto[0]	auto[1]	auto[2]	320623	1			T2	667		T3	437		T4	338
auto[0]	auto[1]	auto[3]	61369	1			T2	62		T3	36		T4	59
auto[0]	auto[2]	auto[0]	216960	1			T4	3100		T26	1433		T6	20
auto[0]	auto[2]	auto[1]	22236	1			T4	321		T26	160		T6	2
auto[0]	auto[2]	auto[2]	24676	1			T4	471		T10	23		T26	137
auto[0]	auto[2]	auto[3]	6499	1			T4	38		T10	1		T26	15
auto[0]	auto[3]	auto[0]	3146966	1			T2	6890		T3	4260		T4	1501
auto[0]	auto[3]	auto[1]	315693	1			T1	1		T2	679		T3	435
auto[0]	auto[3]	auto[2]	327866	1			T1	1		T2	679		T3	398
auto[0]	auto[3]	auto[3]	62262	1			T2	82		T3	40		T4	59
auto[1]	auto[0]	auto[0]	13166	1			T4	2		T8	79		T26	2
auto[1]	auto[0]	auto[1]	58075	1			T4	1		T8	349		T81	1
auto[1]	auto[0]	auto[2]	57609	1			T8	336		T7	1		T100	1482
auto[1]	auto[0]	auto[3]	261648	1			T8	1578		T88	1		T100	6531
auto[1]	auto[1]	auto[0]	3783472	1			T2	7		T3	4		T4	1
auto[1]	auto[1]	auto[1]	680143	1			T8	1205		T9	3		T12	1
auto[1]	auto[1]	auto[2]	665255	1			T2	1		T3	1		T8	686
auto[1]	auto[1]	auto[3]	1510558	1			T8	5497		T9	1		T60	1
auto[1]	auto[2]	auto[0]	10202	1			T4	2		T26	1		T81	2
auto[1]	auto[2]	auto[1]	45404	1			T4	1		T100	853		T103	3699
auto[1]	auto[2]	auto[2]	47454	1			T8	305		T100	1645		T101	422
auto[1]	auto[2]	auto[3]	214784	1			T8	1509		T100	7181		T90	1
auto[1]	auto[3]	auto[0]	3778956	1			T2	9		T3	3		T8	79
auto[1]	auto[3]	auto[1]	651737	1			T2	2		T8	311		T9	2
auto[1]	auto[3]	auto[2]	670915	1			T4	1		T8	1182		T9	4
auto[1]	auto[3]	auto[3]	1465796	1			T8	5187		T9	3		T63	1