Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	325135958	204298	0	0
ctrl_regwen_rd_A	325135958	4231	0	0
exec_rd_A	325135958	3973	0	0
exec_regwen_rd_A	325135958	4430	0	0
readback_rd_A	325135958	2279	0	0
readback_regwen_rd_A	325135958	2088	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325135958	204298	0	0
T2	179441	8974	0	0
T3	410620	0	0	0
T4	194479	0	0	0
T8	751881	0	0	0
T9	345831	0	0	0
T10	849930	0	0	0
T11	29351	0	0	0
T12	13296	0	0	0
T13	24407	0	0	0
T24	0	3540	0	0
T25	0	8717	0	0
T27	1803	0	0	0
T38	0	1205	0	0
T44	0	3822	0	0
T54	0	6840	0	0
T56	0	3394	0	0
T69	0	1478	0	0
T70	0	1393	0	0
T71	0	6071	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325135958	4231	0	0
T15	1177	0	0	0
T25	295595	649	0	0
T38	0	114	0	0
T45	0	60	0	0
T53	9155	0	0	0
T103	162164	0	0	0
T107	0	94	0	0
T108	0	201	0	0
T109	0	354	0	0
T110	0	343	0	0
T111	0	179	0	0
T112	0	89	0	0
T113	0	102	0	0
T114	1780	0	0	0
T115	11139	0	0	0
T116	9279	0	0	0
T117	22252	0	0	0
T118	146752	0	0	0
T119	6690	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325135958	3973	0	0
T15	1177	0	0	0
T25	295595	595	0	0
T38	0	145	0	0
T45	0	64	0	0
T53	9155	0	0	0
T103	162164	0	0	0
T107	0	90	0	0
T108	0	259	0	0
T109	0	437	0	0
T110	0	260	0	0
T111	0	102	0	0
T112	0	90	0	0
T113	0	63	0	0
T114	1780	0	0	0
T115	11139	0	0	0
T116	9279	0	0	0
T117	22252	0	0	0
T118	146752	0	0	0
T119	6690	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325135958	4430	0	0
T15	1177	0	0	0
T25	295595	725	0	0
T38	0	153	0	0
T45	0	109	0	0
T53	9155	0	0	0
T103	162164	0	0	0
T107	0	144	0	0
T108	0	314	0	0
T109	0	455	0	0
T110	0	311	0	0
T111	0	137	0	0
T112	0	116	0	0
T113	0	102	0	0
T114	1780	0	0	0
T115	11139	0	0	0
T116	9279	0	0	0
T117	22252	0	0	0
T118	146752	0	0	0
T119	6690	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325135958	2279	0	0
T15	1177	0	0	0
T25	295595	600	0	0
T38	0	68	0	0
T45	0	23	0	0
T53	9155	0	0	0
T103	162164	0	0	0
T107	0	40	0	0
T108	0	306	0	0
T109	0	346	0	0
T110	0	241	0	0
T111	0	82	0	0
T112	0	88	0	0
T113	0	153	0	0
T114	1780	0	0	0
T115	11139	0	0	0
T116	9279	0	0	0
T117	22252	0	0	0
T118	146752	0	0	0
T119	6690	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325135958	2088	0	0
T15	1177	0	0	0
T25	295595	428	0	0
T38	0	115	0	0
T45	0	64	0	0
T53	9155	0	0	0
T103	162164	0	0	0
T107	0	51	0	0
T108	0	237	0	0
T109	0	334	0	0
T110	0	250	0	0
T111	0	84	0	0
T112	0	134	0	0
T113	0	85	0	0
T114	1780	0	0	0
T115	11139	0	0	0
T116	9279	0	0	0
T117	22252	0	0	0
T118	146752	0	0	0
T119	6690	0	0	0