| T792 |
/workspace/coverage/default/2.sram_ctrl_smoke.231466388 |
|
|
Aug 09 05:41:08 PM PDT 24 |
Aug 09 05:41:12 PM PDT 24 |
298930176 ps |
| T793 |
/workspace/coverage/default/11.sram_ctrl_smoke.4251813013 |
|
|
Aug 09 05:41:31 PM PDT 24 |
Aug 09 05:41:41 PM PDT 24 |
2728209323 ps |
| T794 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2872598147 |
|
|
Aug 09 05:41:36 PM PDT 24 |
Aug 09 05:41:42 PM PDT 24 |
749850179 ps |
| T795 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3273617341 |
|
|
Aug 09 05:45:39 PM PDT 24 |
Aug 09 05:45:42 PM PDT 24 |
60228895 ps |
| T796 |
/workspace/coverage/default/38.sram_ctrl_executable.4025352702 |
|
|
Aug 09 05:44:39 PM PDT 24 |
Aug 09 06:00:24 PM PDT 24 |
18032413545 ps |
| T797 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.757815857 |
|
|
Aug 09 05:43:07 PM PDT 24 |
Aug 09 05:43:14 PM PDT 24 |
639422857 ps |
| T798 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.229879077 |
|
|
Aug 09 05:42:35 PM PDT 24 |
Aug 09 05:42:55 PM PDT 24 |
445099674 ps |
| T799 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3004660311 |
|
|
Aug 09 05:44:12 PM PDT 24 |
Aug 09 05:44:48 PM PDT 24 |
103032386 ps |
| T800 |
/workspace/coverage/default/2.sram_ctrl_bijection.3043587731 |
|
|
Aug 09 05:40:59 PM PDT 24 |
Aug 09 05:42:10 PM PDT 24 |
9500651904 ps |
| T801 |
/workspace/coverage/default/29.sram_ctrl_smoke.3159328873 |
|
|
Aug 09 05:43:26 PM PDT 24 |
Aug 09 05:43:32 PM PDT 24 |
892514782 ps |
| T802 |
/workspace/coverage/default/9.sram_ctrl_partial_access.1876530573 |
|
|
Aug 09 05:41:31 PM PDT 24 |
Aug 09 05:41:41 PM PDT 24 |
475160361 ps |
| T803 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1586776155 |
|
|
Aug 09 05:45:36 PM PDT 24 |
Aug 09 05:45:37 PM PDT 24 |
102051269 ps |
| T804 |
/workspace/coverage/default/8.sram_ctrl_stress_all.3557240438 |
|
|
Aug 09 05:41:25 PM PDT 24 |
Aug 09 06:51:15 PM PDT 24 |
44923962108 ps |
| T805 |
/workspace/coverage/default/9.sram_ctrl_regwen.1102583438 |
|
|
Aug 09 05:41:33 PM PDT 24 |
Aug 09 06:01:03 PM PDT 24 |
53822066980 ps |
| T806 |
/workspace/coverage/default/31.sram_ctrl_executable.401517210 |
|
|
Aug 09 05:43:44 PM PDT 24 |
Aug 09 05:53:10 PM PDT 24 |
8327144330 ps |
| T807 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1750180820 |
|
|
Aug 09 05:41:27 PM PDT 24 |
Aug 09 05:41:33 PM PDT 24 |
239851454 ps |
| T808 |
/workspace/coverage/default/24.sram_ctrl_smoke.1154532163 |
|
|
Aug 09 05:42:50 PM PDT 24 |
Aug 09 05:44:23 PM PDT 24 |
2189993976 ps |
| T809 |
/workspace/coverage/default/44.sram_ctrl_smoke.3099200181 |
|
|
Aug 09 05:45:29 PM PDT 24 |
Aug 09 05:45:35 PM PDT 24 |
410700937 ps |
| T810 |
/workspace/coverage/default/22.sram_ctrl_smoke.2495091910 |
|
|
Aug 09 05:42:35 PM PDT 24 |
Aug 09 05:42:36 PM PDT 24 |
80123335 ps |
| T811 |
/workspace/coverage/default/11.sram_ctrl_partial_access.467249989 |
|
|
Aug 09 05:41:36 PM PDT 24 |
Aug 09 05:41:40 PM PDT 24 |
361945947 ps |
| T812 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1023978214 |
|
|
Aug 09 05:40:57 PM PDT 24 |
Aug 09 05:49:07 PM PDT 24 |
4308552452 ps |
| T813 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.4220281840 |
|
|
Aug 09 05:46:28 PM PDT 24 |
Aug 09 05:46:34 PM PDT 24 |
1019166789 ps |
| T814 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1448356568 |
|
|
Aug 09 05:45:58 PM PDT 24 |
Aug 09 05:49:21 PM PDT 24 |
6014284299 ps |
| T815 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2724479639 |
|
|
Aug 09 05:42:45 PM PDT 24 |
Aug 09 05:42:48 PM PDT 24 |
217635532 ps |
| T816 |
/workspace/coverage/default/16.sram_ctrl_executable.340497620 |
|
|
Aug 09 05:42:06 PM PDT 24 |
Aug 09 05:46:10 PM PDT 24 |
3112358735 ps |
| T817 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.888354964 |
|
|
Aug 09 05:43:33 PM PDT 24 |
Aug 09 05:44:37 PM PDT 24 |
1607351391 ps |
| T818 |
/workspace/coverage/default/27.sram_ctrl_regwen.1714800550 |
|
|
Aug 09 05:43:16 PM PDT 24 |
Aug 09 05:50:20 PM PDT 24 |
5481050655 ps |
| T819 |
/workspace/coverage/default/22.sram_ctrl_stress_all.3139235276 |
|
|
Aug 09 05:42:45 PM PDT 24 |
Aug 09 06:55:36 PM PDT 24 |
413330274999 ps |
| T820 |
/workspace/coverage/default/26.sram_ctrl_alert_test.2995512033 |
|
|
Aug 09 05:43:06 PM PDT 24 |
Aug 09 05:43:07 PM PDT 24 |
43721594 ps |
| T821 |
/workspace/coverage/default/15.sram_ctrl_partial_access.4246463 |
|
|
Aug 09 05:41:55 PM PDT 24 |
Aug 09 05:42:12 PM PDT 24 |
3454585489 ps |
| T822 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2695879150 |
|
|
Aug 09 05:41:17 PM PDT 24 |
Aug 09 05:41:32 PM PDT 24 |
258580477 ps |
| T823 |
/workspace/coverage/default/49.sram_ctrl_alert_test.2931010063 |
|
|
Aug 09 05:46:32 PM PDT 24 |
Aug 09 05:46:33 PM PDT 24 |
12746153 ps |
| T824 |
/workspace/coverage/default/37.sram_ctrl_smoke.1073823229 |
|
|
Aug 09 05:44:24 PM PDT 24 |
Aug 09 05:44:41 PM PDT 24 |
1093741533 ps |
| T825 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.1346472452 |
|
|
Aug 09 05:41:23 PM PDT 24 |
Aug 09 05:41:26 PM PDT 24 |
479915430 ps |
| T826 |
/workspace/coverage/default/33.sram_ctrl_partial_access.4126354613 |
|
|
Aug 09 05:43:56 PM PDT 24 |
Aug 09 05:44:08 PM PDT 24 |
679179381 ps |
| T827 |
/workspace/coverage/default/21.sram_ctrl_regwen.1749887885 |
|
|
Aug 09 05:42:32 PM PDT 24 |
Aug 09 05:48:33 PM PDT 24 |
7925506270 ps |
| T828 |
/workspace/coverage/default/30.sram_ctrl_stress_all.3672142480 |
|
|
Aug 09 05:43:37 PM PDT 24 |
Aug 09 06:47:16 PM PDT 24 |
100688223677 ps |
| T829 |
/workspace/coverage/default/32.sram_ctrl_regwen.729088916 |
|
|
Aug 09 05:43:55 PM PDT 24 |
Aug 09 05:50:47 PM PDT 24 |
4254180074 ps |
| T830 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3322522872 |
|
|
Aug 09 05:42:58 PM PDT 24 |
Aug 09 05:43:07 PM PDT 24 |
142309587 ps |
| T831 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.38042015 |
|
|
Aug 09 05:42:52 PM PDT 24 |
Aug 09 05:53:42 PM PDT 24 |
4709560678 ps |
| T832 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2223093106 |
|
|
Aug 09 05:45:58 PM PDT 24 |
Aug 09 05:45:59 PM PDT 24 |
27780909 ps |
| T833 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.574841375 |
|
|
Aug 09 05:42:51 PM PDT 24 |
Aug 09 05:43:23 PM PDT 24 |
1666674389 ps |
| T834 |
/workspace/coverage/default/45.sram_ctrl_bijection.503843195 |
|
|
Aug 09 05:45:36 PM PDT 24 |
Aug 09 05:45:57 PM PDT 24 |
310675750 ps |
| T835 |
/workspace/coverage/default/26.sram_ctrl_executable.116213089 |
|
|
Aug 09 05:43:07 PM PDT 24 |
Aug 09 06:00:41 PM PDT 24 |
13834767497 ps |
| T836 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2659200648 |
|
|
Aug 09 05:45:32 PM PDT 24 |
Aug 09 05:45:40 PM PDT 24 |
69121922 ps |
| T837 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1153059474 |
|
|
Aug 09 05:44:18 PM PDT 24 |
Aug 09 06:04:56 PM PDT 24 |
163896082484 ps |
| T838 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1260079226 |
|
|
Aug 09 05:42:51 PM PDT 24 |
Aug 09 05:42:52 PM PDT 24 |
114431528 ps |
| T839 |
/workspace/coverage/default/47.sram_ctrl_alert_test.3469376063 |
|
|
Aug 09 05:46:11 PM PDT 24 |
Aug 09 05:46:12 PM PDT 24 |
53257052 ps |
| T840 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1252654194 |
|
|
Aug 09 05:44:07 PM PDT 24 |
Aug 09 05:55:45 PM PDT 24 |
35142474822 ps |
| T841 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.55064445 |
|
|
Aug 09 05:41:51 PM PDT 24 |
Aug 09 05:42:02 PM PDT 24 |
66699816 ps |
| T842 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1320311626 |
|
|
Aug 09 05:41:13 PM PDT 24 |
Aug 09 05:51:31 PM PDT 24 |
21210487629 ps |
| T843 |
/workspace/coverage/default/20.sram_ctrl_regwen.1761793594 |
|
|
Aug 09 05:42:28 PM PDT 24 |
Aug 09 05:56:46 PM PDT 24 |
41299071689 ps |
| T844 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.151257165 |
|
|
Aug 09 05:42:45 PM PDT 24 |
Aug 09 05:42:50 PM PDT 24 |
254607092 ps |
| T845 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.601552626 |
|
|
Aug 09 05:41:00 PM PDT 24 |
Aug 09 05:44:49 PM PDT 24 |
4907917349 ps |
| T846 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2102717730 |
|
|
Aug 09 05:41:38 PM PDT 24 |
Aug 09 05:41:43 PM PDT 24 |
65421218 ps |
| T847 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1100411336 |
|
|
Aug 09 05:42:25 PM PDT 24 |
Aug 09 05:42:34 PM PDT 24 |
869412222 ps |
| T848 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2073095020 |
|
|
Aug 09 05:45:18 PM PDT 24 |
Aug 09 06:03:28 PM PDT 24 |
16659827630 ps |
| T849 |
/workspace/coverage/default/4.sram_ctrl_alert_test.811067936 |
|
|
Aug 09 05:41:19 PM PDT 24 |
Aug 09 05:41:19 PM PDT 24 |
114464990 ps |
| T850 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3271849124 |
|
|
Aug 09 05:45:01 PM PDT 24 |
Aug 09 05:48:13 PM PDT 24 |
10821643156 ps |
| T851 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.2622428388 |
|
|
Aug 09 05:42:27 PM PDT 24 |
Aug 09 05:42:28 PM PDT 24 |
48039570 ps |
| T852 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1524256649 |
|
|
Aug 09 05:45:30 PM PDT 24 |
Aug 09 05:53:15 PM PDT 24 |
2294390927 ps |
| T853 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2196133262 |
|
|
Aug 09 05:41:20 PM PDT 24 |
Aug 09 05:41:25 PM PDT 24 |
249402169 ps |
| T31 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.358152707 |
|
|
Aug 09 05:41:07 PM PDT 24 |
Aug 09 05:41:09 PM PDT 24 |
92746036 ps |
| T854 |
/workspace/coverage/default/18.sram_ctrl_bijection.2076591571 |
|
|
Aug 09 05:42:13 PM PDT 24 |
Aug 09 05:42:48 PM PDT 24 |
8507030928 ps |
| T855 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3301640999 |
|
|
Aug 09 05:45:30 PM PDT 24 |
Aug 09 05:48:24 PM PDT 24 |
7124628361 ps |
| T856 |
/workspace/coverage/default/20.sram_ctrl_bijection.848563377 |
|
|
Aug 09 05:42:26 PM PDT 24 |
Aug 09 05:43:11 PM PDT 24 |
733279102 ps |
| T857 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1453275592 |
|
|
Aug 09 05:41:51 PM PDT 24 |
Aug 09 05:52:57 PM PDT 24 |
17449639749 ps |
| T858 |
/workspace/coverage/default/11.sram_ctrl_stress_all.2267985636 |
|
|
Aug 09 05:41:42 PM PDT 24 |
Aug 09 07:10:26 PM PDT 24 |
453894482916 ps |
| T859 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2143269647 |
|
|
Aug 09 05:46:05 PM PDT 24 |
Aug 09 05:47:46 PM PDT 24 |
840459725 ps |
| T860 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3438041462 |
|
|
Aug 09 05:41:25 PM PDT 24 |
Aug 09 06:05:00 PM PDT 24 |
5155195099 ps |
| T861 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2540728847 |
|
|
Aug 09 05:42:25 PM PDT 24 |
Aug 09 05:44:10 PM PDT 24 |
170002479 ps |
| T862 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.202515291 |
|
|
Aug 09 05:44:19 PM PDT 24 |
Aug 09 05:44:52 PM PDT 24 |
1754869483 ps |
| T113 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3844712844 |
|
|
Aug 09 05:41:27 PM PDT 24 |
Aug 09 05:41:41 PM PDT 24 |
1908220492 ps |
| T863 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1005339657 |
|
|
Aug 09 05:44:39 PM PDT 24 |
Aug 09 05:45:03 PM PDT 24 |
96324886 ps |
| T864 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3732891088 |
|
|
Aug 09 05:45:07 PM PDT 24 |
Aug 09 05:45:12 PM PDT 24 |
232188935 ps |
| T865 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2466276855 |
|
|
Aug 09 05:42:41 PM PDT 24 |
Aug 09 05:46:58 PM PDT 24 |
13023191448 ps |
| T866 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.2097134727 |
|
|
Aug 09 05:42:27 PM PDT 24 |
Aug 09 05:56:34 PM PDT 24 |
12500663599 ps |
| T867 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3077169859 |
|
|
Aug 09 05:43:44 PM PDT 24 |
Aug 09 06:06:17 PM PDT 24 |
3235180926 ps |
| T868 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.416903249 |
|
|
Aug 09 05:43:06 PM PDT 24 |
Aug 09 05:51:30 PM PDT 24 |
25676989136 ps |
| T869 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1397063310 |
|
|
Aug 09 05:41:09 PM PDT 24 |
Aug 09 05:41:10 PM PDT 24 |
33376848 ps |
| T870 |
/workspace/coverage/default/3.sram_ctrl_stress_all.3401336890 |
|
|
Aug 09 05:41:10 PM PDT 24 |
Aug 09 06:53:38 PM PDT 24 |
127039159919 ps |
| T871 |
/workspace/coverage/default/36.sram_ctrl_bijection.2716339412 |
|
|
Aug 09 05:44:19 PM PDT 24 |
Aug 09 05:45:33 PM PDT 24 |
9513429270 ps |
| T872 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.26480957 |
|
|
Aug 09 05:44:25 PM PDT 24 |
Aug 09 06:08:32 PM PDT 24 |
3615078588 ps |
| T873 |
/workspace/coverage/default/49.sram_ctrl_smoke.1510681677 |
|
|
Aug 09 05:46:22 PM PDT 24 |
Aug 09 05:47:27 PM PDT 24 |
3376208788 ps |
| T874 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.3499873705 |
|
|
Aug 09 05:42:10 PM PDT 24 |
Aug 09 05:42:10 PM PDT 24 |
118313406 ps |
| T875 |
/workspace/coverage/default/3.sram_ctrl_regwen.4242763368 |
|
|
Aug 09 05:41:10 PM PDT 24 |
Aug 09 05:52:32 PM PDT 24 |
26914871964 ps |
| T876 |
/workspace/coverage/default/6.sram_ctrl_bijection.1239456082 |
|
|
Aug 09 05:41:22 PM PDT 24 |
Aug 09 05:41:47 PM PDT 24 |
425390026 ps |
| T877 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.4047501670 |
|
|
Aug 09 05:44:07 PM PDT 24 |
Aug 09 06:00:55 PM PDT 24 |
22199707646 ps |
| T878 |
/workspace/coverage/default/35.sram_ctrl_regwen.1349581022 |
|
|
Aug 09 05:44:13 PM PDT 24 |
Aug 09 05:55:31 PM PDT 24 |
4891124905 ps |
| T879 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.3319089664 |
|
|
Aug 09 05:43:32 PM PDT 24 |
Aug 09 05:47:25 PM PDT 24 |
2718276404 ps |
| T880 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3978979227 |
|
|
Aug 09 05:45:25 PM PDT 24 |
Aug 09 05:45:31 PM PDT 24 |
278292911 ps |
| T881 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2789249850 |
|
|
Aug 09 05:41:19 PM PDT 24 |
Aug 09 05:47:45 PM PDT 24 |
5275223138 ps |
| T882 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2254225227 |
|
|
Aug 09 05:43:31 PM PDT 24 |
Aug 09 05:48:20 PM PDT 24 |
39965708507 ps |
| T883 |
/workspace/coverage/default/31.sram_ctrl_partial_access.1038434973 |
|
|
Aug 09 05:43:41 PM PDT 24 |
Aug 09 05:43:57 PM PDT 24 |
4427485639 ps |
| T884 |
/workspace/coverage/default/13.sram_ctrl_stress_all.70012152 |
|
|
Aug 09 05:41:52 PM PDT 24 |
Aug 09 07:21:45 PM PDT 24 |
14702978021 ps |
| T885 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.932548476 |
|
|
Aug 09 05:42:44 PM PDT 24 |
Aug 09 05:47:30 PM PDT 24 |
2464150659 ps |
| T886 |
/workspace/coverage/default/38.sram_ctrl_stress_all.1832015150 |
|
|
Aug 09 05:44:42 PM PDT 24 |
Aug 09 06:15:05 PM PDT 24 |
25201745013 ps |
| T887 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.2889792813 |
|
|
Aug 09 05:42:51 PM PDT 24 |
Aug 09 05:47:35 PM PDT 24 |
11810799819 ps |
| T888 |
/workspace/coverage/default/7.sram_ctrl_alert_test.299192439 |
|
|
Aug 09 05:41:24 PM PDT 24 |
Aug 09 05:41:25 PM PDT 24 |
127054879 ps |
| T889 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.2411240335 |
|
|
Aug 09 05:41:27 PM PDT 24 |
Aug 09 05:41:31 PM PDT 24 |
296050143 ps |
| T890 |
/workspace/coverage/default/6.sram_ctrl_executable.1369443222 |
|
|
Aug 09 05:41:21 PM PDT 24 |
Aug 09 05:53:27 PM PDT 24 |
44544222311 ps |
| T891 |
/workspace/coverage/default/10.sram_ctrl_smoke.3828356387 |
|
|
Aug 09 05:41:35 PM PDT 24 |
Aug 09 05:41:38 PM PDT 24 |
1188366584 ps |
| T892 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1641846215 |
|
|
Aug 09 05:44:25 PM PDT 24 |
Aug 09 05:59:38 PM PDT 24 |
4254032571 ps |
| T893 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.368518806 |
|
|
Aug 09 05:41:17 PM PDT 24 |
Aug 09 05:41:23 PM PDT 24 |
1326192855 ps |
| T894 |
/workspace/coverage/default/1.sram_ctrl_partial_access.2480966484 |
|
|
Aug 09 05:41:01 PM PDT 24 |
Aug 09 05:41:38 PM PDT 24 |
538087643 ps |
| T895 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.3305299955 |
|
|
Aug 09 05:44:21 PM PDT 24 |
Aug 09 05:54:50 PM PDT 24 |
37878430526 ps |
| T896 |
/workspace/coverage/default/28.sram_ctrl_regwen.2703067532 |
|
|
Aug 09 05:43:19 PM PDT 24 |
Aug 09 06:05:32 PM PDT 24 |
12625636140 ps |
| T897 |
/workspace/coverage/default/41.sram_ctrl_partial_access.639993155 |
|
|
Aug 09 05:45:01 PM PDT 24 |
Aug 09 05:45:02 PM PDT 24 |
44877842 ps |
| T898 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.4106989894 |
|
|
Aug 09 05:46:22 PM PDT 24 |
Aug 09 05:57:56 PM PDT 24 |
2301797159 ps |
| T899 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3844842607 |
|
|
Aug 09 05:41:08 PM PDT 24 |
Aug 09 05:46:45 PM PDT 24 |
66584479002 ps |
| T900 |
/workspace/coverage/default/21.sram_ctrl_executable.1938319594 |
|
|
Aug 09 05:42:29 PM PDT 24 |
Aug 09 06:03:49 PM PDT 24 |
14105628263 ps |
| T901 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3426846403 |
|
|
Aug 09 05:43:15 PM PDT 24 |
Aug 09 05:49:44 PM PDT 24 |
30140775347 ps |
| T902 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3801978925 |
|
|
Aug 09 05:45:49 PM PDT 24 |
Aug 09 05:47:59 PM PDT 24 |
3781101499 ps |
| T903 |
/workspace/coverage/default/9.sram_ctrl_bijection.3160756189 |
|
|
Aug 09 05:41:23 PM PDT 24 |
Aug 09 05:42:19 PM PDT 24 |
2557503488 ps |
| T904 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1991110870 |
|
|
Aug 09 05:41:45 PM PDT 24 |
Aug 09 05:43:52 PM PDT 24 |
2828204876 ps |
| T905 |
/workspace/coverage/default/5.sram_ctrl_stress_all.1491313174 |
|
|
Aug 09 05:41:18 PM PDT 24 |
Aug 09 06:32:05 PM PDT 24 |
148597648404 ps |
| T906 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2653582656 |
|
|
Aug 09 05:45:21 PM PDT 24 |
Aug 09 05:47:33 PM PDT 24 |
687632859 ps |
| T907 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3223351610 |
|
|
Aug 09 05:41:13 PM PDT 24 |
Aug 09 05:55:10 PM PDT 24 |
4618545093 ps |
| T908 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.175983075 |
|
|
Aug 09 05:45:24 PM PDT 24 |
Aug 09 05:46:17 PM PDT 24 |
370379364 ps |
| T909 |
/workspace/coverage/default/19.sram_ctrl_smoke.244189237 |
|
|
Aug 09 05:42:16 PM PDT 24 |
Aug 09 05:42:25 PM PDT 24 |
380027271 ps |
| T910 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.760592478 |
|
|
Aug 09 05:44:45 PM PDT 24 |
Aug 09 05:50:04 PM PDT 24 |
68399923932 ps |
| T911 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2675875462 |
|
|
Aug 09 05:42:25 PM PDT 24 |
Aug 09 05:45:24 PM PDT 24 |
1878784556 ps |
| T912 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2150416475 |
|
|
Aug 09 05:41:08 PM PDT 24 |
Aug 09 05:41:09 PM PDT 24 |
49725414 ps |
| T913 |
/workspace/coverage/default/20.sram_ctrl_executable.3052489675 |
|
|
Aug 09 05:42:29 PM PDT 24 |
Aug 09 05:50:00 PM PDT 24 |
4775423009 ps |
| T914 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.4140332294 |
|
|
Aug 09 05:44:54 PM PDT 24 |
Aug 09 05:45:00 PM PDT 24 |
914626034 ps |
| T915 |
/workspace/coverage/default/15.sram_ctrl_regwen.396439478 |
|
|
Aug 09 05:41:56 PM PDT 24 |
Aug 09 05:59:20 PM PDT 24 |
11655944832 ps |
| T916 |
/workspace/coverage/default/24.sram_ctrl_partial_access.195021320 |
|
|
Aug 09 05:42:52 PM PDT 24 |
Aug 09 05:44:09 PM PDT 24 |
2522321689 ps |
| T917 |
/workspace/coverage/default/40.sram_ctrl_regwen.53294202 |
|
|
Aug 09 05:44:57 PM PDT 24 |
Aug 09 05:57:41 PM PDT 24 |
14142332883 ps |
| T918 |
/workspace/coverage/default/19.sram_ctrl_executable.1954791151 |
|
|
Aug 09 05:42:17 PM PDT 24 |
Aug 09 06:07:27 PM PDT 24 |
85945722227 ps |
| T919 |
/workspace/coverage/default/18.sram_ctrl_alert_test.665459791 |
|
|
Aug 09 05:42:18 PM PDT 24 |
Aug 09 05:42:19 PM PDT 24 |
15834348 ps |
| T920 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1414326394 |
|
|
Aug 09 05:41:49 PM PDT 24 |
Aug 09 05:41:50 PM PDT 24 |
183582787 ps |
| T921 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.416940718 |
|
|
Aug 09 05:44:51 PM PDT 24 |
Aug 09 05:54:15 PM PDT 24 |
2271825257 ps |
| T922 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3677580488 |
|
|
Aug 09 05:46:15 PM PDT 24 |
Aug 09 05:46:18 PM PDT 24 |
495320225 ps |
| T923 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3540048943 |
|
|
Aug 09 05:45:48 PM PDT 24 |
Aug 09 05:48:03 PM PDT 24 |
3523065991 ps |
| T924 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.99915416 |
|
|
Aug 09 05:46:22 PM PDT 24 |
Aug 09 05:46:26 PM PDT 24 |
258291001 ps |
| T925 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.958983433 |
|
|
Aug 09 05:41:15 PM PDT 24 |
Aug 09 05:45:55 PM PDT 24 |
689029107 ps |
| T926 |
/workspace/coverage/default/46.sram_ctrl_partial_access.2792056850 |
|
|
Aug 09 05:45:48 PM PDT 24 |
Aug 09 05:46:02 PM PDT 24 |
4171274798 ps |
| T927 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.554093267 |
|
|
Aug 09 05:40:53 PM PDT 24 |
Aug 09 05:43:47 PM PDT 24 |
23267954488 ps |
| T928 |
/workspace/coverage/default/34.sram_ctrl_alert_test.4067175167 |
|
|
Aug 09 05:44:11 PM PDT 24 |
Aug 09 05:44:11 PM PDT 24 |
28594408 ps |
| T929 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2824960591 |
|
|
Aug 09 04:33:26 PM PDT 24 |
Aug 09 04:33:28 PM PDT 24 |
75401843 ps |
| T65 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.788999015 |
|
|
Aug 09 04:33:40 PM PDT 24 |
Aug 09 04:33:41 PM PDT 24 |
354316014 ps |
| T57 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3962377779 |
|
|
Aug 09 04:33:30 PM PDT 24 |
Aug 09 04:33:32 PM PDT 24 |
171609068 ps |
| T66 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3678769615 |
|
|
Aug 09 04:33:45 PM PDT 24 |
Aug 09 04:33:49 PM PDT 24 |
443051475 ps |
| T58 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2963670132 |
|
|
Aug 09 04:33:49 PM PDT 24 |
Aug 09 04:33:52 PM PDT 24 |
331015144 ps |
| T72 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.478873501 |
|
|
Aug 09 04:33:31 PM PDT 24 |
Aug 09 04:33:32 PM PDT 24 |
34693849 ps |
| T73 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1996751487 |
|
|
Aug 09 04:33:42 PM PDT 24 |
Aug 09 04:33:45 PM PDT 24 |
800884458 ps |
| T96 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.650157605 |
|
|
Aug 09 04:33:51 PM PDT 24 |
Aug 09 04:33:52 PM PDT 24 |
127349989 ps |
| T930 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1555503557 |
|
|
Aug 09 04:33:41 PM PDT 24 |
Aug 09 04:33:42 PM PDT 24 |
41314339 ps |
| T931 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1494617319 |
|
|
Aug 09 04:33:37 PM PDT 24 |
Aug 09 04:33:40 PM PDT 24 |
79734267 ps |
| T59 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.146660863 |
|
|
Aug 09 04:33:50 PM PDT 24 |
Aug 09 04:33:51 PM PDT 24 |
363498053 ps |
| T932 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1637277090 |
|
|
Aug 09 04:33:44 PM PDT 24 |
Aug 09 04:33:45 PM PDT 24 |
47135985 ps |
| T104 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3062519225 |
|
|
Aug 09 04:33:28 PM PDT 24 |
Aug 09 04:33:29 PM PDT 24 |
36334760 ps |
| T74 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.159461847 |
|
|
Aug 09 04:33:17 PM PDT 24 |
Aug 09 04:33:18 PM PDT 24 |
39978736 ps |
| T105 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2393096751 |
|
|
Aug 09 04:33:34 PM PDT 24 |
Aug 09 04:33:35 PM PDT 24 |
73704930 ps |
| T933 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.564669974 |
|
|
Aug 09 04:33:36 PM PDT 24 |
Aug 09 04:33:38 PM PDT 24 |
128288394 ps |
| T934 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4186452326 |
|
|
Aug 09 04:33:35 PM PDT 24 |
Aug 09 04:33:36 PM PDT 24 |
86220978 ps |
| T75 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.287462930 |
|
|
Aug 09 04:33:38 PM PDT 24 |
Aug 09 04:33:39 PM PDT 24 |
61661406 ps |
| T935 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.742013621 |
|
|
Aug 09 04:33:42 PM PDT 24 |
Aug 09 04:33:44 PM PDT 24 |
188003550 ps |
| T106 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1220997706 |
|
|
Aug 09 04:33:17 PM PDT 24 |
Aug 09 04:33:18 PM PDT 24 |
13352637 ps |
| T124 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3969276015 |
|
|
Aug 09 04:33:46 PM PDT 24 |
Aug 09 04:33:49 PM PDT 24 |
331742880 ps |
| T936 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.416324896 |
|
|
Aug 09 04:33:44 PM PDT 24 |
Aug 09 04:33:46 PM PDT 24 |
65748700 ps |
| T937 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3507518991 |
|
|
Aug 09 04:33:55 PM PDT 24 |
Aug 09 04:33:58 PM PDT 24 |
120787920 ps |
| T76 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1832462876 |
|
|
Aug 09 04:33:58 PM PDT 24 |
Aug 09 04:33:59 PM PDT 24 |
51435020 ps |
| T122 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3260633977 |
|
|
Aug 09 04:34:00 PM PDT 24 |
Aug 09 04:34:02 PM PDT 24 |
90029063 ps |
| T77 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2270357893 |
|
|
Aug 09 04:33:22 PM PDT 24 |
Aug 09 04:33:23 PM PDT 24 |
30629216 ps |
| T938 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3464886498 |
|
|
Aug 09 04:33:41 PM PDT 24 |
Aug 09 04:33:42 PM PDT 24 |
72683994 ps |
| T78 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3770429246 |
|
|
Aug 09 04:33:33 PM PDT 24 |
Aug 09 04:33:35 PM PDT 24 |
355586846 ps |
| T97 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3618284873 |
|
|
Aug 09 04:33:45 PM PDT 24 |
Aug 09 04:33:45 PM PDT 24 |
25097818 ps |
| T126 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3610217328 |
|
|
Aug 09 04:33:35 PM PDT 24 |
Aug 09 04:33:37 PM PDT 24 |
175704908 ps |
| T79 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3898728180 |
|
|
Aug 09 04:33:28 PM PDT 24 |
Aug 09 04:33:30 PM PDT 24 |
886623043 ps |
| T939 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3436127801 |
|
|
Aug 09 04:33:57 PM PDT 24 |
Aug 09 04:33:58 PM PDT 24 |
137465957 ps |
| T940 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1683180056 |
|
|
Aug 09 04:33:23 PM PDT 24 |
Aug 09 04:33:27 PM PDT 24 |
154843805 ps |
| T941 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1909071777 |
|
|
Aug 09 04:33:29 PM PDT 24 |
Aug 09 04:33:31 PM PDT 24 |
57811051 ps |
| T120 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3364620628 |
|
|
Aug 09 04:33:23 PM PDT 24 |
Aug 09 04:33:26 PM PDT 24 |
866415681 ps |
| T98 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1730213303 |
|
|
Aug 09 04:33:37 PM PDT 24 |
Aug 09 04:33:39 PM PDT 24 |
409772330 ps |
| T121 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3102424138 |
|
|
Aug 09 04:33:57 PM PDT 24 |
Aug 09 04:33:59 PM PDT 24 |
207910071 ps |
| T123 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2277591964 |
|
|
Aug 09 04:33:19 PM PDT 24 |
Aug 09 04:33:21 PM PDT 24 |
255598441 ps |
| T83 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2991365883 |
|
|
Aug 09 04:33:41 PM PDT 24 |
Aug 09 04:33:43 PM PDT 24 |
248651586 ps |
| T84 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3925263268 |
|
|
Aug 09 04:33:57 PM PDT 24 |
Aug 09 04:34:01 PM PDT 24 |
766945903 ps |
| T942 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.455483306 |
|
|
Aug 09 04:33:27 PM PDT 24 |
Aug 09 04:33:28 PM PDT 24 |
88954165 ps |
| T129 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1405121941 |
|
|
Aug 09 04:33:47 PM PDT 24 |
Aug 09 04:33:49 PM PDT 24 |
269378314 ps |
| T130 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2726522395 |
|
|
Aug 09 04:33:48 PM PDT 24 |
Aug 09 04:33:50 PM PDT 24 |
307735094 ps |
| T943 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1741532129 |
|
|
Aug 09 04:33:38 PM PDT 24 |
Aug 09 04:33:39 PM PDT 24 |
257028117 ps |
| T127 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4228035964 |
|
|
Aug 09 04:33:48 PM PDT 24 |
Aug 09 04:33:50 PM PDT 24 |
476974972 ps |
| T944 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1205946419 |
|
|
Aug 09 04:33:58 PM PDT 24 |
Aug 09 04:33:59 PM PDT 24 |
95512392 ps |
| T85 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2118867237 |
|
|
Aug 09 04:33:59 PM PDT 24 |
Aug 09 04:34:01 PM PDT 24 |
755075700 ps |
| T945 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4098608115 |
|
|
Aug 09 04:33:33 PM PDT 24 |
Aug 09 04:33:34 PM PDT 24 |
34658277 ps |
| T946 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2966567615 |
|
|
Aug 09 04:33:31 PM PDT 24 |
Aug 09 04:33:34 PM PDT 24 |
84208917 ps |
| T947 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.350062607 |
|
|
Aug 09 04:33:50 PM PDT 24 |
Aug 09 04:33:52 PM PDT 24 |
308014151 ps |
| T948 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.844918380 |
|
|
Aug 09 04:33:37 PM PDT 24 |
Aug 09 04:33:39 PM PDT 24 |
24814836 ps |
| T949 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2144063121 |
|
|
Aug 09 04:33:42 PM PDT 24 |
Aug 09 04:33:42 PM PDT 24 |
31736837 ps |
| T950 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2330376183 |
|
|
Aug 09 04:33:36 PM PDT 24 |
Aug 09 04:33:40 PM PDT 24 |
140070290 ps |
| T951 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.237400592 |
|
|
Aug 09 04:33:52 PM PDT 24 |
Aug 09 04:33:53 PM PDT 24 |
57851642 ps |
| T952 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.921518372 |
|
|
Aug 09 04:33:53 PM PDT 24 |
Aug 09 04:33:54 PM PDT 24 |
17345605 ps |
| T953 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4118128294 |
|
|
Aug 09 04:33:41 PM PDT 24 |
Aug 09 04:33:42 PM PDT 24 |
53801230 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3111500979 |
|
|
Aug 09 04:33:27 PM PDT 24 |
Aug 09 04:33:28 PM PDT 24 |
88525018 ps |
| T955 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.328064639 |
|
|
Aug 09 04:33:24 PM PDT 24 |
Aug 09 04:33:25 PM PDT 24 |
19589967 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3161331005 |
|
|
Aug 09 04:33:51 PM PDT 24 |
Aug 09 04:33:51 PM PDT 24 |
58335205 ps |
| T957 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.650477794 |
|
|
Aug 09 04:33:42 PM PDT 24 |
Aug 09 04:33:43 PM PDT 24 |
18954568 ps |
| T86 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.62785072 |
|
|
Aug 09 04:33:19 PM PDT 24 |
Aug 09 04:33:22 PM PDT 24 |
485816469 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2301049469 |
|
|
Aug 09 04:33:29 PM PDT 24 |
Aug 09 04:33:30 PM PDT 24 |
53998499 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3388072556 |
|
|
Aug 09 04:33:35 PM PDT 24 |
Aug 09 04:33:36 PM PDT 24 |
37405765 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3178047317 |
|
|
Aug 09 04:33:40 PM PDT 24 |
Aug 09 04:33:41 PM PDT 24 |
222973443 ps |
| T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.104818264 |
|
|
Aug 09 04:33:31 PM PDT 24 |
Aug 09 04:33:33 PM PDT 24 |
848066448 ps |
| T962 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2118705655 |
|
|
Aug 09 04:33:52 PM PDT 24 |
Aug 09 04:33:53 PM PDT 24 |
11983333 ps |
| T125 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1991837606 |
|
|
Aug 09 04:33:34 PM PDT 24 |
Aug 09 04:33:36 PM PDT 24 |
354886356 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1145168571 |
|
|
Aug 09 04:33:41 PM PDT 24 |
Aug 09 04:33:44 PM PDT 24 |
96907703 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.693798745 |
|
|
Aug 09 04:33:27 PM PDT 24 |
Aug 09 04:33:31 PM PDT 24 |
567265599 ps |
| T128 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3276146226 |
|
|
Aug 09 04:33:37 PM PDT 24 |
Aug 09 04:33:41 PM PDT 24 |
4016753819 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2741588207 |
|
|
Aug 09 04:33:38 PM PDT 24 |
Aug 09 04:33:39 PM PDT 24 |
19619335 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1693208645 |
|
|
Aug 09 04:33:44 PM PDT 24 |
Aug 09 04:33:46 PM PDT 24 |
824502430 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2261987109 |
|
|
Aug 09 04:33:21 PM PDT 24 |
Aug 09 04:33:22 PM PDT 24 |
160667598 ps |
| T968 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.702368216 |
|
|
Aug 09 04:33:47 PM PDT 24 |
Aug 09 04:33:50 PM PDT 24 |
1130679323 ps |
| T969 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.266627276 |
|
|
Aug 09 04:33:23 PM PDT 24 |
Aug 09 04:33:24 PM PDT 24 |
40692596 ps |
| T970 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.771090937 |
|
|
Aug 09 04:33:44 PM PDT 24 |
Aug 09 04:33:46 PM PDT 24 |
564298528 ps |
| T971 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2849023898 |
|
|
Aug 09 04:33:38 PM PDT 24 |
Aug 09 04:33:38 PM PDT 24 |
71740902 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4060828467 |
|
|
Aug 09 04:33:35 PM PDT 24 |
Aug 09 04:33:36 PM PDT 24 |
45794682 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4062544863 |
|
|
Aug 09 04:33:19 PM PDT 24 |
Aug 09 04:33:20 PM PDT 24 |
23561363 ps |
| T974 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3802827721 |
|
|
Aug 09 04:33:44 PM PDT 24 |
Aug 09 04:33:45 PM PDT 24 |
54829173 ps |
| T87 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1451554951 |
|
|
Aug 09 04:33:52 PM PDT 24 |
Aug 09 04:33:55 PM PDT 24 |
1755571958 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4250648428 |
|
|
Aug 09 04:33:29 PM PDT 24 |
Aug 09 04:33:31 PM PDT 24 |
248787524 ps |
| T976 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4165605983 |
|
|
Aug 09 04:33:30 PM PDT 24 |
Aug 09 04:33:32 PM PDT 24 |
326155331 ps |
| T977 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2631517726 |
|
|
Aug 09 04:33:23 PM PDT 24 |
Aug 09 04:33:24 PM PDT 24 |
19431703 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3649820701 |
|
|
Aug 09 04:33:29 PM PDT 24 |
Aug 09 04:33:30 PM PDT 24 |
32957103 ps |
| T979 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3090598341 |
|
|
Aug 09 04:33:32 PM PDT 24 |
Aug 09 04:33:32 PM PDT 24 |
33491220 ps |
| T93 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2531949095 |
|
|
Aug 09 04:33:29 PM PDT 24 |
Aug 09 04:33:31 PM PDT 24 |
769032293 ps |
| T94 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3172888061 |
|
|
Aug 09 04:33:42 PM PDT 24 |
Aug 09 04:33:44 PM PDT 24 |
1482011705 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.921811758 |
|
|
Aug 09 04:33:28 PM PDT 24 |
Aug 09 04:33:29 PM PDT 24 |
134778078 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2853028075 |
|
|
Aug 09 04:33:46 PM PDT 24 |
Aug 09 04:33:47 PM PDT 24 |
14758794 ps |
| T131 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3756323634 |
|
|
Aug 09 04:33:29 PM PDT 24 |
Aug 09 04:33:30 PM PDT 24 |
90698144 ps |
| T982 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1832721268 |
|
|
Aug 09 04:33:37 PM PDT 24 |
Aug 09 04:33:38 PM PDT 24 |
58558364 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1982166618 |
|
|
Aug 09 04:33:29 PM PDT 24 |
Aug 09 04:33:30 PM PDT 24 |
53543306 ps |
| T984 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2669707950 |
|
|
Aug 09 04:33:30 PM PDT 24 |
Aug 09 04:33:30 PM PDT 24 |
16610833 ps |
| T985 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1201198966 |
|
|
Aug 09 04:33:17 PM PDT 24 |
Aug 09 04:33:18 PM PDT 24 |
19067618 ps |
| T986 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2692830391 |
|
|
Aug 09 04:33:59 PM PDT 24 |
Aug 09 04:33:59 PM PDT 24 |
29865115 ps |
| T987 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.652813848 |
|
|
Aug 09 04:33:36 PM PDT 24 |
Aug 09 04:33:37 PM PDT 24 |
31313981 ps |
| T95 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2527773938 |
|
|
Aug 09 04:33:32 PM PDT 24 |
Aug 09 04:33:36 PM PDT 24 |
397443507 ps |
| T988 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2336848804 |
|
|
Aug 09 04:33:57 PM PDT 24 |
Aug 09 04:34:03 PM PDT 24 |
6309111260 ps |
| T989 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.573646523 |
|
|
Aug 09 04:33:41 PM PDT 24 |
Aug 09 04:33:42 PM PDT 24 |
13487640 ps |
| T990 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.116250952 |
|
|
Aug 09 04:33:43 PM PDT 24 |
Aug 09 04:33:44 PM PDT 24 |
17521671 ps |
| T991 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4238458787 |
|
|
Aug 09 04:33:41 PM PDT 24 |
Aug 09 04:33:42 PM PDT 24 |
142033625 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3145961500 |
|
|
Aug 09 04:33:44 PM PDT 24 |
Aug 09 04:33:47 PM PDT 24 |
151109204 ps |
| T993 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2312342631 |
|
|
Aug 09 04:33:58 PM PDT 24 |
Aug 09 04:34:01 PM PDT 24 |
111195700 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2619779475 |
|
|
Aug 09 04:33:55 PM PDT 24 |
Aug 09 04:33:56 PM PDT 24 |
40886568 ps |
| T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.804881256 |
|
|
Aug 09 04:33:34 PM PDT 24 |
Aug 09 04:33:36 PM PDT 24 |
453138765 ps |
| T996 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4155390078 |
|
|
Aug 09 04:33:38 PM PDT 24 |
Aug 09 04:33:39 PM PDT 24 |
79925372 ps |
| T997 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.459598105 |
|
|
Aug 09 04:33:33 PM PDT 24 |
Aug 09 04:33:35 PM PDT 24 |
104815287 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2228525714 |
|
|
Aug 09 04:33:34 PM PDT 24 |
Aug 09 04:33:37 PM PDT 24 |
369157163 ps |
| T999 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.800181037 |
|
|
Aug 09 04:33:33 PM PDT 24 |
Aug 09 04:33:36 PM PDT 24 |
2161856397 ps |
| T1000 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2119961759 |
|
|
Aug 09 04:33:34 PM PDT 24 |
Aug 09 04:33:38 PM PDT 24 |
45828873 ps |