Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145650960	1			T2	328048		T3	196		T4	635620
instr_valid_dis	114203729	1			T2	328048		T3	196		T4	635620
instr_en	24403311	1			T25	216644		T26	148602		T27	77744

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11283449	1			T25	84300		T26	10918		T27	5522
sram_ifetch_valid_disable	113468649	1			T2	328048		T3	196		T4	635620
sram_ifetch_enable	20898862	1			T25	92784		T26	144068		T27	228684

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145650960	1			T2	328048		T3	196		T4	635620
hw_debug_en_valid_off	110941750	1			T2	328048		T3	196		T4	635620
hw_debug_en_on	23247194	1			T25	142544		T26	170944		T27	151240

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113468649	1			T2	328048		T3	196		T4	635620
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100674193	1			T2	328048		T3	196		T4	635620
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9743188	1			T25	118546		T26	77378		T20	64558
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4107912	1			T25	60456		T20	49194		T109	56796
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1419990	1			T25	39626		T17	3484		T132	18870
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1968352	1			T25	20830		T20	49194		T109	56796
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4798325	1			T26	10918		T27	5522		T20	44136
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2504044	1			T26	10824		T20	7242		T109	4038
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1653713	1			T26	94		T27	5522		T20	36894
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9840203	1			T25	127400		T26	77142		T27	69178
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4725445	1			T25	93492		T26	33354		T27	34190
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3847794	1			T25	33908		T26	43788		T20	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9573866	1			T25	53424		T26	71130		T27	72222
lc_exec_en	8608666	1			T25	15144		T26	82884		T27	76540
valid_exec_dis	107509566	1			T2	328048		T3	196		T4	635620
invalid_exec_dis	32182311	1			T25	177084		T26	154986		T27	234206