Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42917866	1			T2	149057		T3	98		T4	287405
triple_byte_access	2562164	1			T2	2945		T4	5719		T5	2
halfword_access	3844937	1			T2	4586		T4	8491		T5	7
byte_access	5134006	1			T2	5973		T4	11646		T5	8
zero_access	1293700	1			T2	1463		T4	2953		T5	4

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27831038

1

T2

82353

T3

43

T4

158255

auto[1]

27921635

1

T2

81671

T3

55

T4

157959

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21417144	1			T2	74769		T3	43		T4	143787
auto[0]	triple_byte_access	1276867	1			T2	1508		T4	2956		T5	2
auto[0]	halfword_access	1920294	1			T2	2321		T4	4225		T5	6
auto[0]	byte_access	2566022	1			T2	3010		T4	5830		T5	2
auto[0]	zero_access	650711	1			T2	745		T4	1457		T5	2
auto[1]	word_access	21500722	1			T2	74288		T3	55		T4	143618
auto[1]	triple_byte_access	1285297	1			T2	1437		T4	2763		T8	108
auto[1]	halfword_access	1924643	1			T2	2265		T4	4266		T5	1
auto[1]	byte_access	2567984	1			T2	2963		T4	5816		T5	6
auto[1]	zero_access	642989	1			T2	718		T4	1496		T5	2