| T794 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1860799436 |
|
|
Aug 10 04:44:00 PM PDT 24 |
Aug 10 04:44:01 PM PDT 24 |
12868039 ps |
| T795 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.3956838594 |
|
|
Aug 10 04:45:18 PM PDT 24 |
Aug 10 04:45:26 PM PDT 24 |
4417652339 ps |
| T796 |
/workspace/coverage/default/5.sram_ctrl_alert_test.2362570496 |
|
|
Aug 10 04:43:09 PM PDT 24 |
Aug 10 04:43:10 PM PDT 24 |
31197466 ps |
| T797 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1809531777 |
|
|
Aug 10 04:50:07 PM PDT 24 |
Aug 10 04:50:08 PM PDT 24 |
42447938 ps |
| T798 |
/workspace/coverage/default/17.sram_ctrl_executable.3485314064 |
|
|
Aug 10 04:44:10 PM PDT 24 |
Aug 10 05:13:12 PM PDT 24 |
49196797181 ps |
| T799 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.1760064337 |
|
|
Aug 10 04:46:20 PM PDT 24 |
Aug 10 04:46:30 PM PDT 24 |
1012854693 ps |
| T800 |
/workspace/coverage/default/42.sram_ctrl_partial_access.3760717930 |
|
|
Aug 10 04:48:33 PM PDT 24 |
Aug 10 04:48:42 PM PDT 24 |
763732438 ps |
| T801 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3063908205 |
|
|
Aug 10 04:44:17 PM PDT 24 |
Aug 10 04:47:07 PM PDT 24 |
156880385 ps |
| T802 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3133175963 |
|
|
Aug 10 04:45:41 PM PDT 24 |
Aug 10 04:49:38 PM PDT 24 |
8992987305 ps |
| T803 |
/workspace/coverage/default/31.sram_ctrl_smoke.698458528 |
|
|
Aug 10 04:46:10 PM PDT 24 |
Aug 10 04:46:46 PM PDT 24 |
1710131790 ps |
| T804 |
/workspace/coverage/default/11.sram_ctrl_alert_test.2159496094 |
|
|
Aug 10 04:43:26 PM PDT 24 |
Aug 10 04:43:27 PM PDT 24 |
27001105 ps |
| T805 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.2402302855 |
|
|
Aug 10 04:43:51 PM PDT 24 |
Aug 10 04:44:31 PM PDT 24 |
389806192 ps |
| T806 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1679863113 |
|
|
Aug 10 04:42:51 PM PDT 24 |
Aug 10 05:35:27 PM PDT 24 |
34797850407 ps |
| T807 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.214457627 |
|
|
Aug 10 04:43:19 PM PDT 24 |
Aug 10 04:45:39 PM PDT 24 |
149662314 ps |
| T808 |
/workspace/coverage/default/14.sram_ctrl_partial_access.1006534172 |
|
|
Aug 10 04:43:44 PM PDT 24 |
Aug 10 04:44:34 PM PDT 24 |
2588450286 ps |
| T107 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2999233845 |
|
|
Aug 10 04:43:24 PM PDT 24 |
Aug 10 04:43:40 PM PDT 24 |
496980060 ps |
| T809 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1382409923 |
|
|
Aug 10 04:43:13 PM PDT 24 |
Aug 10 04:45:23 PM PDT 24 |
1807203408 ps |
| T810 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.3467494586 |
|
|
Aug 10 04:43:08 PM PDT 24 |
Aug 10 04:43:09 PM PDT 24 |
85417652 ps |
| T811 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.890040412 |
|
|
Aug 10 04:46:11 PM PDT 24 |
Aug 10 04:54:17 PM PDT 24 |
18701387716 ps |
| T108 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.554562369 |
|
|
Aug 10 04:45:01 PM PDT 24 |
Aug 10 04:45:56 PM PDT 24 |
3525489303 ps |
| T812 |
/workspace/coverage/default/6.sram_ctrl_bijection.3216985352 |
|
|
Aug 10 04:43:14 PM PDT 24 |
Aug 10 04:43:39 PM PDT 24 |
2048268056 ps |
| T813 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.43600949 |
|
|
Aug 10 04:47:28 PM PDT 24 |
Aug 10 04:47:38 PM PDT 24 |
176521446 ps |
| T29 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2105745232 |
|
|
Aug 10 04:43:08 PM PDT 24 |
Aug 10 04:43:11 PM PDT 24 |
255345094 ps |
| T814 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2317186836 |
|
|
Aug 10 04:46:39 PM PDT 24 |
Aug 10 04:51:28 PM PDT 24 |
3939331855 ps |
| T815 |
/workspace/coverage/default/42.sram_ctrl_smoke.452572122 |
|
|
Aug 10 04:48:25 PM PDT 24 |
Aug 10 04:48:44 PM PDT 24 |
15419454244 ps |
| T816 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1253892648 |
|
|
Aug 10 04:47:21 PM PDT 24 |
Aug 10 05:11:02 PM PDT 24 |
15083897328 ps |
| T817 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.485281737 |
|
|
Aug 10 04:50:07 PM PDT 24 |
Aug 10 04:56:29 PM PDT 24 |
19271476234 ps |
| T818 |
/workspace/coverage/default/47.sram_ctrl_stress_all.544560516 |
|
|
Aug 10 04:49:57 PM PDT 24 |
Aug 10 06:23:18 PM PDT 24 |
251843770521 ps |
| T819 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1338611018 |
|
|
Aug 10 04:47:52 PM PDT 24 |
Aug 10 04:47:53 PM PDT 24 |
27118445 ps |
| T820 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.551122386 |
|
|
Aug 10 04:44:51 PM PDT 24 |
Aug 10 04:44:54 PM PDT 24 |
97569770 ps |
| T821 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1079216213 |
|
|
Aug 10 04:47:22 PM PDT 24 |
Aug 10 04:50:04 PM PDT 24 |
309910124 ps |
| T822 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.1841357004 |
|
|
Aug 10 04:45:08 PM PDT 24 |
Aug 10 04:54:54 PM PDT 24 |
1852851078 ps |
| T823 |
/workspace/coverage/default/7.sram_ctrl_executable.645279889 |
|
|
Aug 10 04:43:19 PM PDT 24 |
Aug 10 04:57:53 PM PDT 24 |
18917818741 ps |
| T824 |
/workspace/coverage/default/2.sram_ctrl_regwen.3252151112 |
|
|
Aug 10 04:42:57 PM PDT 24 |
Aug 10 04:51:54 PM PDT 24 |
5432245101 ps |
| T825 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2902591023 |
|
|
Aug 10 04:48:47 PM PDT 24 |
Aug 10 04:48:48 PM PDT 24 |
45200197 ps |
| T826 |
/workspace/coverage/default/28.sram_ctrl_alert_test.2677813310 |
|
|
Aug 10 04:45:43 PM PDT 24 |
Aug 10 04:45:44 PM PDT 24 |
11272669 ps |
| T827 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1732799157 |
|
|
Aug 10 04:46:29 PM PDT 24 |
Aug 10 04:50:28 PM PDT 24 |
33244972178 ps |
| T828 |
/workspace/coverage/default/44.sram_ctrl_partial_access.1652086928 |
|
|
Aug 10 04:48:56 PM PDT 24 |
Aug 10 04:50:21 PM PDT 24 |
1132128819 ps |
| T829 |
/workspace/coverage/default/23.sram_ctrl_executable.2082770863 |
|
|
Aug 10 04:44:51 PM PDT 24 |
Aug 10 05:03:34 PM PDT 24 |
24161528209 ps |
| T830 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.230516846 |
|
|
Aug 10 04:44:45 PM PDT 24 |
Aug 10 04:45:04 PM PDT 24 |
917965046 ps |
| T831 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1635751914 |
|
|
Aug 10 04:42:51 PM PDT 24 |
Aug 10 04:42:52 PM PDT 24 |
27880262 ps |
| T832 |
/workspace/coverage/default/6.sram_ctrl_regwen.3400804899 |
|
|
Aug 10 04:43:19 PM PDT 24 |
Aug 10 05:20:28 PM PDT 24 |
98457454907 ps |
| T833 |
/workspace/coverage/default/16.sram_ctrl_bijection.1429005650 |
|
|
Aug 10 04:44:01 PM PDT 24 |
Aug 10 04:45:17 PM PDT 24 |
6568554269 ps |
| T834 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.319820994 |
|
|
Aug 10 04:44:22 PM PDT 24 |
Aug 10 04:44:34 PM PDT 24 |
72603581 ps |
| T835 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.193351268 |
|
|
Aug 10 04:48:58 PM PDT 24 |
Aug 10 04:49:17 PM PDT 24 |
162578131 ps |
| T836 |
/workspace/coverage/default/10.sram_ctrl_regwen.1828569580 |
|
|
Aug 10 04:43:33 PM PDT 24 |
Aug 10 05:02:50 PM PDT 24 |
2338607148 ps |
| T837 |
/workspace/coverage/default/0.sram_ctrl_regwen.2548815201 |
|
|
Aug 10 04:42:44 PM PDT 24 |
Aug 10 04:47:30 PM PDT 24 |
7682942928 ps |
| T838 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.217168860 |
|
|
Aug 10 04:43:20 PM PDT 24 |
Aug 10 04:44:10 PM PDT 24 |
1080517710 ps |
| T839 |
/workspace/coverage/default/10.sram_ctrl_partial_access.670334150 |
|
|
Aug 10 04:43:28 PM PDT 24 |
Aug 10 04:43:41 PM PDT 24 |
799634562 ps |
| T840 |
/workspace/coverage/default/32.sram_ctrl_alert_test.1187462917 |
|
|
Aug 10 04:46:30 PM PDT 24 |
Aug 10 04:46:31 PM PDT 24 |
37304191 ps |
| T841 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.378669293 |
|
|
Aug 10 04:48:32 PM PDT 24 |
Aug 10 04:48:34 PM PDT 24 |
40009708 ps |
| T842 |
/workspace/coverage/default/25.sram_ctrl_executable.2096389209 |
|
|
Aug 10 04:45:10 PM PDT 24 |
Aug 10 04:56:18 PM PDT 24 |
4946284440 ps |
| T843 |
/workspace/coverage/default/6.sram_ctrl_alert_test.65885537 |
|
|
Aug 10 04:43:18 PM PDT 24 |
Aug 10 04:43:19 PM PDT 24 |
24293710 ps |
| T844 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1128587575 |
|
|
Aug 10 04:49:59 PM PDT 24 |
Aug 10 04:51:27 PM PDT 24 |
229096546 ps |
| T845 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.228125151 |
|
|
Aug 10 04:46:18 PM PDT 24 |
Aug 10 04:47:27 PM PDT 24 |
1467243505 ps |
| T846 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3889278914 |
|
|
Aug 10 04:46:56 PM PDT 24 |
Aug 10 04:49:02 PM PDT 24 |
283641973 ps |
| T847 |
/workspace/coverage/default/46.sram_ctrl_executable.4069344965 |
|
|
Aug 10 04:49:31 PM PDT 24 |
Aug 10 04:51:16 PM PDT 24 |
3646496584 ps |
| T848 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1594728710 |
|
|
Aug 10 04:43:53 PM PDT 24 |
Aug 10 04:48:54 PM PDT 24 |
6181272343 ps |
| T849 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3225681483 |
|
|
Aug 10 04:44:35 PM PDT 24 |
Aug 10 04:47:04 PM PDT 24 |
132726898 ps |
| T850 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1627267013 |
|
|
Aug 10 04:42:58 PM PDT 24 |
Aug 10 04:43:01 PM PDT 24 |
43760657 ps |
| T851 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2775869925 |
|
|
Aug 10 04:42:59 PM PDT 24 |
Aug 10 04:49:42 PM PDT 24 |
5569044324 ps |
| T852 |
/workspace/coverage/default/35.sram_ctrl_regwen.796986797 |
|
|
Aug 10 04:46:55 PM PDT 24 |
Aug 10 05:02:57 PM PDT 24 |
12267035935 ps |
| T853 |
/workspace/coverage/default/12.sram_ctrl_partial_access.659950196 |
|
|
Aug 10 04:43:32 PM PDT 24 |
Aug 10 04:43:37 PM PDT 24 |
87583851 ps |
| T854 |
/workspace/coverage/default/27.sram_ctrl_regwen.3472916469 |
|
|
Aug 10 04:45:34 PM PDT 24 |
Aug 10 04:52:41 PM PDT 24 |
7474056562 ps |
| T855 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.2708611288 |
|
|
Aug 10 04:43:27 PM PDT 24 |
Aug 10 04:44:43 PM PDT 24 |
126468489 ps |
| T856 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1489672575 |
|
|
Aug 10 04:43:19 PM PDT 24 |
Aug 10 04:43:33 PM PDT 24 |
382896858 ps |
| T857 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1552515717 |
|
|
Aug 10 04:48:47 PM PDT 24 |
Aug 10 04:51:53 PM PDT 24 |
1772997371 ps |
| T858 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.851833205 |
|
|
Aug 10 04:44:01 PM PDT 24 |
Aug 10 04:44:07 PM PDT 24 |
2407982756 ps |
| T859 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2872622040 |
|
|
Aug 10 04:44:15 PM PDT 24 |
Aug 10 04:44:45 PM PDT 24 |
3439596254 ps |
| T860 |
/workspace/coverage/default/28.sram_ctrl_regwen.146861876 |
|
|
Aug 10 04:45:42 PM PDT 24 |
Aug 10 04:47:17 PM PDT 24 |
858389646 ps |
| T861 |
/workspace/coverage/default/36.sram_ctrl_alert_test.3113742479 |
|
|
Aug 10 04:47:11 PM PDT 24 |
Aug 10 04:47:12 PM PDT 24 |
29372126 ps |
| T862 |
/workspace/coverage/default/33.sram_ctrl_stress_all.2906397838 |
|
|
Aug 10 04:46:37 PM PDT 24 |
Aug 10 05:25:16 PM PDT 24 |
89671162560 ps |
| T863 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.328348382 |
|
|
Aug 10 04:48:17 PM PDT 24 |
Aug 10 04:48:24 PM PDT 24 |
4328818886 ps |
| T864 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1956074583 |
|
|
Aug 10 04:47:52 PM PDT 24 |
Aug 10 05:06:53 PM PDT 24 |
8025034986 ps |
| T865 |
/workspace/coverage/default/22.sram_ctrl_stress_all.3125602963 |
|
|
Aug 10 04:44:52 PM PDT 24 |
Aug 10 05:10:44 PM PDT 24 |
48408880162 ps |
| T866 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.627880387 |
|
|
Aug 10 04:44:51 PM PDT 24 |
Aug 10 04:44:57 PM PDT 24 |
458853730 ps |
| T867 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.367326173 |
|
|
Aug 10 04:43:45 PM PDT 24 |
Aug 10 04:44:07 PM PDT 24 |
3407413478 ps |
| T868 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2168472338 |
|
|
Aug 10 04:49:44 PM PDT 24 |
Aug 10 04:51:33 PM PDT 24 |
962312176 ps |
| T869 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3002912439 |
|
|
Aug 10 04:49:11 PM PDT 24 |
Aug 10 05:08:23 PM PDT 24 |
11734198263 ps |
| T870 |
/workspace/coverage/default/41.sram_ctrl_partial_access.355594174 |
|
|
Aug 10 04:48:14 PM PDT 24 |
Aug 10 04:49:07 PM PDT 24 |
555555926 ps |
| T871 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.4121865362 |
|
|
Aug 10 04:45:50 PM PDT 24 |
Aug 10 04:45:55 PM PDT 24 |
592319239 ps |
| T872 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2279003338 |
|
|
Aug 10 04:43:36 PM PDT 24 |
Aug 10 04:43:48 PM PDT 24 |
1638209405 ps |
| T873 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3757233088 |
|
|
Aug 10 04:43:19 PM PDT 24 |
Aug 10 04:52:29 PM PDT 24 |
93316564812 ps |
| T874 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1045510053 |
|
|
Aug 10 04:46:58 PM PDT 24 |
Aug 10 04:47:04 PM PDT 24 |
171638791 ps |
| T875 |
/workspace/coverage/default/26.sram_ctrl_regwen.2832859277 |
|
|
Aug 10 04:45:18 PM PDT 24 |
Aug 10 05:14:14 PM PDT 24 |
24698402854 ps |
| T876 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.1077366576 |
|
|
Aug 10 04:44:13 PM PDT 24 |
Aug 10 04:47:02 PM PDT 24 |
1315008242 ps |
| T877 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.4285133130 |
|
|
Aug 10 04:49:31 PM PDT 24 |
Aug 10 05:17:56 PM PDT 24 |
5610633404 ps |
| T878 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1378192345 |
|
|
Aug 10 04:45:16 PM PDT 24 |
Aug 10 04:45:17 PM PDT 24 |
48136804 ps |
| T879 |
/workspace/coverage/default/30.sram_ctrl_smoke.877873978 |
|
|
Aug 10 04:45:57 PM PDT 24 |
Aug 10 04:47:58 PM PDT 24 |
1337301624 ps |
| T880 |
/workspace/coverage/default/18.sram_ctrl_regwen.2654942264 |
|
|
Aug 10 04:44:14 PM PDT 24 |
Aug 10 05:02:20 PM PDT 24 |
15942976521 ps |
| T881 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.4267159109 |
|
|
Aug 10 04:49:09 PM PDT 24 |
Aug 10 04:54:05 PM PDT 24 |
12401199406 ps |
| T882 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1120917430 |
|
|
Aug 10 04:46:21 PM PDT 24 |
Aug 10 04:48:11 PM PDT 24 |
677822127 ps |
| T883 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3408963047 |
|
|
Aug 10 04:42:48 PM PDT 24 |
Aug 10 04:46:07 PM PDT 24 |
5329279913 ps |
| T884 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1260926792 |
|
|
Aug 10 04:48:47 PM PDT 24 |
Aug 10 05:01:41 PM PDT 24 |
9858141477 ps |
| T885 |
/workspace/coverage/default/16.sram_ctrl_alert_test.1217661435 |
|
|
Aug 10 04:44:09 PM PDT 24 |
Aug 10 04:44:10 PM PDT 24 |
41641609 ps |
| T886 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2152497157 |
|
|
Aug 10 04:50:11 PM PDT 24 |
Aug 10 04:50:14 PM PDT 24 |
112269914 ps |
| T887 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1989784817 |
|
|
Aug 10 04:43:47 PM PDT 24 |
Aug 10 04:48:02 PM PDT 24 |
21150429574 ps |
| T888 |
/workspace/coverage/default/47.sram_ctrl_alert_test.3428219840 |
|
|
Aug 10 04:49:56 PM PDT 24 |
Aug 10 04:49:56 PM PDT 24 |
74557438 ps |
| T889 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.521759390 |
|
|
Aug 10 04:43:12 PM PDT 24 |
Aug 10 04:43:52 PM PDT 24 |
107547218 ps |
| T890 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2166461066 |
|
|
Aug 10 04:43:28 PM PDT 24 |
Aug 10 04:43:29 PM PDT 24 |
15005149 ps |
| T891 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.4015984460 |
|
|
Aug 10 04:43:17 PM PDT 24 |
Aug 10 04:44:09 PM PDT 24 |
191594209 ps |
| T892 |
/workspace/coverage/default/27.sram_ctrl_stress_all.1098291148 |
|
|
Aug 10 04:45:35 PM PDT 24 |
Aug 10 06:27:49 PM PDT 24 |
212671474145 ps |
| T893 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.4084227093 |
|
|
Aug 10 04:45:27 PM PDT 24 |
Aug 10 04:50:06 PM PDT 24 |
6112660738 ps |
| T894 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2810576459 |
|
|
Aug 10 04:48:28 PM PDT 24 |
Aug 10 04:48:44 PM PDT 24 |
80621332 ps |
| T895 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3307141763 |
|
|
Aug 10 04:43:20 PM PDT 24 |
Aug 10 04:43:31 PM PDT 24 |
90477722 ps |
| T896 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2109063051 |
|
|
Aug 10 04:44:17 PM PDT 24 |
Aug 10 04:45:34 PM PDT 24 |
248443145 ps |
| T897 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.951332034 |
|
|
Aug 10 04:46:12 PM PDT 24 |
Aug 10 04:46:15 PM PDT 24 |
93821116 ps |
| T898 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.4024333821 |
|
|
Aug 10 04:46:18 PM PDT 24 |
Aug 10 04:46:20 PM PDT 24 |
1096353922 ps |
| T899 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2526916098 |
|
|
Aug 10 04:43:20 PM PDT 24 |
Aug 10 04:43:31 PM PDT 24 |
57821154 ps |
| T900 |
/workspace/coverage/default/19.sram_ctrl_bijection.1243579984 |
|
|
Aug 10 04:44:18 PM PDT 24 |
Aug 10 04:45:39 PM PDT 24 |
23612185229 ps |
| T901 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.4148986681 |
|
|
Aug 10 04:49:17 PM PDT 24 |
Aug 10 04:51:37 PM PDT 24 |
1982114986 ps |
| T902 |
/workspace/coverage/default/29.sram_ctrl_alert_test.666491384 |
|
|
Aug 10 04:45:58 PM PDT 24 |
Aug 10 04:45:58 PM PDT 24 |
31978565 ps |
| T903 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2164951529 |
|
|
Aug 10 04:43:19 PM PDT 24 |
Aug 10 04:52:12 PM PDT 24 |
38559189399 ps |
| T904 |
/workspace/coverage/default/27.sram_ctrl_alert_test.263272663 |
|
|
Aug 10 04:45:34 PM PDT 24 |
Aug 10 04:45:35 PM PDT 24 |
31427389 ps |
| T905 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.1196712558 |
|
|
Aug 10 04:45:25 PM PDT 24 |
Aug 10 04:45:27 PM PDT 24 |
78566592 ps |
| T906 |
/workspace/coverage/default/6.sram_ctrl_smoke.54158534 |
|
|
Aug 10 04:43:15 PM PDT 24 |
Aug 10 04:43:34 PM PDT 24 |
4358180555 ps |
| T907 |
/workspace/coverage/default/37.sram_ctrl_regwen.505932159 |
|
|
Aug 10 04:47:33 PM PDT 24 |
Aug 10 04:50:59 PM PDT 24 |
19674325070 ps |
| T908 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2133417484 |
|
|
Aug 10 04:43:24 PM PDT 24 |
Aug 10 04:43:33 PM PDT 24 |
955158035 ps |
| T909 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3419262955 |
|
|
Aug 10 04:43:17 PM PDT 24 |
Aug 10 04:43:22 PM PDT 24 |
200661995 ps |
| T910 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2989415891 |
|
|
Aug 10 04:43:52 PM PDT 24 |
Aug 10 04:43:56 PM PDT 24 |
415069250 ps |
| T911 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2132984942 |
|
|
Aug 10 04:44:44 PM PDT 24 |
Aug 10 04:44:48 PM PDT 24 |
1435774302 ps |
| T912 |
/workspace/coverage/default/31.sram_ctrl_stress_all.64216133 |
|
|
Aug 10 04:46:29 PM PDT 24 |
Aug 10 05:20:48 PM PDT 24 |
60359250641 ps |
| T30 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.370937334 |
|
|
Aug 10 04:43:10 PM PDT 24 |
Aug 10 04:43:14 PM PDT 24 |
752744374 ps |
| T913 |
/workspace/coverage/default/5.sram_ctrl_regwen.2002310459 |
|
|
Aug 10 04:43:14 PM PDT 24 |
Aug 10 05:01:01 PM PDT 24 |
26733836137 ps |
| T914 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2574708568 |
|
|
Aug 10 04:45:26 PM PDT 24 |
Aug 10 04:58:12 PM PDT 24 |
2126651039 ps |
| T915 |
/workspace/coverage/default/12.sram_ctrl_regwen.2241442915 |
|
|
Aug 10 04:43:35 PM PDT 24 |
Aug 10 04:59:39 PM PDT 24 |
85160008440 ps |
| T916 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.2213708958 |
|
|
Aug 10 04:44:00 PM PDT 24 |
Aug 10 04:44:01 PM PDT 24 |
53212240 ps |
| T917 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1111209001 |
|
|
Aug 10 04:48:47 PM PDT 24 |
Aug 10 04:48:48 PM PDT 24 |
29262821 ps |
| T918 |
/workspace/coverage/default/49.sram_ctrl_stress_all.2067589499 |
|
|
Aug 10 04:50:16 PM PDT 24 |
Aug 10 04:57:12 PM PDT 24 |
8590880619 ps |
| T919 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1548346225 |
|
|
Aug 10 04:44:27 PM PDT 24 |
Aug 10 04:46:14 PM PDT 24 |
449366858 ps |
| T920 |
/workspace/coverage/default/13.sram_ctrl_smoke.2340499513 |
|
|
Aug 10 04:43:38 PM PDT 24 |
Aug 10 04:43:53 PM PDT 24 |
213363825 ps |
| T921 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.359569520 |
|
|
Aug 10 04:47:52 PM PDT 24 |
Aug 10 04:51:51 PM PDT 24 |
9656561818 ps |
| T922 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.2655327801 |
|
|
Aug 10 04:43:10 PM PDT 24 |
Aug 10 04:45:47 PM PDT 24 |
3459039850 ps |
| T923 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.757657151 |
|
|
Aug 10 04:44:19 PM PDT 24 |
Aug 10 04:44:20 PM PDT 24 |
117423622 ps |
| T924 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3108431846 |
|
|
Aug 10 04:43:19 PM PDT 24 |
Aug 10 04:43:20 PM PDT 24 |
131313408 ps |
| T925 |
/workspace/coverage/default/19.sram_ctrl_regwen.1909323902 |
|
|
Aug 10 04:44:24 PM PDT 24 |
Aug 10 05:04:26 PM PDT 24 |
17821135833 ps |
| T926 |
/workspace/coverage/default/15.sram_ctrl_regwen.3580566422 |
|
|
Aug 10 04:44:00 PM PDT 24 |
Aug 10 04:52:31 PM PDT 24 |
1332300795 ps |
| T927 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3235554095 |
|
|
Aug 10 04:44:00 PM PDT 24 |
Aug 10 04:44:01 PM PDT 24 |
110829242 ps |
| T928 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3029641819 |
|
|
Aug 10 04:43:25 PM PDT 24 |
Aug 10 04:58:47 PM PDT 24 |
14857154461 ps |
| T66 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.132815618 |
|
|
Aug 10 04:40:43 PM PDT 24 |
Aug 10 04:40:45 PM PDT 24 |
2325877373 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3875168233 |
|
|
Aug 10 04:41:06 PM PDT 24 |
Aug 10 04:41:07 PM PDT 24 |
30536600 ps |
| T68 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.776785708 |
|
|
Aug 10 04:40:59 PM PDT 24 |
Aug 10 04:41:01 PM PDT 24 |
332136935 ps |
| T929 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1131824504 |
|
|
Aug 10 04:41:00 PM PDT 24 |
Aug 10 04:41:01 PM PDT 24 |
45403159 ps |
| T930 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1740253267 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:41:04 PM PDT 24 |
585085939 ps |
| T63 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3961456580 |
|
|
Aug 10 04:40:52 PM PDT 24 |
Aug 10 04:40:54 PM PDT 24 |
1000907056 ps |
| T931 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3096117076 |
|
|
Aug 10 04:41:14 PM PDT 24 |
Aug 10 04:41:15 PM PDT 24 |
12231046 ps |
| T73 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1760502976 |
|
|
Aug 10 04:40:59 PM PDT 24 |
Aug 10 04:40:59 PM PDT 24 |
162356837 ps |
| T101 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.749228236 |
|
|
Aug 10 04:40:41 PM PDT 24 |
Aug 10 04:40:42 PM PDT 24 |
16265254 ps |
| T74 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1336308886 |
|
|
Aug 10 04:40:43 PM PDT 24 |
Aug 10 04:40:47 PM PDT 24 |
3033975707 ps |
| T932 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1238769179 |
|
|
Aug 10 04:40:59 PM PDT 24 |
Aug 10 04:41:03 PM PDT 24 |
132241074 ps |
| T933 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2781898738 |
|
|
Aug 10 04:41:17 PM PDT 24 |
Aug 10 04:41:20 PM PDT 24 |
39195998 ps |
| T64 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3693086175 |
|
|
Aug 10 04:41:06 PM PDT 24 |
Aug 10 04:41:07 PM PDT 24 |
115787401 ps |
| T934 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.906272512 |
|
|
Aug 10 04:41:14 PM PDT 24 |
Aug 10 04:41:18 PM PDT 24 |
517633060 ps |
| T75 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2093442908 |
|
|
Aug 10 04:41:08 PM PDT 24 |
Aug 10 04:41:12 PM PDT 24 |
1827021953 ps |
| T76 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2624424206 |
|
|
Aug 10 04:41:10 PM PDT 24 |
Aug 10 04:41:11 PM PDT 24 |
27238419 ps |
| T77 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.156667772 |
|
|
Aug 10 04:40:44 PM PDT 24 |
Aug 10 04:40:45 PM PDT 24 |
12762880 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.874438608 |
|
|
Aug 10 04:40:39 PM PDT 24 |
Aug 10 04:40:40 PM PDT 24 |
58514692 ps |
| T935 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3602431159 |
|
|
Aug 10 04:41:06 PM PDT 24 |
Aug 10 04:41:08 PM PDT 24 |
38123082 ps |
| T79 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1593228623 |
|
|
Aug 10 04:40:39 PM PDT 24 |
Aug 10 04:40:41 PM PDT 24 |
73095418 ps |
| T936 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2710647336 |
|
|
Aug 10 04:41:06 PM PDT 24 |
Aug 10 04:41:08 PM PDT 24 |
52675380 ps |
| T937 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1942820013 |
|
|
Aug 10 04:40:45 PM PDT 24 |
Aug 10 04:40:47 PM PDT 24 |
806404310 ps |
| T65 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1945231920 |
|
|
Aug 10 04:40:39 PM PDT 24 |
Aug 10 04:40:41 PM PDT 24 |
329306273 ps |
| T938 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1447519654 |
|
|
Aug 10 04:40:43 PM PDT 24 |
Aug 10 04:40:44 PM PDT 24 |
25858578 ps |
| T115 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1559593415 |
|
|
Aug 10 04:41:07 PM PDT 24 |
Aug 10 04:41:09 PM PDT 24 |
355527053 ps |
| T939 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1643586270 |
|
|
Aug 10 04:41:00 PM PDT 24 |
Aug 10 04:41:01 PM PDT 24 |
28390785 ps |
| T940 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.798350545 |
|
|
Aug 10 04:40:47 PM PDT 24 |
Aug 10 04:40:48 PM PDT 24 |
145288461 ps |
| T80 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1290875418 |
|
|
Aug 10 04:41:14 PM PDT 24 |
Aug 10 04:41:16 PM PDT 24 |
2995342786 ps |
| T81 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2387735394 |
|
|
Aug 10 04:40:39 PM PDT 24 |
Aug 10 04:40:40 PM PDT 24 |
19676262 ps |
| T97 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1869453049 |
|
|
Aug 10 04:41:06 PM PDT 24 |
Aug 10 04:41:07 PM PDT 24 |
39252458 ps |
| T941 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3815317806 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:41:00 PM PDT 24 |
37347447 ps |
| T942 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2011116039 |
|
|
Aug 10 04:41:00 PM PDT 24 |
Aug 10 04:41:01 PM PDT 24 |
41547768 ps |
| T82 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.4217762300 |
|
|
Aug 10 04:41:16 PM PDT 24 |
Aug 10 04:41:20 PM PDT 24 |
441122808 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1116537393 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:40:58 PM PDT 24 |
48634656 ps |
| T944 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.233137388 |
|
|
Aug 10 04:41:26 PM PDT 24 |
Aug 10 04:41:29 PM PDT 24 |
1532227845 ps |
| T945 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.752820659 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:40:59 PM PDT 24 |
34379672 ps |
| T946 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1872681262 |
|
|
Aug 10 04:41:15 PM PDT 24 |
Aug 10 04:41:16 PM PDT 24 |
105907478 ps |
| T83 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1436625813 |
|
|
Aug 10 04:40:50 PM PDT 24 |
Aug 10 04:40:52 PM PDT 24 |
263577264 ps |
| T947 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2152225479 |
|
|
Aug 10 04:41:14 PM PDT 24 |
Aug 10 04:41:15 PM PDT 24 |
32375047 ps |
| T948 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1723979692 |
|
|
Aug 10 04:40:51 PM PDT 24 |
Aug 10 04:40:52 PM PDT 24 |
25195934 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1205813249 |
|
|
Aug 10 04:40:50 PM PDT 24 |
Aug 10 04:40:50 PM PDT 24 |
36117543 ps |
| T113 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1659374760 |
|
|
Aug 10 04:40:40 PM PDT 24 |
Aug 10 04:40:42 PM PDT 24 |
379287235 ps |
| T84 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4007714753 |
|
|
Aug 10 04:40:49 PM PDT 24 |
Aug 10 04:40:52 PM PDT 24 |
973530893 ps |
| T85 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2615544476 |
|
|
Aug 10 04:41:14 PM PDT 24 |
Aug 10 04:41:17 PM PDT 24 |
1433440061 ps |
| T86 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2698608118 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:41:00 PM PDT 24 |
247920215 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.12701610 |
|
|
Aug 10 04:40:47 PM PDT 24 |
Aug 10 04:40:48 PM PDT 24 |
22425543 ps |
| T951 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2071150443 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:40:59 PM PDT 24 |
26401971 ps |
| T116 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.558202739 |
|
|
Aug 10 04:40:50 PM PDT 24 |
Aug 10 04:40:52 PM PDT 24 |
372335489 ps |
| T952 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2918025126 |
|
|
Aug 10 04:40:50 PM PDT 24 |
Aug 10 04:40:52 PM PDT 24 |
62013402 ps |
| T953 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3848570019 |
|
|
Aug 10 04:41:06 PM PDT 24 |
Aug 10 04:41:07 PM PDT 24 |
108103553 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1740401464 |
|
|
Aug 10 04:40:46 PM PDT 24 |
Aug 10 04:40:47 PM PDT 24 |
17444732 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2949234466 |
|
|
Aug 10 04:41:14 PM PDT 24 |
Aug 10 04:41:15 PM PDT 24 |
50379504 ps |
| T956 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1983703623 |
|
|
Aug 10 04:40:43 PM PDT 24 |
Aug 10 04:40:46 PM PDT 24 |
1463209824 ps |
| T957 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3353477357 |
|
|
Aug 10 04:41:16 PM PDT 24 |
Aug 10 04:41:17 PM PDT 24 |
28899705 ps |
| T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2641220580 |
|
|
Aug 10 04:40:44 PM PDT 24 |
Aug 10 04:40:45 PM PDT 24 |
45360613 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1516908464 |
|
|
Aug 10 04:40:52 PM PDT 24 |
Aug 10 04:40:53 PM PDT 24 |
133478416 ps |
| T959 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.678803827 |
|
|
Aug 10 04:40:47 PM PDT 24 |
Aug 10 04:40:49 PM PDT 24 |
235869185 ps |
| T122 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.986727436 |
|
|
Aug 10 04:40:39 PM PDT 24 |
Aug 10 04:40:42 PM PDT 24 |
266730073 ps |
| T94 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.903393630 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:41:01 PM PDT 24 |
1619158731 ps |
| T960 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.474646429 |
|
|
Aug 10 04:41:08 PM PDT 24 |
Aug 10 04:41:09 PM PDT 24 |
14676889 ps |
| T961 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.133514260 |
|
|
Aug 10 04:40:59 PM PDT 24 |
Aug 10 04:41:04 PM PDT 24 |
584242449 ps |
| T962 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1145913763 |
|
|
Aug 10 04:40:48 PM PDT 24 |
Aug 10 04:40:51 PM PDT 24 |
713174724 ps |
| T963 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.482676149 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:41:00 PM PDT 24 |
36881114 ps |
| T114 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2765185857 |
|
|
Aug 10 04:40:57 PM PDT 24 |
Aug 10 04:41:00 PM PDT 24 |
154519271 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3249743884 |
|
|
Aug 10 04:40:40 PM PDT 24 |
Aug 10 04:40:42 PM PDT 24 |
231866591 ps |
| T965 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3478533112 |
|
|
Aug 10 04:41:05 PM PDT 24 |
Aug 10 04:41:06 PM PDT 24 |
63909350 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4265477624 |
|
|
Aug 10 04:41:02 PM PDT 24 |
Aug 10 04:41:04 PM PDT 24 |
160501534 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3905692153 |
|
|
Aug 10 04:40:48 PM PDT 24 |
Aug 10 04:40:52 PM PDT 24 |
857035720 ps |
| T117 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1167366262 |
|
|
Aug 10 04:40:47 PM PDT 24 |
Aug 10 04:40:49 PM PDT 24 |
572878387 ps |
| T968 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2820597106 |
|
|
Aug 10 04:41:25 PM PDT 24 |
Aug 10 04:41:26 PM PDT 24 |
22186499 ps |
| T118 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2581907453 |
|
|
Aug 10 04:40:59 PM PDT 24 |
Aug 10 04:41:01 PM PDT 24 |
300677300 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3529941675 |
|
|
Aug 10 04:40:49 PM PDT 24 |
Aug 10 04:40:50 PM PDT 24 |
56535706 ps |
| T95 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3119443815 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:41:00 PM PDT 24 |
1133455905 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1080832488 |
|
|
Aug 10 04:40:49 PM PDT 24 |
Aug 10 04:40:51 PM PDT 24 |
101340287 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.53792592 |
|
|
Aug 10 04:40:42 PM PDT 24 |
Aug 10 04:40:43 PM PDT 24 |
34653818 ps |
| T972 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1900592326 |
|
|
Aug 10 04:41:25 PM PDT 24 |
Aug 10 04:41:26 PM PDT 24 |
32723141 ps |
| T973 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.792752266 |
|
|
Aug 10 04:41:06 PM PDT 24 |
Aug 10 04:41:08 PM PDT 24 |
468380003 ps |
| T121 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3643223088 |
|
|
Aug 10 04:41:24 PM PDT 24 |
Aug 10 04:41:26 PM PDT 24 |
122006415 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3074983407 |
|
|
Aug 10 04:40:42 PM PDT 24 |
Aug 10 04:40:43 PM PDT 24 |
177043314 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2863058977 |
|
|
Aug 10 04:40:42 PM PDT 24 |
Aug 10 04:40:43 PM PDT 24 |
22241369 ps |
| T975 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1612183071 |
|
|
Aug 10 04:40:48 PM PDT 24 |
Aug 10 04:40:49 PM PDT 24 |
58940819 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1305450235 |
|
|
Aug 10 04:40:39 PM PDT 24 |
Aug 10 04:40:42 PM PDT 24 |
29566025 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3731731507 |
|
|
Aug 10 04:40:59 PM PDT 24 |
Aug 10 04:41:00 PM PDT 24 |
343266132 ps |
| T978 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.493010146 |
|
|
Aug 10 04:41:02 PM PDT 24 |
Aug 10 04:41:02 PM PDT 24 |
73946520 ps |
| T979 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3465191192 |
|
|
Aug 10 04:41:06 PM PDT 24 |
Aug 10 04:41:08 PM PDT 24 |
220783710 ps |
| T980 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1419501529 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:40:59 PM PDT 24 |
78024999 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3984459182 |
|
|
Aug 10 04:41:10 PM PDT 24 |
Aug 10 04:41:13 PM PDT 24 |
270092112 ps |
| T982 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2273104696 |
|
|
Aug 10 04:41:05 PM PDT 24 |
Aug 10 04:41:08 PM PDT 24 |
400157955 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2599372660 |
|
|
Aug 10 04:40:48 PM PDT 24 |
Aug 10 04:40:49 PM PDT 24 |
25497797 ps |
| T983 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2511775776 |
|
|
Aug 10 04:41:14 PM PDT 24 |
Aug 10 04:41:15 PM PDT 24 |
50045557 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.500258530 |
|
|
Aug 10 04:40:51 PM PDT 24 |
Aug 10 04:40:53 PM PDT 24 |
32011984 ps |
| T985 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2421600076 |
|
|
Aug 10 04:40:47 PM PDT 24 |
Aug 10 04:40:48 PM PDT 24 |
35443265 ps |
| T986 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4191444296 |
|
|
Aug 10 04:40:43 PM PDT 24 |
Aug 10 04:40:46 PM PDT 24 |
57488709 ps |
| T987 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3564111373 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:40:59 PM PDT 24 |
141761593 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2346168315 |
|
|
Aug 10 04:40:48 PM PDT 24 |
Aug 10 04:40:49 PM PDT 24 |
26123017 ps |
| T989 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.918522310 |
|
|
Aug 10 04:41:08 PM PDT 24 |
Aug 10 04:41:12 PM PDT 24 |
146177949 ps |
| T990 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1420544707 |
|
|
Aug 10 04:41:14 PM PDT 24 |
Aug 10 04:41:17 PM PDT 24 |
220552131 ps |
| T123 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3145411111 |
|
|
Aug 10 04:40:52 PM PDT 24 |
Aug 10 04:40:55 PM PDT 24 |
276232529 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3547665178 |
|
|
Aug 10 04:41:14 PM PDT 24 |
Aug 10 04:41:15 PM PDT 24 |
40254957 ps |
| T992 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1337786102 |
|
|
Aug 10 04:41:08 PM PDT 24 |
Aug 10 04:41:09 PM PDT 24 |
50284155 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.691438311 |
|
|
Aug 10 04:41:07 PM PDT 24 |
Aug 10 04:41:08 PM PDT 24 |
102022549 ps |
| T124 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1335754969 |
|
|
Aug 10 04:41:08 PM PDT 24 |
Aug 10 04:41:10 PM PDT 24 |
266380377 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1416844639 |
|
|
Aug 10 04:40:58 PM PDT 24 |
Aug 10 04:40:58 PM PDT 24 |
25140138 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1669385205 |
|
|
Aug 10 04:41:10 PM PDT 24 |
Aug 10 04:41:11 PM PDT 24 |
16393163 ps |
| T996 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.606006631 |
|
|
Aug 10 04:40:47 PM PDT 24 |
Aug 10 04:40:47 PM PDT 24 |
65572903 ps |
| T997 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4171199127 |
|
|
Aug 10 04:40:48 PM PDT 24 |
Aug 10 04:40:49 PM PDT 24 |
16756541 ps |
| T998 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.611669374 |
|
|
Aug 10 04:41:08 PM PDT 24 |
Aug 10 04:41:09 PM PDT 24 |
88266591 ps |
| T999 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2599723019 |
|
|
Aug 10 04:41:14 PM PDT 24 |
Aug 10 04:41:16 PM PDT 24 |
93907510 ps |
| T1000 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1029398727 |
|
|
Aug 10 04:41:07 PM PDT 24 |
Aug 10 04:41:08 PM PDT 24 |
94248963 ps |
| T1001 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2844310767 |
|
|
Aug 10 04:41:02 PM PDT 24 |
Aug 10 04:41:05 PM PDT 24 |
395078051 ps |
| T1002 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.260562934 |
|
|
Aug 10 04:40:59 PM PDT 24 |
Aug 10 04:41:00 PM PDT 24 |
16174354 ps |