Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	146108366	1			T1	251336		T3	10354		T4	1906
instr_valid_dis	112972422	1			T1	251336		T3	10354		T4	1906
instr_en	23469835	1			T26	202312		T20	651832		T75	312890

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10434966	1			T26	205460		T27	50530		T20	113324
sram_ifetch_valid_disable	113143876	1			T1	251336		T3	10354		T4	1906
sram_ifetch_enable	22529524	1			T26	167996		T27	42258		T20	330026

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	146108366	1			T1	251336		T3	10354		T4	1906
hw_debug_en_valid_off	113944621	1			T1	251336		T3	10354		T4	1906
hw_debug_en_on	21550541	1			T26	85048		T27	47036		T20	127828

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113143876	1			T1	251336		T3	10354		T4	1906
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99904172	1			T1	251336		T3	10354		T4	1906
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9550028	1			T26	95850		T20	208482		T75	181848
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4014102	1			T26	138120		T27	18896		T20	86506
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1784014	1			T26	119156		T29	6500		T137	64550
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1594092	1			T26	18964		T20	86506		T83	106992
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4213054	1			T26	6472		T27	31634		T20	14528
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1498504	1			T9	10566		T137	48334		T136	31528
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1966164	1			T26	6472		T20	14528		T75	56050
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7741469	1			T26	30950		T27	13430		T20	40134
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2955689	1			T26	10950		T9	22548		T137	74
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3927699	1			T26	20000		T20	40134		T75	56122

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9770297	1			T26	81026		T20	330026		T75	74992
lc_exec_en	9596018	1			T26	47626		T27	1972		T20	73166
valid_exec_dis	109578739	1			T1	251336		T3	10354		T4	1906
invalid_exec_dis	32964490	1			T26	373456		T27	92788		T20	443350