Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43722375	1			T1	114287		T3	5177		T4	51
triple_byte_access	2599804	1			T1	2306		T4	124		T6	15654
halfword_access	3898457	1			T1	3402		T4	217		T6	23594
byte_access	5205736	1			T1	4611		T4	372		T6	30952
zero_access	1309137	1			T1	1062		T4	189		T6	7840

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28313295

1

T1

62815

T3

2613

T4

350

auto[1]

28422214

1

T1

62853

T3

2564

T4

603

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21815256	1			T1	57080		T3	2613		T4	2
auto[0]	triple_byte_access	1295487	1			T1	1169		T4	14		T6	7856
auto[0]	halfword_access	1945425	1			T1	1734		T4	60		T6	11829
auto[0]	byte_access	2599446	1			T1	2292		T4	132		T6	15430
auto[0]	zero_access	657681	1			T1	540		T4	142		T6	3940
auto[1]	word_access	21907119	1			T1	57207		T3	2564		T4	49
auto[1]	triple_byte_access	1304317	1			T1	1137		T4	110		T6	7798
auto[1]	halfword_access	1953032	1			T1	1668		T4	157		T6	11765
auto[1]	byte_access	2606290	1			T1	2319		T4	240		T6	15522
auto[1]	zero_access	651456	1			T1	522		T4	47		T6	3900