| T789 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.3583944043 |
|
|
Aug 11 05:36:55 PM PDT 24 |
Aug 11 05:37:02 PM PDT 24 |
1243938764 ps |
| T790 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3344242650 |
|
|
Aug 11 05:36:42 PM PDT 24 |
Aug 11 05:36:47 PM PDT 24 |
1309714174 ps |
| T791 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1262679529 |
|
|
Aug 11 05:38:37 PM PDT 24 |
Aug 11 05:38:39 PM PDT 24 |
127338483 ps |
| T792 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.226886969 |
|
|
Aug 11 05:40:30 PM PDT 24 |
Aug 11 05:42:33 PM PDT 24 |
301592728 ps |
| T793 |
/workspace/coverage/default/0.sram_ctrl_regwen.1746448008 |
|
|
Aug 11 05:36:41 PM PDT 24 |
Aug 11 05:54:22 PM PDT 24 |
11913811890 ps |
| T794 |
/workspace/coverage/default/24.sram_ctrl_stress_all.733414252 |
|
|
Aug 11 05:38:37 PM PDT 24 |
Aug 11 05:56:17 PM PDT 24 |
52752554068 ps |
| T795 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3796912267 |
|
|
Aug 11 05:37:29 PM PDT 24 |
Aug 11 05:42:11 PM PDT 24 |
226816071053 ps |
| T796 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.836831006 |
|
|
Aug 11 05:40:10 PM PDT 24 |
Aug 11 05:40:16 PM PDT 24 |
474008298 ps |
| T797 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1083194993 |
|
|
Aug 11 05:41:15 PM PDT 24 |
Aug 11 05:56:47 PM PDT 24 |
32276802491 ps |
| T798 |
/workspace/coverage/default/8.sram_ctrl_executable.1070118116 |
|
|
Aug 11 05:37:19 PM PDT 24 |
Aug 11 05:48:19 PM PDT 24 |
23875174677 ps |
| T799 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.1222556539 |
|
|
Aug 11 05:41:22 PM PDT 24 |
Aug 11 05:41:30 PM PDT 24 |
492234231 ps |
| T800 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.970045884 |
|
|
Aug 11 05:40:42 PM PDT 24 |
Aug 11 05:43:45 PM PDT 24 |
2405428203 ps |
| T801 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.371085197 |
|
|
Aug 11 05:37:11 PM PDT 24 |
Aug 11 05:37:45 PM PDT 24 |
3850125960 ps |
| T802 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.995517782 |
|
|
Aug 11 05:40:50 PM PDT 24 |
Aug 11 05:41:29 PM PDT 24 |
355180318 ps |
| T803 |
/workspace/coverage/default/13.sram_ctrl_executable.4147505530 |
|
|
Aug 11 05:37:27 PM PDT 24 |
Aug 11 05:49:05 PM PDT 24 |
6627023365 ps |
| T804 |
/workspace/coverage/default/48.sram_ctrl_bijection.2087569215 |
|
|
Aug 11 05:42:57 PM PDT 24 |
Aug 11 05:43:54 PM PDT 24 |
4001960588 ps |
| T805 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.302994172 |
|
|
Aug 11 05:41:16 PM PDT 24 |
Aug 11 05:41:26 PM PDT 24 |
1048001306 ps |
| T806 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.2125613346 |
|
|
Aug 11 05:38:17 PM PDT 24 |
Aug 11 05:38:29 PM PDT 24 |
2647816075 ps |
| T807 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.818298507 |
|
|
Aug 11 05:37:27 PM PDT 24 |
Aug 11 05:37:36 PM PDT 24 |
445506658 ps |
| T808 |
/workspace/coverage/default/41.sram_ctrl_stress_all.1268702589 |
|
|
Aug 11 05:41:43 PM PDT 24 |
Aug 11 05:50:02 PM PDT 24 |
1707806514 ps |
| T809 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.4135866331 |
|
|
Aug 11 05:41:17 PM PDT 24 |
Aug 11 05:44:34 PM PDT 24 |
4742036677 ps |
| T810 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3614112801 |
|
|
Aug 11 05:42:01 PM PDT 24 |
Aug 11 05:42:04 PM PDT 24 |
43750603 ps |
| T811 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.3036082226 |
|
|
Aug 11 05:38:04 PM PDT 24 |
Aug 11 05:38:05 PM PDT 24 |
33485795 ps |
| T812 |
/workspace/coverage/default/34.sram_ctrl_bijection.1198885509 |
|
|
Aug 11 05:40:09 PM PDT 24 |
Aug 11 05:40:34 PM PDT 24 |
3104009871 ps |
| T813 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2185668754 |
|
|
Aug 11 05:43:06 PM PDT 24 |
Aug 11 05:43:11 PM PDT 24 |
329518619 ps |
| T814 |
/workspace/coverage/default/49.sram_ctrl_smoke.2896910942 |
|
|
Aug 11 05:43:08 PM PDT 24 |
Aug 11 05:43:16 PM PDT 24 |
82703911 ps |
| T815 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3569597660 |
|
|
Aug 11 05:37:27 PM PDT 24 |
Aug 11 05:44:52 PM PDT 24 |
7882293604 ps |
| T816 |
/workspace/coverage/default/1.sram_ctrl_bijection.728334110 |
|
|
Aug 11 05:36:44 PM PDT 24 |
Aug 11 05:37:14 PM PDT 24 |
1330367554 ps |
| T817 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2528253872 |
|
|
Aug 11 05:37:17 PM PDT 24 |
Aug 11 05:37:20 PM PDT 24 |
373872947 ps |
| T818 |
/workspace/coverage/default/35.sram_ctrl_bijection.3741506743 |
|
|
Aug 11 05:40:27 PM PDT 24 |
Aug 11 05:41:46 PM PDT 24 |
15068659663 ps |
| T819 |
/workspace/coverage/default/36.sram_ctrl_smoke.933135038 |
|
|
Aug 11 05:40:37 PM PDT 24 |
Aug 11 05:40:44 PM PDT 24 |
289017104 ps |
| T820 |
/workspace/coverage/default/46.sram_ctrl_regwen.3186917811 |
|
|
Aug 11 05:42:37 PM PDT 24 |
Aug 11 05:53:28 PM PDT 24 |
2474746104 ps |
| T821 |
/workspace/coverage/default/36.sram_ctrl_stress_all.407018951 |
|
|
Aug 11 05:40:41 PM PDT 24 |
Aug 11 06:09:37 PM PDT 24 |
51195765967 ps |
| T822 |
/workspace/coverage/default/22.sram_ctrl_regwen.1324538716 |
|
|
Aug 11 05:38:16 PM PDT 24 |
Aug 11 05:39:44 PM PDT 24 |
1932206669 ps |
| T823 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3563978375 |
|
|
Aug 11 05:42:19 PM PDT 24 |
Aug 11 05:42:25 PM PDT 24 |
345152304 ps |
| T824 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1463011894 |
|
|
Aug 11 05:38:02 PM PDT 24 |
Aug 11 05:38:12 PM PDT 24 |
265345706 ps |
| T825 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2002285899 |
|
|
Aug 11 05:41:35 PM PDT 24 |
Aug 11 06:02:24 PM PDT 24 |
11586607855 ps |
| T826 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.293395552 |
|
|
Aug 11 05:37:30 PM PDT 24 |
Aug 11 05:43:01 PM PDT 24 |
52449194136 ps |
| T827 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.994668341 |
|
|
Aug 11 05:37:36 PM PDT 24 |
Aug 11 05:47:10 PM PDT 24 |
6778787177 ps |
| T828 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1698075222 |
|
|
Aug 11 05:38:16 PM PDT 24 |
Aug 11 05:42:41 PM PDT 24 |
6609250880 ps |
| T829 |
/workspace/coverage/default/30.sram_ctrl_regwen.634807883 |
|
|
Aug 11 05:39:30 PM PDT 24 |
Aug 11 05:59:12 PM PDT 24 |
53133930370 ps |
| T830 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.25017920 |
|
|
Aug 11 05:40:23 PM PDT 24 |
Aug 11 06:04:31 PM PDT 24 |
5620555450 ps |
| T831 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.2285864379 |
|
|
Aug 11 05:36:44 PM PDT 24 |
Aug 11 05:36:51 PM PDT 24 |
1136494026 ps |
| T832 |
/workspace/coverage/default/23.sram_ctrl_regwen.1558458519 |
|
|
Aug 11 05:38:25 PM PDT 24 |
Aug 11 05:51:55 PM PDT 24 |
11937839339 ps |
| T833 |
/workspace/coverage/default/22.sram_ctrl_stress_all.1724750645 |
|
|
Aug 11 05:38:29 PM PDT 24 |
Aug 11 06:24:07 PM PDT 24 |
8951995611 ps |
| T834 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2861910251 |
|
|
Aug 11 05:36:59 PM PDT 24 |
Aug 11 06:18:21 PM PDT 24 |
35837759050 ps |
| T835 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.2619052607 |
|
|
Aug 11 05:38:45 PM PDT 24 |
Aug 11 05:38:57 PM PDT 24 |
672010809 ps |
| T836 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2127361575 |
|
|
Aug 11 05:43:06 PM PDT 24 |
Aug 11 05:46:29 PM PDT 24 |
8571826376 ps |
| T837 |
/workspace/coverage/default/25.sram_ctrl_partial_access.612532159 |
|
|
Aug 11 05:38:45 PM PDT 24 |
Aug 11 05:40:22 PM PDT 24 |
573449178 ps |
| T838 |
/workspace/coverage/default/19.sram_ctrl_alert_test.1240845483 |
|
|
Aug 11 05:38:05 PM PDT 24 |
Aug 11 05:38:06 PM PDT 24 |
13845719 ps |
| T839 |
/workspace/coverage/default/37.sram_ctrl_regwen.1533325838 |
|
|
Aug 11 05:40:55 PM PDT 24 |
Aug 11 05:47:55 PM PDT 24 |
6942392729 ps |
| T840 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3980756630 |
|
|
Aug 11 05:37:25 PM PDT 24 |
Aug 11 05:41:41 PM PDT 24 |
11496861834 ps |
| T841 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.2755324506 |
|
|
Aug 11 05:39:30 PM PDT 24 |
Aug 11 05:39:35 PM PDT 24 |
83625182 ps |
| T842 |
/workspace/coverage/default/22.sram_ctrl_smoke.1182915089 |
|
|
Aug 11 05:38:18 PM PDT 24 |
Aug 11 05:38:37 PM PDT 24 |
4141490768 ps |
| T843 |
/workspace/coverage/default/37.sram_ctrl_partial_access.993047488 |
|
|
Aug 11 05:40:50 PM PDT 24 |
Aug 11 05:41:01 PM PDT 24 |
1999036629 ps |
| T844 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3525428554 |
|
|
Aug 11 05:41:43 PM PDT 24 |
Aug 11 05:55:14 PM PDT 24 |
6797541179 ps |
| T845 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2766412928 |
|
|
Aug 11 05:38:51 PM PDT 24 |
Aug 11 05:42:57 PM PDT 24 |
9834439418 ps |
| T846 |
/workspace/coverage/default/10.sram_ctrl_regwen.2275283296 |
|
|
Aug 11 05:37:23 PM PDT 24 |
Aug 11 05:47:09 PM PDT 24 |
27835472196 ps |
| T847 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1019386923 |
|
|
Aug 11 05:37:19 PM PDT 24 |
Aug 11 05:37:28 PM PDT 24 |
952969791 ps |
| T848 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2973169976 |
|
|
Aug 11 05:42:25 PM PDT 24 |
Aug 11 05:49:45 PM PDT 24 |
24004257617 ps |
| T849 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4026684801 |
|
|
Aug 11 05:37:13 PM PDT 24 |
Aug 11 05:39:51 PM PDT 24 |
561865202 ps |
| T850 |
/workspace/coverage/default/3.sram_ctrl_stress_all.2511891037 |
|
|
Aug 11 05:36:55 PM PDT 24 |
Aug 11 06:28:37 PM PDT 24 |
45757818114 ps |
| T851 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1516894344 |
|
|
Aug 11 05:36:46 PM PDT 24 |
Aug 11 05:41:38 PM PDT 24 |
12266996084 ps |
| T852 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2994290859 |
|
|
Aug 11 05:40:02 PM PDT 24 |
Aug 11 05:43:30 PM PDT 24 |
2232436443 ps |
| T853 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2167368520 |
|
|
Aug 11 05:36:45 PM PDT 24 |
Aug 11 05:38:09 PM PDT 24 |
2122462531 ps |
| T854 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1833749491 |
|
|
Aug 11 05:36:48 PM PDT 24 |
Aug 11 05:37:08 PM PDT 24 |
323062832 ps |
| T855 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.2612484723 |
|
|
Aug 11 05:37:37 PM PDT 24 |
Aug 11 05:37:38 PM PDT 24 |
137999249 ps |
| T856 |
/workspace/coverage/default/27.sram_ctrl_alert_test.4050296195 |
|
|
Aug 11 05:39:04 PM PDT 24 |
Aug 11 05:39:05 PM PDT 24 |
15939549 ps |
| T857 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3019905271 |
|
|
Aug 11 05:37:27 PM PDT 24 |
Aug 11 05:40:59 PM PDT 24 |
2338120107 ps |
| T858 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.679757878 |
|
|
Aug 11 05:41:21 PM PDT 24 |
Aug 11 05:41:22 PM PDT 24 |
28087538 ps |
| T859 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.3269394622 |
|
|
Aug 11 05:38:05 PM PDT 24 |
Aug 11 05:38:09 PM PDT 24 |
270971526 ps |
| T860 |
/workspace/coverage/default/48.sram_ctrl_regwen.4050316976 |
|
|
Aug 11 05:43:05 PM PDT 24 |
Aug 11 05:45:35 PM PDT 24 |
3264809854 ps |
| T861 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.354716855 |
|
|
Aug 11 05:39:44 PM PDT 24 |
Aug 11 05:39:50 PM PDT 24 |
1390136903 ps |
| T862 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2087268634 |
|
|
Aug 11 05:41:11 PM PDT 24 |
Aug 11 05:51:44 PM PDT 24 |
5770780089 ps |
| T863 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.359486648 |
|
|
Aug 11 05:36:44 PM PDT 24 |
Aug 11 05:36:45 PM PDT 24 |
169066165 ps |
| T864 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1505468187 |
|
|
Aug 11 05:37:24 PM PDT 24 |
Aug 11 06:33:57 PM PDT 24 |
221607283452 ps |
| T865 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.1890655771 |
|
|
Aug 11 05:37:56 PM PDT 24 |
Aug 11 05:44:48 PM PDT 24 |
1335969230 ps |
| T866 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3579018612 |
|
|
Aug 11 05:37:04 PM PDT 24 |
Aug 11 05:37:09 PM PDT 24 |
246554609 ps |
| T867 |
/workspace/coverage/default/14.sram_ctrl_alert_test.408324537 |
|
|
Aug 11 05:37:30 PM PDT 24 |
Aug 11 05:37:31 PM PDT 24 |
25304137 ps |
| T868 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.984401480 |
|
|
Aug 11 05:37:03 PM PDT 24 |
Aug 11 05:37:29 PM PDT 24 |
99998688 ps |
| T869 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.651428526 |
|
|
Aug 11 05:41:28 PM PDT 24 |
Aug 11 05:41:34 PM PDT 24 |
450290093 ps |
| T870 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.2261489504 |
|
|
Aug 11 05:37:29 PM PDT 24 |
Aug 11 05:37:40 PM PDT 24 |
1844491485 ps |
| T871 |
/workspace/coverage/default/4.sram_ctrl_smoke.1292280332 |
|
|
Aug 11 05:36:50 PM PDT 24 |
Aug 11 05:37:03 PM PDT 24 |
867347469 ps |
| T872 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.100841160 |
|
|
Aug 11 05:36:59 PM PDT 24 |
Aug 11 05:40:43 PM PDT 24 |
12914079916 ps |
| T873 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1308232763 |
|
|
Aug 11 05:42:34 PM PDT 24 |
Aug 11 05:42:37 PM PDT 24 |
104758689 ps |
| T874 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1177617845 |
|
|
Aug 11 05:38:17 PM PDT 24 |
Aug 11 05:40:11 PM PDT 24 |
1363920052 ps |
| T875 |
/workspace/coverage/default/25.sram_ctrl_alert_test.2411993876 |
|
|
Aug 11 05:38:50 PM PDT 24 |
Aug 11 05:38:51 PM PDT 24 |
22334525 ps |
| T876 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2111273565 |
|
|
Aug 11 05:38:19 PM PDT 24 |
Aug 11 05:40:12 PM PDT 24 |
279311048 ps |
| T877 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.595457223 |
|
|
Aug 11 05:40:50 PM PDT 24 |
Aug 11 05:41:31 PM PDT 24 |
124510585 ps |
| T878 |
/workspace/coverage/default/12.sram_ctrl_alert_test.2180627704 |
|
|
Aug 11 05:37:25 PM PDT 24 |
Aug 11 05:37:26 PM PDT 24 |
39756396 ps |
| T879 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1258683507 |
|
|
Aug 11 05:39:36 PM PDT 24 |
Aug 11 05:39:39 PM PDT 24 |
104713224 ps |
| T880 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.1537044201 |
|
|
Aug 11 05:38:45 PM PDT 24 |
Aug 11 05:53:05 PM PDT 24 |
3461296715 ps |
| T881 |
/workspace/coverage/default/40.sram_ctrl_alert_test.4233035101 |
|
|
Aug 11 05:41:35 PM PDT 24 |
Aug 11 05:41:35 PM PDT 24 |
12457087 ps |
| T882 |
/workspace/coverage/default/23.sram_ctrl_bijection.1863201264 |
|
|
Aug 11 05:38:26 PM PDT 24 |
Aug 11 05:38:42 PM PDT 24 |
2034038867 ps |
| T883 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.290353744 |
|
|
Aug 11 05:37:26 PM PDT 24 |
Aug 11 06:04:58 PM PDT 24 |
3450348976 ps |
| T884 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3801917798 |
|
|
Aug 11 05:36:52 PM PDT 24 |
Aug 11 05:39:35 PM PDT 24 |
8491750857 ps |
| T885 |
/workspace/coverage/default/21.sram_ctrl_partial_access.2884725964 |
|
|
Aug 11 05:38:11 PM PDT 24 |
Aug 11 05:38:18 PM PDT 24 |
1273455507 ps |
| T886 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3202538902 |
|
|
Aug 11 05:38:25 PM PDT 24 |
Aug 11 05:38:30 PM PDT 24 |
1832961718 ps |
| T887 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.445283148 |
|
|
Aug 11 05:37:45 PM PDT 24 |
Aug 11 06:06:46 PM PDT 24 |
15102756142 ps |
| T888 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.953336483 |
|
|
Aug 11 05:38:44 PM PDT 24 |
Aug 11 05:38:49 PM PDT 24 |
266309715 ps |
| T889 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3591180908 |
|
|
Aug 11 05:37:04 PM PDT 24 |
Aug 11 05:37:43 PM PDT 24 |
95287640 ps |
| T890 |
/workspace/coverage/default/47.sram_ctrl_executable.1765387564 |
|
|
Aug 11 05:42:52 PM PDT 24 |
Aug 11 05:56:07 PM PDT 24 |
6986890963 ps |
| T891 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.952443838 |
|
|
Aug 11 05:41:50 PM PDT 24 |
Aug 11 05:43:36 PM PDT 24 |
133959633 ps |
| T892 |
/workspace/coverage/default/31.sram_ctrl_regwen.1082681074 |
|
|
Aug 11 05:39:42 PM PDT 24 |
Aug 11 05:56:57 PM PDT 24 |
2803077060 ps |
| T893 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2708804600 |
|
|
Aug 11 05:40:10 PM PDT 24 |
Aug 11 05:47:36 PM PDT 24 |
16518218687 ps |
| T894 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2513536966 |
|
|
Aug 11 05:43:01 PM PDT 24 |
Aug 11 05:49:09 PM PDT 24 |
29893015764 ps |
| T895 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.4230136157 |
|
|
Aug 11 05:42:49 PM PDT 24 |
Aug 11 06:04:54 PM PDT 24 |
54001869635 ps |
| T896 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3719823385 |
|
|
Aug 11 05:37:42 PM PDT 24 |
Aug 11 05:43:04 PM PDT 24 |
3317678252 ps |
| T897 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3530630674 |
|
|
Aug 11 05:40:39 PM PDT 24 |
Aug 11 05:45:14 PM PDT 24 |
13987450234 ps |
| T898 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.737190056 |
|
|
Aug 11 05:39:37 PM PDT 24 |
Aug 11 05:43:26 PM PDT 24 |
9409404997 ps |
| T35 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3279830417 |
|
|
Aug 11 05:37:04 PM PDT 24 |
Aug 11 05:37:06 PM PDT 24 |
484271165 ps |
| T899 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2201874414 |
|
|
Aug 11 05:42:30 PM PDT 24 |
Aug 11 05:42:30 PM PDT 24 |
14078836 ps |
| T900 |
/workspace/coverage/default/31.sram_ctrl_smoke.3004994114 |
|
|
Aug 11 05:39:36 PM PDT 24 |
Aug 11 05:40:51 PM PDT 24 |
241481027 ps |
| T901 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.724902750 |
|
|
Aug 11 05:37:08 PM PDT 24 |
Aug 11 05:45:55 PM PDT 24 |
2918605171 ps |
| T902 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.804878002 |
|
|
Aug 11 05:38:11 PM PDT 24 |
Aug 11 05:38:14 PM PDT 24 |
195379220 ps |
| T903 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1100285213 |
|
|
Aug 11 05:43:07 PM PDT 24 |
Aug 11 05:52:44 PM PDT 24 |
51580349668 ps |
| T904 |
/workspace/coverage/default/45.sram_ctrl_executable.2176849493 |
|
|
Aug 11 05:42:34 PM PDT 24 |
Aug 11 05:54:58 PM PDT 24 |
3693131604 ps |
| T905 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.2511050115 |
|
|
Aug 11 05:40:58 PM PDT 24 |
Aug 11 06:00:15 PM PDT 24 |
3050760700 ps |
| T906 |
/workspace/coverage/default/2.sram_ctrl_regwen.3430418501 |
|
|
Aug 11 05:36:50 PM PDT 24 |
Aug 11 05:45:27 PM PDT 24 |
10117453768 ps |
| T907 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2998764007 |
|
|
Aug 11 05:37:25 PM PDT 24 |
Aug 11 05:37:26 PM PDT 24 |
248315391 ps |
| T908 |
/workspace/coverage/default/34.sram_ctrl_stress_all.876793607 |
|
|
Aug 11 05:40:22 PM PDT 24 |
Aug 11 05:43:58 PM PDT 24 |
5827431821 ps |
| T909 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2290484883 |
|
|
Aug 11 05:37:25 PM PDT 24 |
Aug 11 05:38:09 PM PDT 24 |
435550548 ps |
| T910 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.318785311 |
|
|
Aug 11 05:38:46 PM PDT 24 |
Aug 11 05:41:45 PM PDT 24 |
3675192144 ps |
| T36 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.352009246 |
|
|
Aug 11 05:36:51 PM PDT 24 |
Aug 11 05:36:54 PM PDT 24 |
470943224 ps |
| T911 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3097711570 |
|
|
Aug 11 05:36:52 PM PDT 24 |
Aug 11 05:36:56 PM PDT 24 |
56915925 ps |
| T912 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2072111352 |
|
|
Aug 11 05:41:10 PM PDT 24 |
Aug 11 05:41:13 PM PDT 24 |
184398799 ps |
| T913 |
/workspace/coverage/default/28.sram_ctrl_stress_all.1614617970 |
|
|
Aug 11 05:39:18 PM PDT 24 |
Aug 11 06:31:32 PM PDT 24 |
8729636183 ps |
| T914 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2497647769 |
|
|
Aug 11 05:37:04 PM PDT 24 |
Aug 11 05:37:10 PM PDT 24 |
413802871 ps |
| T915 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2798557493 |
|
|
Aug 11 05:37:11 PM PDT 24 |
Aug 11 05:37:15 PM PDT 24 |
53021318 ps |
| T916 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1881648476 |
|
|
Aug 11 05:39:34 PM PDT 24 |
Aug 11 05:44:31 PM PDT 24 |
15958432377 ps |
| T917 |
/workspace/coverage/default/10.sram_ctrl_executable.4069992017 |
|
|
Aug 11 05:37:17 PM PDT 24 |
Aug 11 05:42:17 PM PDT 24 |
20889008408 ps |
| T918 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1838233574 |
|
|
Aug 11 05:37:30 PM PDT 24 |
Aug 11 06:42:24 PM PDT 24 |
63852589464 ps |
| T919 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.4015434473 |
|
|
Aug 11 05:41:30 PM PDT 24 |
Aug 11 05:41:31 PM PDT 24 |
72716086 ps |
| T920 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3131680548 |
|
|
Aug 11 05:37:56 PM PDT 24 |
Aug 11 05:37:57 PM PDT 24 |
76222878 ps |
| T921 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1698926048 |
|
|
Aug 11 05:40:27 PM PDT 24 |
Aug 11 05:40:28 PM PDT 24 |
135311249 ps |
| T922 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2874738412 |
|
|
Aug 11 05:39:42 PM PDT 24 |
Aug 11 05:40:55 PM PDT 24 |
18591530302 ps |
| T923 |
/workspace/coverage/default/28.sram_ctrl_smoke.1178216934 |
|
|
Aug 11 05:39:11 PM PDT 24 |
Aug 11 05:39:22 PM PDT 24 |
217207374 ps |
| T924 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.872474746 |
|
|
Aug 11 05:43:06 PM PDT 24 |
Aug 11 05:43:13 PM PDT 24 |
2633486081 ps |
| T925 |
/workspace/coverage/default/5.sram_ctrl_bijection.91092525 |
|
|
Aug 11 05:36:59 PM PDT 24 |
Aug 11 05:38:24 PM PDT 24 |
35546363832 ps |
| T926 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.356074134 |
|
|
Aug 11 05:41:34 PM PDT 24 |
Aug 11 05:41:50 PM PDT 24 |
689248855 ps |
| T927 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.877131714 |
|
|
Aug 11 05:39:36 PM PDT 24 |
Aug 11 05:39:51 PM PDT 24 |
1265342398 ps |
| T928 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.2831525030 |
|
|
Aug 11 05:43:21 PM PDT 24 |
Aug 11 05:43:28 PM PDT 24 |
679165758 ps |
| T929 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.1693543516 |
|
|
Aug 11 05:38:03 PM PDT 24 |
Aug 11 05:44:12 PM PDT 24 |
3622058253 ps |
| T930 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4157694892 |
|
|
Aug 11 05:37:28 PM PDT 24 |
Aug 11 05:37:42 PM PDT 24 |
3288720242 ps |
| T931 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.1994969781 |
|
|
Aug 11 05:40:09 PM PDT 24 |
Aug 11 05:40:10 PM PDT 24 |
43516359 ps |
| T932 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3275261016 |
|
|
Aug 11 05:41:50 PM PDT 24 |
Aug 11 05:48:26 PM PDT 24 |
54544344913 ps |
| T933 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1387584058 |
|
|
Aug 11 05:39:55 PM PDT 24 |
Aug 11 06:12:56 PM PDT 24 |
7268102958 ps |
| T66 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3365329950 |
|
|
Aug 11 05:25:17 PM PDT 24 |
Aug 11 05:25:19 PM PDT 24 |
234339425 ps |
| T67 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.239357685 |
|
|
Aug 11 05:25:14 PM PDT 24 |
Aug 11 05:25:17 PM PDT 24 |
1126155082 ps |
| T68 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3640880172 |
|
|
Aug 11 05:24:49 PM PDT 24 |
Aug 11 05:24:52 PM PDT 24 |
634195047 ps |
| T108 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1598627350 |
|
|
Aug 11 05:24:49 PM PDT 24 |
Aug 11 05:24:50 PM PDT 24 |
27198613 ps |
| T934 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.482878488 |
|
|
Aug 11 05:24:47 PM PDT 24 |
Aug 11 05:24:51 PM PDT 24 |
194246740 ps |
| T935 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2884412485 |
|
|
Aug 11 05:25:25 PM PDT 24 |
Aug 11 05:25:29 PM PDT 24 |
46334516 ps |
| T936 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2850097123 |
|
|
Aug 11 05:24:56 PM PDT 24 |
Aug 11 05:24:58 PM PDT 24 |
85289883 ps |
| T84 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.570250696 |
|
|
Aug 11 05:24:57 PM PDT 24 |
Aug 11 05:24:59 PM PDT 24 |
1730092162 ps |
| T61 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1932157020 |
|
|
Aug 11 05:25:12 PM PDT 24 |
Aug 11 05:25:14 PM PDT 24 |
163558361 ps |
| T937 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1808843764 |
|
|
Aug 11 05:25:11 PM PDT 24 |
Aug 11 05:25:13 PM PDT 24 |
63508466 ps |
| T62 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2392177441 |
|
|
Aug 11 05:25:00 PM PDT 24 |
Aug 11 05:25:03 PM PDT 24 |
173431231 ps |
| T85 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2586256044 |
|
|
Aug 11 05:25:16 PM PDT 24 |
Aug 11 05:25:17 PM PDT 24 |
15068689 ps |
| T63 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3065536265 |
|
|
Aug 11 05:25:23 PM PDT 24 |
Aug 11 05:25:26 PM PDT 24 |
482708506 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1249341547 |
|
|
Aug 11 05:24:35 PM PDT 24 |
Aug 11 05:24:37 PM PDT 24 |
176810875 ps |
| T86 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.418025254 |
|
|
Aug 11 05:25:23 PM PDT 24 |
Aug 11 05:25:24 PM PDT 24 |
16928002 ps |
| T87 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.8079896 |
|
|
Aug 11 05:25:24 PM PDT 24 |
Aug 11 05:25:26 PM PDT 24 |
207765787 ps |
| T938 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1755868808 |
|
|
Aug 11 05:25:02 PM PDT 24 |
Aug 11 05:25:03 PM PDT 24 |
68458922 ps |
| T123 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2593303704 |
|
|
Aug 11 05:24:40 PM PDT 24 |
Aug 11 05:24:43 PM PDT 24 |
1146495670 ps |
| T125 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1202613169 |
|
|
Aug 11 05:25:01 PM PDT 24 |
Aug 11 05:25:03 PM PDT 24 |
381227991 ps |
| T88 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2768893674 |
|
|
Aug 11 05:24:53 PM PDT 24 |
Aug 11 05:24:57 PM PDT 24 |
989560952 ps |
| T939 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4064838822 |
|
|
Aug 11 05:25:19 PM PDT 24 |
Aug 11 05:25:20 PM PDT 24 |
59770073 ps |
| T940 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4159332374 |
|
|
Aug 11 05:25:12 PM PDT 24 |
Aug 11 05:25:14 PM PDT 24 |
32374324 ps |
| T941 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2660078877 |
|
|
Aug 11 05:24:53 PM PDT 24 |
Aug 11 05:24:56 PM PDT 24 |
74081963 ps |
| T942 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1115108415 |
|
|
Aug 11 05:24:40 PM PDT 24 |
Aug 11 05:24:41 PM PDT 24 |
70803530 ps |
| T943 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2844820437 |
|
|
Aug 11 05:24:47 PM PDT 24 |
Aug 11 05:24:48 PM PDT 24 |
22144814 ps |
| T89 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1098332973 |
|
|
Aug 11 05:25:15 PM PDT 24 |
Aug 11 05:25:16 PM PDT 24 |
27063067 ps |
| T90 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3474460791 |
|
|
Aug 11 05:25:17 PM PDT 24 |
Aug 11 05:25:18 PM PDT 24 |
29674850 ps |
| T91 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3804270892 |
|
|
Aug 11 05:24:57 PM PDT 24 |
Aug 11 05:24:59 PM PDT 24 |
277404108 ps |
| T944 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4176856532 |
|
|
Aug 11 05:24:40 PM PDT 24 |
Aug 11 05:24:42 PM PDT 24 |
138841358 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3992487593 |
|
|
Aug 11 05:24:41 PM PDT 24 |
Aug 11 05:24:42 PM PDT 24 |
21321682 ps |
| T93 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3547943635 |
|
|
Aug 11 05:24:50 PM PDT 24 |
Aug 11 05:24:51 PM PDT 24 |
38711876 ps |
| T946 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1667148350 |
|
|
Aug 11 05:25:18 PM PDT 24 |
Aug 11 05:25:19 PM PDT 24 |
49435440 ps |
| T94 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.170967590 |
|
|
Aug 11 05:24:46 PM PDT 24 |
Aug 11 05:24:47 PM PDT 24 |
102989377 ps |
| T105 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3322660441 |
|
|
Aug 11 05:25:17 PM PDT 24 |
Aug 11 05:25:18 PM PDT 24 |
136755570 ps |
| T947 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3791904747 |
|
|
Aug 11 05:24:49 PM PDT 24 |
Aug 11 05:24:50 PM PDT 24 |
43612482 ps |
| T948 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3945255367 |
|
|
Aug 11 05:24:36 PM PDT 24 |
Aug 11 05:24:37 PM PDT 24 |
14946720 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1243371117 |
|
|
Aug 11 05:24:44 PM PDT 24 |
Aug 11 05:24:46 PM PDT 24 |
284165092 ps |
| T101 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4033266688 |
|
|
Aug 11 05:25:19 PM PDT 24 |
Aug 11 05:25:21 PM PDT 24 |
407188717 ps |
| T949 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.180639215 |
|
|
Aug 11 05:24:44 PM PDT 24 |
Aug 11 05:24:45 PM PDT 24 |
202409263 ps |
| T131 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2089346854 |
|
|
Aug 11 05:24:53 PM PDT 24 |
Aug 11 05:24:54 PM PDT 24 |
163946398 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2570576055 |
|
|
Aug 11 05:24:36 PM PDT 24 |
Aug 11 05:24:39 PM PDT 24 |
4770145165 ps |
| T950 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.621852382 |
|
|
Aug 11 05:25:14 PM PDT 24 |
Aug 11 05:25:15 PM PDT 24 |
15808048 ps |
| T100 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2638454692 |
|
|
Aug 11 05:25:00 PM PDT 24 |
Aug 11 05:25:07 PM PDT 24 |
1573402611 ps |
| T951 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3118711649 |
|
|
Aug 11 05:24:54 PM PDT 24 |
Aug 11 05:24:55 PM PDT 24 |
36849752 ps |
| T103 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4145904691 |
|
|
Aug 11 05:25:16 PM PDT 24 |
Aug 11 05:25:20 PM PDT 24 |
1313882363 ps |
| T952 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2341151820 |
|
|
Aug 11 05:24:53 PM PDT 24 |
Aug 11 05:24:54 PM PDT 24 |
147762053 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2052914093 |
|
|
Aug 11 05:24:44 PM PDT 24 |
Aug 11 05:24:46 PM PDT 24 |
186120348 ps |
| T954 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3029908286 |
|
|
Aug 11 05:25:13 PM PDT 24 |
Aug 11 05:25:16 PM PDT 24 |
130985464 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2547495626 |
|
|
Aug 11 05:25:22 PM PDT 24 |
Aug 11 05:25:24 PM PDT 24 |
76078342 ps |
| T132 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2678891591 |
|
|
Aug 11 05:25:03 PM PDT 24 |
Aug 11 05:25:06 PM PDT 24 |
1186828830 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3522738277 |
|
|
Aug 11 05:24:50 PM PDT 24 |
Aug 11 05:24:51 PM PDT 24 |
53085124 ps |
| T128 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2993615508 |
|
|
Aug 11 05:24:38 PM PDT 24 |
Aug 11 05:24:40 PM PDT 24 |
388914823 ps |
| T957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2987036209 |
|
|
Aug 11 05:25:21 PM PDT 24 |
Aug 11 05:25:21 PM PDT 24 |
18248690 ps |
| T958 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3306891518 |
|
|
Aug 11 05:25:12 PM PDT 24 |
Aug 11 05:25:13 PM PDT 24 |
15937717 ps |
| T959 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3055497604 |
|
|
Aug 11 05:25:13 PM PDT 24 |
Aug 11 05:25:16 PM PDT 24 |
77497891 ps |
| T126 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1177204621 |
|
|
Aug 11 05:24:57 PM PDT 24 |
Aug 11 05:24:59 PM PDT 24 |
964454800 ps |
| T960 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2463701642 |
|
|
Aug 11 05:25:16 PM PDT 24 |
Aug 11 05:25:19 PM PDT 24 |
71038152 ps |
| T961 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1100451461 |
|
|
Aug 11 05:25:13 PM PDT 24 |
Aug 11 05:25:19 PM PDT 24 |
830555759 ps |
| T962 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1265264046 |
|
|
Aug 11 05:25:17 PM PDT 24 |
Aug 11 05:25:17 PM PDT 24 |
38233973 ps |
| T963 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2627215449 |
|
|
Aug 11 05:24:57 PM PDT 24 |
Aug 11 05:24:58 PM PDT 24 |
39242328 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1586612883 |
|
|
Aug 11 05:24:35 PM PDT 24 |
Aug 11 05:24:36 PM PDT 24 |
19445261 ps |
| T965 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2254593244 |
|
|
Aug 11 05:25:15 PM PDT 24 |
Aug 11 05:25:18 PM PDT 24 |
82081442 ps |
| T966 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.829286650 |
|
|
Aug 11 05:25:15 PM PDT 24 |
Aug 11 05:25:16 PM PDT 24 |
127298290 ps |
| T127 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4144812954 |
|
|
Aug 11 05:25:17 PM PDT 24 |
Aug 11 05:25:20 PM PDT 24 |
1927734437 ps |
| T967 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2935714327 |
|
|
Aug 11 05:25:18 PM PDT 24 |
Aug 11 05:25:18 PM PDT 24 |
19608621 ps |
| T968 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1244846078 |
|
|
Aug 11 05:25:18 PM PDT 24 |
Aug 11 05:25:22 PM PDT 24 |
1563600096 ps |
| T129 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.369377022 |
|
|
Aug 11 05:24:49 PM PDT 24 |
Aug 11 05:24:51 PM PDT 24 |
336634226 ps |
| T969 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.320102929 |
|
|
Aug 11 05:24:43 PM PDT 24 |
Aug 11 05:24:44 PM PDT 24 |
17077731 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1277998911 |
|
|
Aug 11 05:24:48 PM PDT 24 |
Aug 11 05:24:49 PM PDT 24 |
154026389 ps |
| T971 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.514773186 |
|
|
Aug 11 05:25:19 PM PDT 24 |
Aug 11 05:25:23 PM PDT 24 |
84365947 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.525880758 |
|
|
Aug 11 05:24:43 PM PDT 24 |
Aug 11 05:24:44 PM PDT 24 |
288480080 ps |
| T104 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1903001400 |
|
|
Aug 11 05:25:01 PM PDT 24 |
Aug 11 05:25:03 PM PDT 24 |
817916988 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.319040324 |
|
|
Aug 11 05:24:48 PM PDT 24 |
Aug 11 05:24:50 PM PDT 24 |
277439013 ps |
| T974 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2631577733 |
|
|
Aug 11 05:24:47 PM PDT 24 |
Aug 11 05:24:49 PM PDT 24 |
143864724 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2390593355 |
|
|
Aug 11 05:25:27 PM PDT 24 |
Aug 11 05:25:31 PM PDT 24 |
41493805 ps |
| T976 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3541201841 |
|
|
Aug 11 05:25:19 PM PDT 24 |
Aug 11 05:25:20 PM PDT 24 |
13835921 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4148149614 |
|
|
Aug 11 05:24:34 PM PDT 24 |
Aug 11 05:24:35 PM PDT 24 |
78178737 ps |
| T978 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3821551156 |
|
|
Aug 11 05:25:16 PM PDT 24 |
Aug 11 05:25:17 PM PDT 24 |
33573438 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3676077545 |
|
|
Aug 11 05:24:56 PM PDT 24 |
Aug 11 05:24:57 PM PDT 24 |
30921130 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3849394289 |
|
|
Aug 11 05:24:49 PM PDT 24 |
Aug 11 05:24:54 PM PDT 24 |
4386978095 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3696360618 |
|
|
Aug 11 05:25:11 PM PDT 24 |
Aug 11 05:25:12 PM PDT 24 |
14532468 ps |
| T982 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4112701725 |
|
|
Aug 11 05:24:59 PM PDT 24 |
Aug 11 05:25:00 PM PDT 24 |
57969862 ps |
| T124 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.961134515 |
|
|
Aug 11 05:25:19 PM PDT 24 |
Aug 11 05:25:22 PM PDT 24 |
1141915285 ps |
| T983 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3253372889 |
|
|
Aug 11 05:25:01 PM PDT 24 |
Aug 11 05:25:02 PM PDT 24 |
38580979 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.596179412 |
|
|
Aug 11 05:24:47 PM PDT 24 |
Aug 11 05:24:47 PM PDT 24 |
42188525 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1062827259 |
|
|
Aug 11 05:24:43 PM PDT 24 |
Aug 11 05:24:44 PM PDT 24 |
13686909 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3493681015 |
|
|
Aug 11 05:24:55 PM PDT 24 |
Aug 11 05:24:56 PM PDT 24 |
16041751 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.440056028 |
|
|
Aug 11 05:25:16 PM PDT 24 |
Aug 11 05:25:16 PM PDT 24 |
76469191 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4241168483 |
|
|
Aug 11 05:24:47 PM PDT 24 |
Aug 11 05:24:49 PM PDT 24 |
253243175 ps |
| T989 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2276857918 |
|
|
Aug 11 05:24:56 PM PDT 24 |
Aug 11 05:25:00 PM PDT 24 |
469383037 ps |
| T98 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3222725498 |
|
|
Aug 11 05:24:34 PM PDT 24 |
Aug 11 05:24:35 PM PDT 24 |
19461573 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2597295518 |
|
|
Aug 11 05:24:43 PM PDT 24 |
Aug 11 05:24:45 PM PDT 24 |
80936339 ps |
| T991 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1960902386 |
|
|
Aug 11 05:24:56 PM PDT 24 |
Aug 11 05:24:57 PM PDT 24 |
25804919 ps |
| T992 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.711254646 |
|
|
Aug 11 05:25:16 PM PDT 24 |
Aug 11 05:25:17 PM PDT 24 |
74207832 ps |
| T993 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3264844291 |
|
|
Aug 11 05:25:00 PM PDT 24 |
Aug 11 05:25:01 PM PDT 24 |
13528096 ps |
| T994 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.496944682 |
|
|
Aug 11 05:24:40 PM PDT 24 |
Aug 11 05:24:43 PM PDT 24 |
240179766 ps |
| T995 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1613072370 |
|
|
Aug 11 05:25:24 PM PDT 24 |
Aug 11 05:25:25 PM PDT 24 |
45747940 ps |
| T996 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1084006941 |
|
|
Aug 11 05:25:18 PM PDT 24 |
Aug 11 05:25:20 PM PDT 24 |
933828572 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1655572478 |
|
|
Aug 11 05:24:40 PM PDT 24 |
Aug 11 05:24:42 PM PDT 24 |
158222560 ps |
| T998 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.321078427 |
|
|
Aug 11 05:25:02 PM PDT 24 |
Aug 11 05:25:05 PM PDT 24 |
34150693 ps |
| T130 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2515873936 |
|
|
Aug 11 05:25:15 PM PDT 24 |
Aug 11 05:25:17 PM PDT 24 |
470187315 ps |
| T999 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1216243973 |
|
|
Aug 11 05:25:18 PM PDT 24 |
Aug 11 05:25:18 PM PDT 24 |
13469635 ps |
| T1000 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.888508935 |
|
|
Aug 11 05:25:19 PM PDT 24 |
Aug 11 05:25:19 PM PDT 24 |
16196001 ps |