Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	153086908	1			T1	621494		T2	45056		T3	102400
instr_valid_dis	118249839	1			T1	621494		T2	45056		T3	102400
instr_en	23476898	1			T4	871124		T5	400006		T10	264682

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11063591	1			T4	150022		T5	84914		T10	45398
sram_ifetch_valid_disable	117751799	1			T1	621494		T2	45056		T3	102400
sram_ifetch_enable	24271518	1			T4	542882		T5	221064		T10	58846

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	153086908	1			T1	621494		T2	45056		T3	102400
hw_debug_en_valid_off	115694399	1			T1	621494		T2	45056		T3	102400
hw_debug_en_on	23969109	1			T4	532762		T5	201644		T10	10230

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	117751799	1			T1	621494		T2	45056		T3	102400
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	103528471	1			T1	621494		T2	45056		T3	102400
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9591346	1			T4	305272		T5	94028		T10	160438
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3804496	1			T4	86360		T5	26314		T10	37412
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1473360	1			T138	16496		T137	23070		T119	17856
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1840198	1			T4	86360		T5	26314		T10	37412
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4576811	1			T4	42586		T5	58600		T10	7986
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1736572	1			T133	25892		T137	5248		T134	18894
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2015548	1			T4	38734		T5	58600		T10	7986
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9887208	1			T4	256924		T5	4526		T58	42370
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4066106	1			T4	39584		T58	17076		T20	46524
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3636352	1			T4	185302		T5	4526		T58	25294

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9347442	1			T4	439682		T5	221064		T10	58846
lc_exec_en	9505090	1			T4	233252		T5	138518		T10	2244
valid_exec_dis	112319587	1			T1	621494		T2	45056		T3	102400
invalid_exec_dis	35335109	1			T4	692904		T5	305978		T10	104244