Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44916261	1			T1	56328		T2	22528		T3	51200
triple_byte_access	2666623	1			T1	51085		T4	7112		T5	1418
halfword_access	4006119	1			T1	76408		T4	10932		T5	2149
byte_access	5341335	1			T1	101436		T4	14670		T5	2942
zero_access	1344654	1			T1	25490		T4	3515		T5	711

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29081162

1

T1

155311

T2

11264

T3

25600

auto[1]

29193830

1

T1

155436

T2

11264

T3

25600

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22405551	1			T1	28091		T2	11264		T3	25600
auto[0]	triple_byte_access	1330063	1			T1	25439		T4	3544		T5	704
auto[0]	halfword_access	1999451	1			T1	38231		T4	5404		T5	1043
auto[0]	byte_access	2669338	1			T1	50719		T4	7336		T5	1462
auto[0]	zero_access	676759	1			T1	12831		T4	1764		T5	371
auto[1]	word_access	22510710	1			T1	28237		T2	11264		T3	25600
auto[1]	triple_byte_access	1336560	1			T1	25646		T4	3568		T5	714
auto[1]	halfword_access	2006668	1			T1	38177		T4	5528		T5	1106
auto[1]	byte_access	2671997	1			T1	50717		T4	7334		T5	1480
auto[1]	zero_access	667895	1			T1	12659		T4	1751		T5	340