| T791 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2523239874 |
|
|
Aug 12 04:48:12 PM PDT 24 |
Aug 12 04:48:13 PM PDT 24 |
79809064 ps |
| T792 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3154349899 |
|
|
Aug 12 04:51:53 PM PDT 24 |
Aug 12 04:57:53 PM PDT 24 |
9403066506 ps |
| T793 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1407584310 |
|
|
Aug 12 04:47:49 PM PDT 24 |
Aug 12 04:53:35 PM PDT 24 |
9578815616 ps |
| T794 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.960907221 |
|
|
Aug 12 04:48:04 PM PDT 24 |
Aug 12 04:48:11 PM PDT 24 |
1279964374 ps |
| T795 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.1224721598 |
|
|
Aug 12 04:52:17 PM PDT 24 |
Aug 12 04:52:19 PM PDT 24 |
137529928 ps |
| T796 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.447636252 |
|
|
Aug 12 04:51:19 PM PDT 24 |
Aug 12 04:59:22 PM PDT 24 |
883233403 ps |
| T797 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.90001300 |
|
|
Aug 12 04:48:03 PM PDT 24 |
Aug 12 04:48:04 PM PDT 24 |
58086972 ps |
| T798 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.4208659310 |
|
|
Aug 12 04:47:15 PM PDT 24 |
Aug 12 04:54:08 PM PDT 24 |
27730290814 ps |
| T799 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1977643056 |
|
|
Aug 12 04:47:42 PM PDT 24 |
Aug 12 04:47:47 PM PDT 24 |
1112615954 ps |
| T800 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3630593936 |
|
|
Aug 12 04:47:14 PM PDT 24 |
Aug 12 04:47:21 PM PDT 24 |
433627440 ps |
| T801 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2689575373 |
|
|
Aug 12 04:47:08 PM PDT 24 |
Aug 12 04:51:06 PM PDT 24 |
29536121820 ps |
| T802 |
/workspace/coverage/default/11.sram_ctrl_smoke.2964129855 |
|
|
Aug 12 04:47:36 PM PDT 24 |
Aug 12 04:50:03 PM PDT 24 |
5347175174 ps |
| T803 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.886471957 |
|
|
Aug 12 04:52:58 PM PDT 24 |
Aug 12 04:55:12 PM PDT 24 |
641050359 ps |
| T804 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.59617682 |
|
|
Aug 12 04:51:46 PM PDT 24 |
Aug 12 04:51:57 PM PDT 24 |
2258082803 ps |
| T805 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1913801621 |
|
|
Aug 12 04:48:02 PM PDT 24 |
Aug 12 04:48:03 PM PDT 24 |
41382685 ps |
| T806 |
/workspace/coverage/default/20.sram_ctrl_stress_all.2467922996 |
|
|
Aug 12 04:48:24 PM PDT 24 |
Aug 12 05:32:14 PM PDT 24 |
209491962018 ps |
| T807 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.688068158 |
|
|
Aug 12 04:48:28 PM PDT 24 |
Aug 12 04:52:55 PM PDT 24 |
11023481696 ps |
| T808 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.912344362 |
|
|
Aug 12 04:50:50 PM PDT 24 |
Aug 12 04:50:51 PM PDT 24 |
52056387 ps |
| T809 |
/workspace/coverage/default/4.sram_ctrl_regwen.1741691527 |
|
|
Aug 12 04:47:13 PM PDT 24 |
Aug 12 05:16:33 PM PDT 24 |
15537423832 ps |
| T810 |
/workspace/coverage/default/16.sram_ctrl_executable.2243156985 |
|
|
Aug 12 04:47:58 PM PDT 24 |
Aug 12 04:54:08 PM PDT 24 |
9461613928 ps |
| T811 |
/workspace/coverage/default/30.sram_ctrl_partial_access.450384017 |
|
|
Aug 12 04:49:35 PM PDT 24 |
Aug 12 04:50:55 PM PDT 24 |
1142758673 ps |
| T812 |
/workspace/coverage/default/32.sram_ctrl_smoke.2441259101 |
|
|
Aug 12 04:49:47 PM PDT 24 |
Aug 12 04:49:54 PM PDT 24 |
1173615068 ps |
| T813 |
/workspace/coverage/default/11.sram_ctrl_regwen.1865323721 |
|
|
Aug 12 04:47:41 PM PDT 24 |
Aug 12 05:09:55 PM PDT 24 |
15963194448 ps |
| T814 |
/workspace/coverage/default/27.sram_ctrl_regwen.1121969012 |
|
|
Aug 12 04:49:12 PM PDT 24 |
Aug 12 04:54:44 PM PDT 24 |
5950513096 ps |
| T815 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2166968849 |
|
|
Aug 12 04:47:08 PM PDT 24 |
Aug 12 04:49:08 PM PDT 24 |
141070740 ps |
| T816 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3090651886 |
|
|
Aug 12 04:49:13 PM PDT 24 |
Aug 12 05:02:56 PM PDT 24 |
15385938659 ps |
| T817 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1292234105 |
|
|
Aug 12 04:48:09 PM PDT 24 |
Aug 12 04:48:22 PM PDT 24 |
162921368 ps |
| T818 |
/workspace/coverage/default/23.sram_ctrl_alert_test.3831868906 |
|
|
Aug 12 04:48:46 PM PDT 24 |
Aug 12 04:48:47 PM PDT 24 |
14218094 ps |
| T819 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3903947687 |
|
|
Aug 12 04:52:02 PM PDT 24 |
Aug 12 05:00:40 PM PDT 24 |
8282498951 ps |
| T820 |
/workspace/coverage/default/26.sram_ctrl_executable.1502895475 |
|
|
Aug 12 04:48:59 PM PDT 24 |
Aug 12 05:13:27 PM PDT 24 |
34022578976 ps |
| T821 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.569166312 |
|
|
Aug 12 04:47:00 PM PDT 24 |
Aug 12 04:47:35 PM PDT 24 |
109138687 ps |
| T822 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2379034329 |
|
|
Aug 12 04:47:33 PM PDT 24 |
Aug 12 04:47:34 PM PDT 24 |
35955526 ps |
| T823 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.3557724123 |
|
|
Aug 12 04:51:41 PM PDT 24 |
Aug 12 04:51:52 PM PDT 24 |
1841686321 ps |
| T824 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.933534179 |
|
|
Aug 12 04:49:12 PM PDT 24 |
Aug 12 04:49:20 PM PDT 24 |
431720827 ps |
| T825 |
/workspace/coverage/default/8.sram_ctrl_executable.2179803323 |
|
|
Aug 12 04:47:21 PM PDT 24 |
Aug 12 05:15:18 PM PDT 24 |
98155445939 ps |
| T826 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1413750811 |
|
|
Aug 12 04:52:58 PM PDT 24 |
Aug 12 04:53:01 PM PDT 24 |
88733813 ps |
| T827 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3685416530 |
|
|
Aug 12 04:48:10 PM PDT 24 |
Aug 12 04:49:01 PM PDT 24 |
192272781 ps |
| T828 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1009722680 |
|
|
Aug 12 04:52:11 PM PDT 24 |
Aug 12 04:52:12 PM PDT 24 |
30967648 ps |
| T829 |
/workspace/coverage/default/28.sram_ctrl_executable.515825626 |
|
|
Aug 12 04:49:25 PM PDT 24 |
Aug 12 04:58:14 PM PDT 24 |
15990336939 ps |
| T830 |
/workspace/coverage/default/41.sram_ctrl_bijection.1412673489 |
|
|
Aug 12 04:51:39 PM PDT 24 |
Aug 12 04:52:55 PM PDT 24 |
7117584592 ps |
| T831 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.271069633 |
|
|
Aug 12 04:50:29 PM PDT 24 |
Aug 12 04:50:32 PM PDT 24 |
370330473 ps |
| T832 |
/workspace/coverage/default/22.sram_ctrl_bijection.1144767464 |
|
|
Aug 12 04:48:32 PM PDT 24 |
Aug 12 04:49:04 PM PDT 24 |
971270186 ps |
| T833 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2003479009 |
|
|
Aug 12 04:49:28 PM PDT 24 |
Aug 12 05:03:12 PM PDT 24 |
25564153476 ps |
| T834 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3324541899 |
|
|
Aug 12 04:52:14 PM PDT 24 |
Aug 12 04:55:29 PM PDT 24 |
16021166349 ps |
| T835 |
/workspace/coverage/default/1.sram_ctrl_partial_access.2768661027 |
|
|
Aug 12 04:47:00 PM PDT 24 |
Aug 12 04:47:05 PM PDT 24 |
558301518 ps |
| T836 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2616552479 |
|
|
Aug 12 04:46:55 PM PDT 24 |
Aug 12 04:52:35 PM PDT 24 |
13571704763 ps |
| T837 |
/workspace/coverage/default/2.sram_ctrl_regwen.4035822003 |
|
|
Aug 12 04:47:02 PM PDT 24 |
Aug 12 05:14:43 PM PDT 24 |
31876570348 ps |
| T838 |
/workspace/coverage/default/4.sram_ctrl_bijection.1653684048 |
|
|
Aug 12 04:47:07 PM PDT 24 |
Aug 12 04:47:43 PM PDT 24 |
7850985044 ps |
| T839 |
/workspace/coverage/default/37.sram_ctrl_smoke.1927762154 |
|
|
Aug 12 04:50:42 PM PDT 24 |
Aug 12 04:51:17 PM PDT 24 |
212971103 ps |
| T840 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2335686679 |
|
|
Aug 12 04:49:35 PM PDT 24 |
Aug 12 04:50:28 PM PDT 24 |
483971178 ps |
| T841 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1511228246 |
|
|
Aug 12 04:51:01 PM PDT 24 |
Aug 12 04:51:07 PM PDT 24 |
378042629 ps |
| T842 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1400714091 |
|
|
Aug 12 04:53:05 PM PDT 24 |
Aug 12 04:53:11 PM PDT 24 |
340677259 ps |
| T843 |
/workspace/coverage/default/47.sram_ctrl_smoke.2331513260 |
|
|
Aug 12 04:52:36 PM PDT 24 |
Aug 12 04:52:46 PM PDT 24 |
1600598020 ps |
| T844 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2344176944 |
|
|
Aug 12 04:47:01 PM PDT 24 |
Aug 12 04:52:33 PM PDT 24 |
3871538948 ps |
| T845 |
/workspace/coverage/default/40.sram_ctrl_bijection.814137572 |
|
|
Aug 12 04:51:19 PM PDT 24 |
Aug 12 04:51:48 PM PDT 24 |
1559697483 ps |
| T846 |
/workspace/coverage/default/32.sram_ctrl_executable.1357665860 |
|
|
Aug 12 04:49:54 PM PDT 24 |
Aug 12 04:51:09 PM PDT 24 |
1368363086 ps |
| T847 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.3442033262 |
|
|
Aug 12 04:48:39 PM PDT 24 |
Aug 12 04:49:17 PM PDT 24 |
99367917 ps |
| T848 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.306795024 |
|
|
Aug 12 04:51:50 PM PDT 24 |
Aug 12 04:51:51 PM PDT 24 |
145561209 ps |
| T849 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.542272352 |
|
|
Aug 12 04:47:56 PM PDT 24 |
Aug 12 04:47:59 PM PDT 24 |
115574241 ps |
| T850 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.46048320 |
|
|
Aug 12 04:47:23 PM PDT 24 |
Aug 12 04:49:52 PM PDT 24 |
513648294 ps |
| T851 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.511353699 |
|
|
Aug 12 04:48:24 PM PDT 24 |
Aug 12 04:48:29 PM PDT 24 |
1230174199 ps |
| T852 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.2440827497 |
|
|
Aug 12 04:48:17 PM PDT 24 |
Aug 12 05:00:06 PM PDT 24 |
2940574038 ps |
| T853 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2033119602 |
|
|
Aug 12 04:48:26 PM PDT 24 |
Aug 12 04:51:03 PM PDT 24 |
2680035152 ps |
| T854 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.2629523952 |
|
|
Aug 12 04:51:13 PM PDT 24 |
Aug 12 04:51:28 PM PDT 24 |
72199372 ps |
| T855 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2769685834 |
|
|
Aug 12 04:47:17 PM PDT 24 |
Aug 12 04:53:46 PM PDT 24 |
10602833934 ps |
| T856 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.2755979904 |
|
|
Aug 12 04:48:07 PM PDT 24 |
Aug 12 04:58:00 PM PDT 24 |
3802490408 ps |
| T857 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2264768652 |
|
|
Aug 12 04:52:16 PM PDT 24 |
Aug 12 04:55:26 PM PDT 24 |
2582011207 ps |
| T858 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.951365395 |
|
|
Aug 12 04:48:39 PM PDT 24 |
Aug 12 04:51:23 PM PDT 24 |
6902575881 ps |
| T859 |
/workspace/coverage/default/27.sram_ctrl_bijection.1091836265 |
|
|
Aug 12 04:49:10 PM PDT 24 |
Aug 12 04:49:59 PM PDT 24 |
1641741080 ps |
| T860 |
/workspace/coverage/default/10.sram_ctrl_stress_all.2737664119 |
|
|
Aug 12 04:47:33 PM PDT 24 |
Aug 12 05:11:01 PM PDT 24 |
82845808548 ps |
| T861 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2023114563 |
|
|
Aug 12 04:47:24 PM PDT 24 |
Aug 12 04:47:25 PM PDT 24 |
78504857 ps |
| T862 |
/workspace/coverage/default/3.sram_ctrl_alert_test.3150802215 |
|
|
Aug 12 04:47:07 PM PDT 24 |
Aug 12 04:47:08 PM PDT 24 |
24605161 ps |
| T863 |
/workspace/coverage/default/48.sram_ctrl_partial_access.1485641081 |
|
|
Aug 12 04:52:48 PM PDT 24 |
Aug 12 04:52:51 PM PDT 24 |
185111715 ps |
| T864 |
/workspace/coverage/default/47.sram_ctrl_regwen.4023122866 |
|
|
Aug 12 04:52:45 PM PDT 24 |
Aug 12 05:11:23 PM PDT 24 |
20157669526 ps |
| T865 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.610187108 |
|
|
Aug 12 04:47:31 PM PDT 24 |
Aug 12 04:47:42 PM PDT 24 |
2361197835 ps |
| T866 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.4070458533 |
|
|
Aug 12 04:47:56 PM PDT 24 |
Aug 12 04:50:43 PM PDT 24 |
5660886080 ps |
| T867 |
/workspace/coverage/default/44.sram_ctrl_executable.186537215 |
|
|
Aug 12 04:52:09 PM PDT 24 |
Aug 12 05:11:42 PM PDT 24 |
15202463082 ps |
| T868 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.6503504 |
|
|
Aug 12 04:48:47 PM PDT 24 |
Aug 12 04:48:53 PM PDT 24 |
700153844 ps |
| T869 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.516061490 |
|
|
Aug 12 04:47:34 PM PDT 24 |
Aug 12 04:52:14 PM PDT 24 |
11331387322 ps |
| T870 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3303412509 |
|
|
Aug 12 04:51:47 PM PDT 24 |
Aug 12 05:39:10 PM PDT 24 |
30817981287 ps |
| T871 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1475112093 |
|
|
Aug 12 04:47:35 PM PDT 24 |
Aug 12 04:51:13 PM PDT 24 |
2277625436 ps |
| T872 |
/workspace/coverage/default/18.sram_ctrl_regwen.1256827044 |
|
|
Aug 12 04:48:09 PM PDT 24 |
Aug 12 05:00:58 PM PDT 24 |
84511000559 ps |
| T873 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1251784430 |
|
|
Aug 12 04:52:00 PM PDT 24 |
Aug 12 04:52:09 PM PDT 24 |
694291395 ps |
| T874 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3744176069 |
|
|
Aug 12 04:48:40 PM PDT 24 |
Aug 12 04:48:48 PM PDT 24 |
769373552 ps |
| T875 |
/workspace/coverage/default/34.sram_ctrl_stress_all.122359964 |
|
|
Aug 12 04:50:22 PM PDT 24 |
Aug 12 05:06:04 PM PDT 24 |
9693108350 ps |
| T876 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3491250945 |
|
|
Aug 12 04:47:36 PM PDT 24 |
Aug 12 04:47:37 PM PDT 24 |
62199693 ps |
| T877 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.645511060 |
|
|
Aug 12 04:50:44 PM PDT 24 |
Aug 12 04:52:36 PM PDT 24 |
1131675163 ps |
| T878 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.793513925 |
|
|
Aug 12 04:50:01 PM PDT 24 |
Aug 12 04:50:04 PM PDT 24 |
222977154 ps |
| T879 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3906924948 |
|
|
Aug 12 04:47:13 PM PDT 24 |
Aug 12 04:47:16 PM PDT 24 |
64112088 ps |
| T880 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.62305656 |
|
|
Aug 12 04:48:52 PM PDT 24 |
Aug 12 04:48:58 PM PDT 24 |
456483304 ps |
| T881 |
/workspace/coverage/default/17.sram_ctrl_partial_access.343518193 |
|
|
Aug 12 04:48:05 PM PDT 24 |
Aug 12 04:48:54 PM PDT 24 |
619980269 ps |
| T882 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2018541499 |
|
|
Aug 12 04:47:37 PM PDT 24 |
Aug 12 04:47:44 PM PDT 24 |
1704642838 ps |
| T883 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.2717454306 |
|
|
Aug 12 04:52:49 PM PDT 24 |
Aug 12 04:52:56 PM PDT 24 |
191971608 ps |
| T884 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1606287019 |
|
|
Aug 12 04:48:10 PM PDT 24 |
Aug 12 04:53:04 PM PDT 24 |
43840473895 ps |
| T885 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.3025053955 |
|
|
Aug 12 04:51:17 PM PDT 24 |
Aug 12 04:51:27 PM PDT 24 |
1755652800 ps |
| T886 |
/workspace/coverage/default/5.sram_ctrl_alert_test.1076415874 |
|
|
Aug 12 04:47:15 PM PDT 24 |
Aug 12 04:47:16 PM PDT 24 |
40752291 ps |
| T887 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1470618115 |
|
|
Aug 12 04:49:11 PM PDT 24 |
Aug 12 04:53:12 PM PDT 24 |
14997234847 ps |
| T888 |
/workspace/coverage/default/29.sram_ctrl_regwen.2229883257 |
|
|
Aug 12 04:49:26 PM PDT 24 |
Aug 12 05:07:05 PM PDT 24 |
19286411861 ps |
| T889 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.3286892104 |
|
|
Aug 12 04:47:36 PM PDT 24 |
Aug 12 04:48:45 PM PDT 24 |
528488257 ps |
| T890 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.4101883038 |
|
|
Aug 12 04:47:01 PM PDT 24 |
Aug 12 04:47:10 PM PDT 24 |
732089619 ps |
| T891 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3925762278 |
|
|
Aug 12 04:51:18 PM PDT 24 |
Aug 12 04:51:20 PM PDT 24 |
72998931 ps |
| T892 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3795478489 |
|
|
Aug 12 04:49:08 PM PDT 24 |
Aug 12 04:57:26 PM PDT 24 |
2335067511 ps |
| T893 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.737148483 |
|
|
Aug 12 04:49:33 PM PDT 24 |
Aug 12 04:51:31 PM PDT 24 |
1196591298 ps |
| T894 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3153050860 |
|
|
Aug 12 04:47:39 PM PDT 24 |
Aug 12 05:39:49 PM PDT 24 |
51002145106 ps |
| T895 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.3870203169 |
|
|
Aug 12 04:50:01 PM PDT 24 |
Aug 12 05:15:55 PM PDT 24 |
3790819919 ps |
| T896 |
/workspace/coverage/default/29.sram_ctrl_stress_all.1983577982 |
|
|
Aug 12 04:49:33 PM PDT 24 |
Aug 12 05:38:11 PM PDT 24 |
20646931225 ps |
| T897 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.644896978 |
|
|
Aug 12 04:49:41 PM PDT 24 |
Aug 12 04:55:33 PM PDT 24 |
64238522229 ps |
| T898 |
/workspace/coverage/default/48.sram_ctrl_bijection.2529570072 |
|
|
Aug 12 04:52:50 PM PDT 24 |
Aug 12 04:53:30 PM PDT 24 |
7241611358 ps |
| T899 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1916543860 |
|
|
Aug 12 04:52:15 PM PDT 24 |
Aug 12 04:54:36 PM PDT 24 |
1480793027 ps |
| T900 |
/workspace/coverage/default/27.sram_ctrl_alert_test.166299962 |
|
|
Aug 12 04:49:20 PM PDT 24 |
Aug 12 04:49:21 PM PDT 24 |
33625060 ps |
| T901 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.840450095 |
|
|
Aug 12 04:49:19 PM PDT 24 |
Aug 12 04:50:33 PM PDT 24 |
139483289 ps |
| T902 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.890616977 |
|
|
Aug 12 04:47:50 PM PDT 24 |
Aug 12 04:47:51 PM PDT 24 |
30295583 ps |
| T903 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3648181853 |
|
|
Aug 12 04:47:25 PM PDT 24 |
Aug 12 04:50:21 PM PDT 24 |
1879846328 ps |
| T904 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.814420646 |
|
|
Aug 12 04:50:09 PM PDT 24 |
Aug 12 04:55:18 PM PDT 24 |
2955789500 ps |
| T905 |
/workspace/coverage/default/10.sram_ctrl_executable.1938568996 |
|
|
Aug 12 04:47:29 PM PDT 24 |
Aug 12 04:57:21 PM PDT 24 |
3255349047 ps |
| T906 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.849971229 |
|
|
Aug 12 04:52:58 PM PDT 24 |
Aug 12 04:55:55 PM PDT 24 |
3386763587 ps |
| T907 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.516806073 |
|
|
Aug 12 04:47:25 PM PDT 24 |
Aug 12 04:51:30 PM PDT 24 |
2477363830 ps |
| T908 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3273068403 |
|
|
Aug 12 04:52:58 PM PDT 24 |
Aug 12 04:52:58 PM PDT 24 |
38178075 ps |
| T909 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1745011939 |
|
|
Aug 12 04:49:34 PM PDT 24 |
Aug 12 04:52:25 PM PDT 24 |
407146583 ps |
| T910 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.3963753570 |
|
|
Aug 12 04:48:19 PM PDT 24 |
Aug 12 04:48:20 PM PDT 24 |
47387435 ps |
| T911 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3222500967 |
|
|
Aug 12 04:52:01 PM PDT 24 |
Aug 12 04:58:24 PM PDT 24 |
3054203922 ps |
| T912 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3146783855 |
|
|
Aug 12 04:48:09 PM PDT 24 |
Aug 12 04:50:17 PM PDT 24 |
2259426736 ps |
| T913 |
/workspace/coverage/default/24.sram_ctrl_alert_test.597262993 |
|
|
Aug 12 04:48:54 PM PDT 24 |
Aug 12 04:48:55 PM PDT 24 |
41893124 ps |
| T914 |
/workspace/coverage/default/35.sram_ctrl_bijection.544152759 |
|
|
Aug 12 04:50:29 PM PDT 24 |
Aug 12 04:51:28 PM PDT 24 |
2712092449 ps |
| T915 |
/workspace/coverage/default/40.sram_ctrl_executable.3080904263 |
|
|
Aug 12 04:51:25 PM PDT 24 |
Aug 12 05:09:09 PM PDT 24 |
27565033207 ps |
| T916 |
/workspace/coverage/default/11.sram_ctrl_alert_test.95229263 |
|
|
Aug 12 04:47:44 PM PDT 24 |
Aug 12 04:47:45 PM PDT 24 |
32513755 ps |
| T917 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1456758450 |
|
|
Aug 12 04:52:43 PM PDT 24 |
Aug 12 04:52:44 PM PDT 24 |
16827580 ps |
| T918 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1007871018 |
|
|
Aug 12 04:51:46 PM PDT 24 |
Aug 12 04:53:57 PM PDT 24 |
12682955435 ps |
| T919 |
/workspace/coverage/default/33.sram_ctrl_stress_all.3349774147 |
|
|
Aug 12 04:50:11 PM PDT 24 |
Aug 12 05:32:33 PM PDT 24 |
13287642812 ps |
| T920 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2359441274 |
|
|
Aug 12 04:52:02 PM PDT 24 |
Aug 12 04:52:03 PM PDT 24 |
14070763 ps |
| T29 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.621967555 |
|
|
Aug 12 04:47:07 PM PDT 24 |
Aug 12 04:47:10 PM PDT 24 |
345025077 ps |
| T921 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.2326053136 |
|
|
Aug 12 04:47:48 PM PDT 24 |
Aug 12 05:05:04 PM PDT 24 |
16233238426 ps |
| T922 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2810020826 |
|
|
Aug 12 04:47:37 PM PDT 24 |
Aug 12 04:50:11 PM PDT 24 |
372340743 ps |
| T923 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.1190062525 |
|
|
Aug 12 04:50:12 PM PDT 24 |
Aug 12 04:50:13 PM PDT 24 |
29780547 ps |
| T924 |
/workspace/coverage/default/28.sram_ctrl_alert_test.2221075991 |
|
|
Aug 12 04:49:27 PM PDT 24 |
Aug 12 04:49:28 PM PDT 24 |
41904839 ps |
| T925 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.785252271 |
|
|
Aug 12 04:47:21 PM PDT 24 |
Aug 12 04:47:27 PM PDT 24 |
90671501 ps |
| T926 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2721197942 |
|
|
Aug 12 04:49:26 PM PDT 24 |
Aug 12 04:51:53 PM PDT 24 |
500236690 ps |
| T30 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.460560975 |
|
|
Aug 12 04:46:57 PM PDT 24 |
Aug 12 04:47:01 PM PDT 24 |
426513381 ps |
| T927 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2934762684 |
|
|
Aug 12 04:48:52 PM PDT 24 |
Aug 12 04:50:53 PM PDT 24 |
1571485748 ps |
| T928 |
/workspace/coverage/default/39.sram_ctrl_stress_all.3780931221 |
|
|
Aug 12 04:51:18 PM PDT 24 |
Aug 12 05:36:29 PM PDT 24 |
35838974714 ps |
| T929 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.3906029765 |
|
|
Aug 12 04:48:57 PM PDT 24 |
Aug 12 04:48:58 PM PDT 24 |
83942347 ps |
| T930 |
/workspace/coverage/default/26.sram_ctrl_regwen.2285697842 |
|
|
Aug 12 04:49:05 PM PDT 24 |
Aug 12 05:08:07 PM PDT 24 |
6083645907 ps |
| T931 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1498577059 |
|
|
Aug 12 04:47:29 PM PDT 24 |
Aug 12 04:58:35 PM PDT 24 |
1647872494 ps |
| T932 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3342316336 |
|
|
Aug 12 04:47:06 PM PDT 24 |
Aug 12 04:47:07 PM PDT 24 |
36207548 ps |
| T933 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.399924232 |
|
|
Aug 12 04:49:00 PM PDT 24 |
Aug 12 04:52:31 PM PDT 24 |
4301975006 ps |
| T934 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3977773758 |
|
|
Aug 12 04:52:30 PM PDT 24 |
Aug 12 04:52:34 PM PDT 24 |
212021911 ps |
| T935 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3700598420 |
|
|
Aug 12 04:39:45 PM PDT 24 |
Aug 12 04:39:47 PM PDT 24 |
266318369 ps |
| T72 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3986939134 |
|
|
Aug 12 04:40:01 PM PDT 24 |
Aug 12 04:40:01 PM PDT 24 |
30662871 ps |
| T73 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3120364094 |
|
|
Aug 12 04:39:42 PM PDT 24 |
Aug 12 04:39:42 PM PDT 24 |
21996840 ps |
| T74 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.692368594 |
|
|
Aug 12 04:39:53 PM PDT 24 |
Aug 12 04:39:55 PM PDT 24 |
927799091 ps |
| T86 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2769468395 |
|
|
Aug 12 04:39:46 PM PDT 24 |
Aug 12 04:39:47 PM PDT 24 |
41319979 ps |
| T87 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3198620969 |
|
|
Aug 12 04:39:57 PM PDT 24 |
Aug 12 04:39:59 PM PDT 24 |
216083219 ps |
| T68 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3800821938 |
|
|
Aug 12 04:39:37 PM PDT 24 |
Aug 12 04:39:39 PM PDT 24 |
254823534 ps |
| T88 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2294990594 |
|
|
Aug 12 04:39:48 PM PDT 24 |
Aug 12 04:39:51 PM PDT 24 |
576933235 ps |
| T936 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3796405193 |
|
|
Aug 12 04:39:52 PM PDT 24 |
Aug 12 04:39:55 PM PDT 24 |
123827255 ps |
| T89 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.559957245 |
|
|
Aug 12 04:39:47 PM PDT 24 |
Aug 12 04:39:48 PM PDT 24 |
14373327 ps |
| T937 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1238533816 |
|
|
Aug 12 04:39:48 PM PDT 24 |
Aug 12 04:39:49 PM PDT 24 |
43976814 ps |
| T938 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3498305810 |
|
|
Aug 12 04:39:45 PM PDT 24 |
Aug 12 04:39:46 PM PDT 24 |
172966881 ps |
| T939 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3523649870 |
|
|
Aug 12 04:40:01 PM PDT 24 |
Aug 12 04:40:04 PM PDT 24 |
287810527 ps |
| T940 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4140944138 |
|
|
Aug 12 04:39:53 PM PDT 24 |
Aug 12 04:39:54 PM PDT 24 |
97642781 ps |
| T90 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4215179675 |
|
|
Aug 12 04:39:54 PM PDT 24 |
Aug 12 04:39:57 PM PDT 24 |
1491322880 ps |
| T91 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.47002880 |
|
|
Aug 12 04:39:48 PM PDT 24 |
Aug 12 04:39:50 PM PDT 24 |
299176899 ps |
| T941 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3942341651 |
|
|
Aug 12 04:39:53 PM PDT 24 |
Aug 12 04:39:55 PM PDT 24 |
33774939 ps |
| T942 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.372903211 |
|
|
Aug 12 04:39:56 PM PDT 24 |
Aug 12 04:39:58 PM PDT 24 |
41005149 ps |
| T92 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.873584961 |
|
|
Aug 12 04:39:55 PM PDT 24 |
Aug 12 04:39:56 PM PDT 24 |
69531449 ps |
| T943 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1809452403 |
|
|
Aug 12 04:39:39 PM PDT 24 |
Aug 12 04:39:41 PM PDT 24 |
31097453 ps |
| T93 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1966629017 |
|
|
Aug 12 04:39:48 PM PDT 24 |
Aug 12 04:39:50 PM PDT 24 |
391481344 ps |
| T944 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2670329540 |
|
|
Aug 12 04:39:39 PM PDT 24 |
Aug 12 04:39:40 PM PDT 24 |
90164099 ps |
| T69 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.603453056 |
|
|
Aug 12 04:39:39 PM PDT 24 |
Aug 12 04:39:41 PM PDT 24 |
142532124 ps |
| T945 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2374502264 |
|
|
Aug 12 04:39:54 PM PDT 24 |
Aug 12 04:39:56 PM PDT 24 |
64129782 ps |
| T110 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3765153133 |
|
|
Aug 12 04:39:47 PM PDT 24 |
Aug 12 04:39:49 PM PDT 24 |
246217454 ps |
| T94 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.854304867 |
|
|
Aug 12 04:39:55 PM PDT 24 |
Aug 12 04:39:58 PM PDT 24 |
1515564249 ps |
| T70 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1546896839 |
|
|
Aug 12 04:40:04 PM PDT 24 |
Aug 12 04:40:06 PM PDT 24 |
239588008 ps |
| T946 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2826076330 |
|
|
Aug 12 04:39:44 PM PDT 24 |
Aug 12 04:39:45 PM PDT 24 |
18565962 ps |
| T947 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3359088996 |
|
|
Aug 12 04:40:00 PM PDT 24 |
Aug 12 04:40:02 PM PDT 24 |
39489427 ps |
| T121 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1279028213 |
|
|
Aug 12 04:39:45 PM PDT 24 |
Aug 12 04:39:48 PM PDT 24 |
2994599715 ps |
| T95 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3895658889 |
|
|
Aug 12 04:40:11 PM PDT 24 |
Aug 12 04:40:13 PM PDT 24 |
1970815653 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3004536756 |
|
|
Aug 12 04:39:39 PM PDT 24 |
Aug 12 04:39:40 PM PDT 24 |
56359792 ps |
| T949 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3866842880 |
|
|
Aug 12 04:39:56 PM PDT 24 |
Aug 12 04:39:59 PM PDT 24 |
300357081 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2236494085 |
|
|
Aug 12 04:39:56 PM PDT 24 |
Aug 12 04:39:57 PM PDT 24 |
15251917 ps |
| T951 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1805399151 |
|
|
Aug 12 04:40:11 PM PDT 24 |
Aug 12 04:40:11 PM PDT 24 |
14530525 ps |
| T952 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1683481806 |
|
|
Aug 12 04:39:37 PM PDT 24 |
Aug 12 04:39:38 PM PDT 24 |
11735261 ps |
| T124 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.954899918 |
|
|
Aug 12 04:39:48 PM PDT 24 |
Aug 12 04:39:49 PM PDT 24 |
425184805 ps |
| T953 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2684618915 |
|
|
Aug 12 04:39:49 PM PDT 24 |
Aug 12 04:39:52 PM PDT 24 |
103233916 ps |
| T130 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1799459515 |
|
|
Aug 12 04:40:09 PM PDT 24 |
Aug 12 04:40:11 PM PDT 24 |
409748087 ps |
| T954 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2480864267 |
|
|
Aug 12 04:39:56 PM PDT 24 |
Aug 12 04:39:59 PM PDT 24 |
201860861 ps |
| T105 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.573012149 |
|
|
Aug 12 04:39:54 PM PDT 24 |
Aug 12 04:39:55 PM PDT 24 |
16945368 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3526942359 |
|
|
Aug 12 04:39:50 PM PDT 24 |
Aug 12 04:39:51 PM PDT 24 |
42908061 ps |
| T956 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3467217816 |
|
|
Aug 12 04:39:55 PM PDT 24 |
Aug 12 04:39:57 PM PDT 24 |
884885812 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.105688615 |
|
|
Aug 12 04:39:54 PM PDT 24 |
Aug 12 04:39:54 PM PDT 24 |
18880081 ps |
| T958 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1081510359 |
|
|
Aug 12 04:39:53 PM PDT 24 |
Aug 12 04:39:54 PM PDT 24 |
62987845 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3400653527 |
|
|
Aug 12 04:40:04 PM PDT 24 |
Aug 12 04:40:05 PM PDT 24 |
15985737 ps |
| T960 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3703129606 |
|
|
Aug 12 04:39:54 PM PDT 24 |
Aug 12 04:39:55 PM PDT 24 |
54718035 ps |
| T103 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2782670703 |
|
|
Aug 12 04:39:45 PM PDT 24 |
Aug 12 04:39:46 PM PDT 24 |
19408130 ps |
| T961 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1255220 |
|
|
Aug 12 04:39:36 PM PDT 24 |
Aug 12 04:39:39 PM PDT 24 |
145493700 ps |
| T122 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3994448051 |
|
|
Aug 12 04:39:55 PM PDT 24 |
Aug 12 04:39:57 PM PDT 24 |
1026068560 ps |
| T962 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2751438865 |
|
|
Aug 12 04:39:49 PM PDT 24 |
Aug 12 04:39:51 PM PDT 24 |
221398501 ps |
| T104 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4216907636 |
|
|
Aug 12 04:39:58 PM PDT 24 |
Aug 12 04:40:01 PM PDT 24 |
2062527027 ps |
| T963 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3574015818 |
|
|
Aug 12 04:40:08 PM PDT 24 |
Aug 12 04:40:10 PM PDT 24 |
18449876 ps |
| T964 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3356346372 |
|
|
Aug 12 04:39:48 PM PDT 24 |
Aug 12 04:39:48 PM PDT 24 |
52963554 ps |
| T965 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1928724144 |
|
|
Aug 12 04:39:41 PM PDT 24 |
Aug 12 04:39:42 PM PDT 24 |
84368806 ps |
| T966 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4204678726 |
|
|
Aug 12 04:39:55 PM PDT 24 |
Aug 12 04:39:58 PM PDT 24 |
701222713 ps |
| T967 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.516465371 |
|
|
Aug 12 04:39:54 PM PDT 24 |
Aug 12 04:39:55 PM PDT 24 |
20541938 ps |
| T968 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3134833660 |
|
|
Aug 12 04:39:46 PM PDT 24 |
Aug 12 04:39:47 PM PDT 24 |
15715812 ps |
| T969 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3817893641 |
|
|
Aug 12 04:39:47 PM PDT 24 |
Aug 12 04:39:48 PM PDT 24 |
50005604 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2794429090 |
|
|
Aug 12 04:39:55 PM PDT 24 |
Aug 12 04:39:58 PM PDT 24 |
121988745 ps |
| T971 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1957531800 |
|
|
Aug 12 04:39:53 PM PDT 24 |
Aug 12 04:39:54 PM PDT 24 |
32246150 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3932232076 |
|
|
Aug 12 04:39:38 PM PDT 24 |
Aug 12 04:39:39 PM PDT 24 |
70251892 ps |
| T106 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1987221982 |
|
|
Aug 12 04:39:48 PM PDT 24 |
Aug 12 04:39:51 PM PDT 24 |
380129382 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2409332410 |
|
|
Aug 12 04:39:46 PM PDT 24 |
Aug 12 04:39:47 PM PDT 24 |
14028385 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.518620880 |
|
|
Aug 12 04:39:42 PM PDT 24 |
Aug 12 04:39:44 PM PDT 24 |
122350861 ps |
| T129 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3725403549 |
|
|
Aug 12 04:39:55 PM PDT 24 |
Aug 12 04:39:57 PM PDT 24 |
613859799 ps |
| T132 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3361666799 |
|
|
Aug 12 04:39:46 PM PDT 24 |
Aug 12 04:39:48 PM PDT 24 |
505668799 ps |
| T107 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1086596257 |
|
|
Aug 12 04:39:36 PM PDT 24 |
Aug 12 04:39:39 PM PDT 24 |
525614570 ps |
| T975 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2813694591 |
|
|
Aug 12 04:39:53 PM PDT 24 |
Aug 12 04:39:54 PM PDT 24 |
33281821 ps |
| T976 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.902628372 |
|
|
Aug 12 04:39:48 PM PDT 24 |
Aug 12 04:39:50 PM PDT 24 |
54940490 ps |
| T123 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.722303470 |
|
|
Aug 12 04:39:44 PM PDT 24 |
Aug 12 04:39:47 PM PDT 24 |
320421515 ps |
| T977 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1115819937 |
|
|
Aug 12 04:39:46 PM PDT 24 |
Aug 12 04:39:47 PM PDT 24 |
16665545 ps |
| T978 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.949606983 |
|
|
Aug 12 04:39:56 PM PDT 24 |
Aug 12 04:39:59 PM PDT 24 |
1145149525 ps |
| T979 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2794776779 |
|
|
Aug 12 04:39:55 PM PDT 24 |
Aug 12 04:39:56 PM PDT 24 |
26413442 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2171127946 |
|
|
Aug 12 04:39:48 PM PDT 24 |
Aug 12 04:39:50 PM PDT 24 |
96282498 ps |
| T981 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.6925397 |
|
|
Aug 12 04:39:55 PM PDT 24 |
Aug 12 04:39:56 PM PDT 24 |
140967316 ps |
| T139 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1980145389 |
|
|
Aug 12 04:40:03 PM PDT 24 |
Aug 12 04:40:06 PM PDT 24 |
480017130 ps |
| T127 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3073714457 |
|
|
Aug 12 04:39:42 PM PDT 24 |
Aug 12 04:39:44 PM PDT 24 |
661849298 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.694379716 |
|
|
Aug 12 04:39:41 PM PDT 24 |
Aug 12 04:39:42 PM PDT 24 |
102160685 ps |
| T983 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2164735136 |
|
|
Aug 12 04:40:02 PM PDT 24 |
Aug 12 04:40:06 PM PDT 24 |
105830196 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1107156700 |
|
|
Aug 12 04:39:44 PM PDT 24 |
Aug 12 04:39:44 PM PDT 24 |
14149348 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1046212735 |
|
|
Aug 12 04:39:44 PM PDT 24 |
Aug 12 04:39:46 PM PDT 24 |
103409484 ps |
| T986 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3815959466 |
|
|
Aug 12 04:39:54 PM PDT 24 |
Aug 12 04:39:55 PM PDT 24 |
21863137 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1277252363 |
|
|
Aug 12 04:39:37 PM PDT 24 |
Aug 12 04:39:40 PM PDT 24 |
1481402495 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.928233408 |
|
|
Aug 12 04:39:37 PM PDT 24 |
Aug 12 04:39:39 PM PDT 24 |
187500367 ps |
| T989 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4164133480 |
|
|
Aug 12 04:39:56 PM PDT 24 |
Aug 12 04:39:59 PM PDT 24 |
67587662 ps |
| T990 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.562347359 |
|
|
Aug 12 04:39:39 PM PDT 24 |
Aug 12 04:39:39 PM PDT 24 |
40643701 ps |
| T108 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3578064630 |
|
|
Aug 12 04:39:50 PM PDT 24 |
Aug 12 04:39:51 PM PDT 24 |
50730648 ps |
| T102 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3752149996 |
|
|
Aug 12 04:39:53 PM PDT 24 |
Aug 12 04:39:54 PM PDT 24 |
31688164 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.525063989 |
|
|
Aug 12 04:39:43 PM PDT 24 |
Aug 12 04:39:44 PM PDT 24 |
25343319 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3110661957 |
|
|
Aug 12 04:39:45 PM PDT 24 |
Aug 12 04:39:49 PM PDT 24 |
35492139 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3722307429 |
|
|
Aug 12 04:39:40 PM PDT 24 |
Aug 12 04:39:42 PM PDT 24 |
65097203 ps |
| T109 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1302251141 |
|
|
Aug 12 04:39:47 PM PDT 24 |
Aug 12 04:39:50 PM PDT 24 |
444547636 ps |
| T994 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4294745177 |
|
|
Aug 12 04:39:35 PM PDT 24 |
Aug 12 04:39:36 PM PDT 24 |
17491825 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.429374222 |
|
|
Aug 12 04:39:38 PM PDT 24 |
Aug 12 04:39:39 PM PDT 24 |
32586079 ps |
| T996 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2784864510 |
|
|
Aug 12 04:39:46 PM PDT 24 |
Aug 12 04:39:50 PM PDT 24 |
1375031273 ps |
| T997 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2058768087 |
|
|
Aug 12 04:39:44 PM PDT 24 |
Aug 12 04:39:49 PM PDT 24 |
153041247 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.45609977 |
|
|
Aug 12 04:39:37 PM PDT 24 |
Aug 12 04:39:39 PM PDT 24 |
1101840996 ps |
| T999 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3635636662 |
|
|
Aug 12 04:39:47 PM PDT 24 |
Aug 12 04:39:50 PM PDT 24 |
280564538 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3586429276 |
|
|
Aug 12 04:39:46 PM PDT 24 |
Aug 12 04:39:46 PM PDT 24 |
38215773 ps |
| T1001 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3740987108 |
|
|
Aug 12 04:39:45 PM PDT 24 |
Aug 12 04:39:49 PM PDT 24 |
117537374 ps |
| T1002 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1163693583 |
|
|
Aug 12 04:39:44 PM PDT 24 |
Aug 12 04:39:48 PM PDT 24 |
167965625 ps |
| T1003 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.331445793 |
|
|
Aug 12 04:39:55 PM PDT 24 |
Aug 12 04:39:56 PM PDT 24 |
73584957 ps |
| T1004 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1398014791 |
|
|
Aug 12 04:39:58 PM PDT 24 |
Aug 12 04:39:59 PM PDT 24 |
44470269 ps |