SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 9 | 0 | 9 | 100.00 |
Crosses | 16 | 0 | 16 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
csr_exec_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
en_sram_ifetch_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
lc_hw_debug_en_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
executable_cross | 16 | 0 | 16 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
instr_invalid_dis | 144785550 | 1 | T2 | 3718 | T3 | 10794 | T4 | 754042 | ||||
instr_valid_dis | 110706386 | 1 | T2 | 3718 | T3 | 10794 | T4 | 495418 | ||||
instr_en | 23264066 | 1 | T4 | 258624 | T10 | 63998 | T45 | 403304 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
sram_ifetch_invalid_disable | 11121665 | 1 | T4 | 179798 | T10 | 15746 | T7 | 60726 | ||||
sram_ifetch_valid_disable | 111528406 | 1 | T2 | 3718 | T3 | 10794 | T4 | 527596 | ||||
sram_ifetch_enable | 22135479 | 1 | T4 | 46648 | T10 | 158274 | T7 | 158918 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | 144785550 | 1 | T2 | 3718 | T3 | 10794 | T4 | 754042 | ||||
hw_debug_en_valid_off | 110484668 | 1 | T2 | 3718 | T3 | 10794 | T4 | 387678 | ||||
hw_debug_en_on | 23626085 | 1 | T4 | 249748 | T10 | 88872 | T7 | 174116 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 16 | 0 | 16 | 100.00 | |
Automatically Generated Cross Bins | 12 | 0 | 12 | 100.00 | |
User Defined Cross Bins | 4 | 0 | 4 | 100.00 |
lc_hw_debug_en_cp | en_sram_ifetch_cp | csr_exec_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_invalid_dis | 111528406 | 1 | T2 | 3718 | T3 | 10794 | T4 | 527596 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_valid_dis | 97685485 | 1 | T2 | 3718 | T3 | 10794 | T4 | 400428 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_en | 9658381 | 1 | T4 | 127168 | T10 | 20224 | T45 | 178384 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_invalid_dis | 4416449 | 1 | T4 | 68466 | T7 | 18912 | T19 | 36396 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_valid_dis | 1563866 | 1 | T4 | 68466 | T143 | 17104 | T24 | 3716 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_en | 2035986 | 1 | T45 | 21434 | T143 | 23492 | T20 | 20000 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_invalid_dis | 4582740 | 1 | T4 | 46764 | T10 | 15746 | T7 | 41814 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_valid_dis | 1649566 | 1 | T23 | 67966 | T20 | 12402 | T82 | 36966 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_en | 2503038 | 1 | T4 | 46764 | T10 | 15746 | T45 | 54026 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_invalid_dis | 9302599 | 1 | T4 | 187502 | T10 | 20224 | T7 | 33674 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_valid_dis | 3583760 | 1 | T4 | 144996 | T143 | 36990 | T147 | 27334 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_en | 4132093 | 1 | T4 | 42506 | T10 | 20224 | T45 | 79090 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
csr_exec_en | 8070735 | 1 | T4 | 20124 | T10 | 28028 | T45 | 149460 | ||||
lc_exec_en | 9740746 | 1 | T4 | 15482 | T10 | 52902 | T7 | 98628 | ||||
valid_exec_dis | 106390042 | 1 | T2 | 3718 | T3 | 10794 | T4 | 343884 | ||||
invalid_exec_dis | 33257144 | 1 | T4 | 226446 | T10 | 174020 | T7 | 219644 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |