Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42731536	1			T2	1680		T3	4442		T4	193134
triple_byte_access	2531118	1			T2	35		T3	201		T4	2414
halfword_access	3803241	1			T2	57		T3	269		T4	3518
byte_access	5080475	1			T2	73		T3	390		T4	4792
zero_access	1276655	1			T2	14		T3	95		T4	1165

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27651707

1

T2

911

T3

2726

T4

102688

auto[1]

27771318

1

T2

948

T3

2671

T4

102335

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21311490	1			T2	814		T3	2270		T4	96749
auto[0]	triple_byte_access	1261676	1			T2	19		T3	98		T4	1197
auto[0]	halfword_access	1896577	1			T2	35		T3	122		T4	1751
auto[0]	byte_access	2539276	1			T2	37		T3	194		T4	2417
auto[0]	zero_access	642688	1			T2	6		T3	42		T4	574
auto[1]	word_access	21420046	1			T2	866		T3	2172		T4	96385
auto[1]	triple_byte_access	1269442	1			T2	16		T3	103		T4	1217
auto[1]	halfword_access	1906664	1			T2	22		T3	147		T4	1767
auto[1]	byte_access	2541199	1			T2	36		T3	196		T4	2375
auto[1]	zero_access	633967	1			T2	8		T3	53		T4	591