| T796 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2777439919 |
|
|
Aug 13 04:34:55 PM PDT 24 |
Aug 13 04:34:56 PM PDT 24 |
81429327 ps |
| T797 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.98891540 |
|
|
Aug 13 04:33:58 PM PDT 24 |
Aug 13 04:34:09 PM PDT 24 |
688065466 ps |
| T798 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3908045048 |
|
|
Aug 13 04:35:31 PM PDT 24 |
Aug 13 04:57:23 PM PDT 24 |
14194559850 ps |
| T799 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2468901587 |
|
|
Aug 13 04:34:40 PM PDT 24 |
Aug 13 04:40:56 PM PDT 24 |
33825381007 ps |
| T800 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.2577838385 |
|
|
Aug 13 04:34:32 PM PDT 24 |
Aug 13 04:36:52 PM PDT 24 |
553902643 ps |
| T50 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3660020498 |
|
|
Aug 13 04:34:24 PM PDT 24 |
Aug 13 04:36:01 PM PDT 24 |
1619438738 ps |
| T801 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.949132742 |
|
|
Aug 13 04:34:55 PM PDT 24 |
Aug 13 04:36:03 PM PDT 24 |
154278930 ps |
| T802 |
/workspace/coverage/default/8.sram_ctrl_regwen.386451816 |
|
|
Aug 13 04:34:10 PM PDT 24 |
Aug 13 04:44:37 PM PDT 24 |
26582531228 ps |
| T803 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.792844547 |
|
|
Aug 13 04:35:28 PM PDT 24 |
Aug 13 04:57:26 PM PDT 24 |
13819517808 ps |
| T804 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.4092345962 |
|
|
Aug 13 04:35:05 PM PDT 24 |
Aug 13 04:35:14 PM PDT 24 |
1487535661 ps |
| T805 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.258074875 |
|
|
Aug 13 04:35:16 PM PDT 24 |
Aug 13 04:38:29 PM PDT 24 |
2127602479 ps |
| T806 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3882972957 |
|
|
Aug 13 04:35:14 PM PDT 24 |
Aug 13 04:35:27 PM PDT 24 |
9452676279 ps |
| T807 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1983672663 |
|
|
Aug 13 04:33:26 PM PDT 24 |
Aug 13 04:56:13 PM PDT 24 |
23475927189 ps |
| T808 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1968637761 |
|
|
Aug 13 04:34:05 PM PDT 24 |
Aug 13 05:39:07 PM PDT 24 |
255773787480 ps |
| T809 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.2384619648 |
|
|
Aug 13 04:34:48 PM PDT 24 |
Aug 13 04:34:49 PM PDT 24 |
88250117 ps |
| T810 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.1899155633 |
|
|
Aug 13 04:34:37 PM PDT 24 |
Aug 13 04:34:40 PM PDT 24 |
1096716341 ps |
| T811 |
/workspace/coverage/default/28.sram_ctrl_regwen.2065641580 |
|
|
Aug 13 04:34:36 PM PDT 24 |
Aug 13 04:59:02 PM PDT 24 |
10088060841 ps |
| T812 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.798940541 |
|
|
Aug 13 04:35:39 PM PDT 24 |
Aug 13 04:44:24 PM PDT 24 |
47082905568 ps |
| T813 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2159849586 |
|
|
Aug 13 04:35:10 PM PDT 24 |
Aug 13 04:37:29 PM PDT 24 |
280011303 ps |
| T814 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1796466412 |
|
|
Aug 13 04:33:36 PM PDT 24 |
Aug 13 04:33:42 PM PDT 24 |
656492344 ps |
| T815 |
/workspace/coverage/default/29.sram_ctrl_alert_test.368923927 |
|
|
Aug 13 04:34:56 PM PDT 24 |
Aug 13 04:34:57 PM PDT 24 |
15319955 ps |
| T816 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3910569724 |
|
|
Aug 13 04:34:14 PM PDT 24 |
Aug 13 04:46:37 PM PDT 24 |
77913881849 ps |
| T817 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.5406862 |
|
|
Aug 13 04:34:10 PM PDT 24 |
Aug 13 04:50:24 PM PDT 24 |
13813649737 ps |
| T818 |
/workspace/coverage/default/24.sram_ctrl_smoke.3486156512 |
|
|
Aug 13 04:34:30 PM PDT 24 |
Aug 13 04:34:43 PM PDT 24 |
1240307879 ps |
| T819 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2818624553 |
|
|
Aug 13 04:35:29 PM PDT 24 |
Aug 13 04:37:53 PM PDT 24 |
224160992 ps |
| T820 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2690716857 |
|
|
Aug 13 04:34:34 PM PDT 24 |
Aug 13 04:37:46 PM PDT 24 |
791203922 ps |
| T821 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2021240663 |
|
|
Aug 13 04:35:56 PM PDT 24 |
Aug 13 04:36:04 PM PDT 24 |
282750711 ps |
| T822 |
/workspace/coverage/default/1.sram_ctrl_smoke.1110843386 |
|
|
Aug 13 04:33:43 PM PDT 24 |
Aug 13 04:33:56 PM PDT 24 |
798669069 ps |
| T823 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.774982786 |
|
|
Aug 13 04:34:17 PM PDT 24 |
Aug 13 04:43:21 PM PDT 24 |
6627267372 ps |
| T824 |
/workspace/coverage/default/38.sram_ctrl_regwen.2700486351 |
|
|
Aug 13 04:35:13 PM PDT 24 |
Aug 13 04:39:31 PM PDT 24 |
3622652095 ps |
| T825 |
/workspace/coverage/default/45.sram_ctrl_bijection.3303670264 |
|
|
Aug 13 04:35:29 PM PDT 24 |
Aug 13 04:36:20 PM PDT 24 |
2660730965 ps |
| T826 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3198119848 |
|
|
Aug 13 04:33:59 PM PDT 24 |
Aug 13 04:42:39 PM PDT 24 |
1428815364 ps |
| T827 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.427693398 |
|
|
Aug 13 04:34:38 PM PDT 24 |
Aug 13 04:35:54 PM PDT 24 |
484545530 ps |
| T828 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1282895302 |
|
|
Aug 13 04:33:56 PM PDT 24 |
Aug 13 04:34:04 PM PDT 24 |
2607319284 ps |
| T829 |
/workspace/coverage/default/20.sram_ctrl_regwen.2591396864 |
|
|
Aug 13 04:34:35 PM PDT 24 |
Aug 13 04:39:34 PM PDT 24 |
1674665660 ps |
| T830 |
/workspace/coverage/default/13.sram_ctrl_executable.3239981056 |
|
|
Aug 13 04:34:06 PM PDT 24 |
Aug 13 04:50:03 PM PDT 24 |
49535443134 ps |
| T831 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1294689739 |
|
|
Aug 13 04:34:24 PM PDT 24 |
Aug 13 04:36:09 PM PDT 24 |
140218106 ps |
| T832 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3434715469 |
|
|
Aug 13 04:34:23 PM PDT 24 |
Aug 13 04:38:21 PM PDT 24 |
3223981093 ps |
| T833 |
/workspace/coverage/default/40.sram_ctrl_partial_access.539781017 |
|
|
Aug 13 04:35:21 PM PDT 24 |
Aug 13 04:35:35 PM PDT 24 |
278172224 ps |
| T834 |
/workspace/coverage/default/17.sram_ctrl_bijection.2466749684 |
|
|
Aug 13 04:34:27 PM PDT 24 |
Aug 13 04:34:52 PM PDT 24 |
1316396642 ps |
| T835 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.3530165406 |
|
|
Aug 13 04:34:05 PM PDT 24 |
Aug 13 04:34:27 PM PDT 24 |
294998583 ps |
| T836 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.3633411878 |
|
|
Aug 13 04:34:37 PM PDT 24 |
Aug 13 04:34:43 PM PDT 24 |
1225651637 ps |
| T837 |
/workspace/coverage/default/47.sram_ctrl_regwen.1256197714 |
|
|
Aug 13 04:35:39 PM PDT 24 |
Aug 13 04:45:56 PM PDT 24 |
2372647592 ps |
| T838 |
/workspace/coverage/default/36.sram_ctrl_partial_access.1245357074 |
|
|
Aug 13 04:35:01 PM PDT 24 |
Aug 13 04:35:14 PM PDT 24 |
3431835630 ps |
| T839 |
/workspace/coverage/default/4.sram_ctrl_regwen.1734283638 |
|
|
Aug 13 04:33:59 PM PDT 24 |
Aug 13 05:02:18 PM PDT 24 |
9943377520 ps |
| T840 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.326193334 |
|
|
Aug 13 04:33:43 PM PDT 24 |
Aug 13 04:34:43 PM PDT 24 |
538911869 ps |
| T841 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2619054283 |
|
|
Aug 13 04:34:32 PM PDT 24 |
Aug 13 04:34:45 PM PDT 24 |
1439178349 ps |
| T842 |
/workspace/coverage/default/27.sram_ctrl_bijection.3160286746 |
|
|
Aug 13 04:34:35 PM PDT 24 |
Aug 13 04:35:19 PM PDT 24 |
690109946 ps |
| T843 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3119910288 |
|
|
Aug 13 04:35:01 PM PDT 24 |
Aug 13 04:42:53 PM PDT 24 |
67322697347 ps |
| T844 |
/workspace/coverage/default/18.sram_ctrl_alert_test.1665878888 |
|
|
Aug 13 04:34:32 PM PDT 24 |
Aug 13 04:34:33 PM PDT 24 |
20297893 ps |
| T845 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1927265272 |
|
|
Aug 13 04:35:26 PM PDT 24 |
Aug 13 04:50:36 PM PDT 24 |
16292941686 ps |
| T846 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.1783341333 |
|
|
Aug 13 04:34:59 PM PDT 24 |
Aug 13 04:35:22 PM PDT 24 |
767042737 ps |
| T847 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.145594796 |
|
|
Aug 13 04:33:47 PM PDT 24 |
Aug 13 04:36:16 PM PDT 24 |
4883306921 ps |
| T848 |
/workspace/coverage/default/8.sram_ctrl_stress_all.713816109 |
|
|
Aug 13 04:34:05 PM PDT 24 |
Aug 13 05:58:16 PM PDT 24 |
45532569532 ps |
| T849 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1760881337 |
|
|
Aug 13 04:34:35 PM PDT 24 |
Aug 13 04:36:37 PM PDT 24 |
182027494 ps |
| T850 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1805104276 |
|
|
Aug 13 04:35:03 PM PDT 24 |
Aug 13 04:41:59 PM PDT 24 |
36246500750 ps |
| T851 |
/workspace/coverage/default/9.sram_ctrl_regwen.1162291670 |
|
|
Aug 13 04:34:29 PM PDT 24 |
Aug 13 04:52:05 PM PDT 24 |
35539824112 ps |
| T852 |
/workspace/coverage/default/3.sram_ctrl_stress_all.1891226904 |
|
|
Aug 13 04:33:43 PM PDT 24 |
Aug 13 05:02:56 PM PDT 24 |
45742916481 ps |
| T853 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.2479927838 |
|
|
Aug 13 04:34:21 PM PDT 24 |
Aug 13 04:34:32 PM PDT 24 |
72046991 ps |
| T854 |
/workspace/coverage/default/17.sram_ctrl_alert_test.148806719 |
|
|
Aug 13 04:34:15 PM PDT 24 |
Aug 13 04:34:16 PM PDT 24 |
35425134 ps |
| T855 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1652584463 |
|
|
Aug 13 04:34:24 PM PDT 24 |
Aug 13 04:34:29 PM PDT 24 |
503768809 ps |
| T856 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2665896967 |
|
|
Aug 13 04:33:58 PM PDT 24 |
Aug 13 04:34:05 PM PDT 24 |
2711402749 ps |
| T857 |
/workspace/coverage/default/46.sram_ctrl_smoke.4255976524 |
|
|
Aug 13 04:35:44 PM PDT 24 |
Aug 13 04:35:50 PM PDT 24 |
261727788 ps |
| T858 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.3980695101 |
|
|
Aug 13 04:35:12 PM PDT 24 |
Aug 13 04:40:01 PM PDT 24 |
24412011072 ps |
| T859 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1142287331 |
|
|
Aug 13 04:34:57 PM PDT 24 |
Aug 13 04:34:58 PM PDT 24 |
36487382 ps |
| T860 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.525979286 |
|
|
Aug 13 04:34:39 PM PDT 24 |
Aug 13 04:35:59 PM PDT 24 |
804537514 ps |
| T861 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2275355368 |
|
|
Aug 13 04:35:34 PM PDT 24 |
Aug 13 04:37:52 PM PDT 24 |
1267882051 ps |
| T862 |
/workspace/coverage/default/23.sram_ctrl_executable.3659429404 |
|
|
Aug 13 04:34:35 PM PDT 24 |
Aug 13 04:48:50 PM PDT 24 |
47296024342 ps |
| T863 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.954849735 |
|
|
Aug 13 04:34:58 PM PDT 24 |
Aug 13 04:43:38 PM PDT 24 |
19670510203 ps |
| T864 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2464884483 |
|
|
Aug 13 04:34:17 PM PDT 24 |
Aug 13 04:40:30 PM PDT 24 |
169982097916 ps |
| T865 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3112824651 |
|
|
Aug 13 04:35:30 PM PDT 24 |
Aug 13 04:35:31 PM PDT 24 |
90022092 ps |
| T866 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.4102675123 |
|
|
Aug 13 04:34:15 PM PDT 24 |
Aug 13 04:54:37 PM PDT 24 |
20647315564 ps |
| T867 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.4093105223 |
|
|
Aug 13 04:33:42 PM PDT 24 |
Aug 13 04:33:46 PM PDT 24 |
687352064 ps |
| T868 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2391394968 |
|
|
Aug 13 04:34:32 PM PDT 24 |
Aug 13 04:46:42 PM PDT 24 |
114437665158 ps |
| T869 |
/workspace/coverage/default/31.sram_ctrl_regwen.459175231 |
|
|
Aug 13 04:34:46 PM PDT 24 |
Aug 13 04:37:08 PM PDT 24 |
621587566 ps |
| T870 |
/workspace/coverage/default/44.sram_ctrl_regwen.942073452 |
|
|
Aug 13 04:35:26 PM PDT 24 |
Aug 13 04:46:26 PM PDT 24 |
8404839763 ps |
| T871 |
/workspace/coverage/default/15.sram_ctrl_executable.728976698 |
|
|
Aug 13 04:34:28 PM PDT 24 |
Aug 13 04:55:48 PM PDT 24 |
15162771256 ps |
| T872 |
/workspace/coverage/default/3.sram_ctrl_alert_test.3289348560 |
|
|
Aug 13 04:33:47 PM PDT 24 |
Aug 13 04:33:48 PM PDT 24 |
15463902 ps |
| T873 |
/workspace/coverage/default/38.sram_ctrl_smoke.2127884741 |
|
|
Aug 13 04:35:12 PM PDT 24 |
Aug 13 04:35:55 PM PDT 24 |
405024474 ps |
| T874 |
/workspace/coverage/default/28.sram_ctrl_alert_test.3955669387 |
|
|
Aug 13 04:34:52 PM PDT 24 |
Aug 13 04:34:53 PM PDT 24 |
13202738 ps |
| T875 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2515128863 |
|
|
Aug 13 04:33:41 PM PDT 24 |
Aug 13 04:33:42 PM PDT 24 |
75848132 ps |
| T876 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.184597152 |
|
|
Aug 13 04:34:04 PM PDT 24 |
Aug 13 04:36:10 PM PDT 24 |
640879983 ps |
| T877 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3342074810 |
|
|
Aug 13 04:34:31 PM PDT 24 |
Aug 13 04:34:38 PM PDT 24 |
218901650 ps |
| T878 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3956718885 |
|
|
Aug 13 04:33:42 PM PDT 24 |
Aug 13 04:33:45 PM PDT 24 |
96677156 ps |
| T879 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2015065594 |
|
|
Aug 13 04:34:29 PM PDT 24 |
Aug 13 04:37:51 PM PDT 24 |
2051069387 ps |
| T880 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3664353772 |
|
|
Aug 13 04:35:09 PM PDT 24 |
Aug 13 04:36:30 PM PDT 24 |
262858187 ps |
| T881 |
/workspace/coverage/default/24.sram_ctrl_stress_all.806327554 |
|
|
Aug 13 04:34:35 PM PDT 24 |
Aug 13 05:09:04 PM PDT 24 |
46792643137 ps |
| T882 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4117311858 |
|
|
Aug 13 04:35:38 PM PDT 24 |
Aug 13 04:40:47 PM PDT 24 |
12408090388 ps |
| T883 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.3242087496 |
|
|
Aug 13 04:35:19 PM PDT 24 |
Aug 13 04:35:30 PM PDT 24 |
724700977 ps |
| T884 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.797273411 |
|
|
Aug 13 04:35:10 PM PDT 24 |
Aug 13 04:39:00 PM PDT 24 |
20653808154 ps |
| T885 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.238434166 |
|
|
Aug 13 04:34:27 PM PDT 24 |
Aug 13 04:34:33 PM PDT 24 |
228797443 ps |
| T886 |
/workspace/coverage/default/25.sram_ctrl_regwen.2170644208 |
|
|
Aug 13 04:34:44 PM PDT 24 |
Aug 13 04:37:16 PM PDT 24 |
2336232946 ps |
| T887 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3480965380 |
|
|
Aug 13 04:33:55 PM PDT 24 |
Aug 13 04:33:56 PM PDT 24 |
33444883 ps |
| T888 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3190670399 |
|
|
Aug 13 04:35:33 PM PDT 24 |
Aug 13 04:40:52 PM PDT 24 |
6068325232 ps |
| T889 |
/workspace/coverage/default/7.sram_ctrl_executable.3279272457 |
|
|
Aug 13 04:34:03 PM PDT 24 |
Aug 13 04:39:20 PM PDT 24 |
614541648 ps |
| T890 |
/workspace/coverage/default/41.sram_ctrl_partial_access.4142581030 |
|
|
Aug 13 04:35:21 PM PDT 24 |
Aug 13 04:35:32 PM PDT 24 |
557393868 ps |
| T891 |
/workspace/coverage/default/2.sram_ctrl_smoke.3094639971 |
|
|
Aug 13 04:34:10 PM PDT 24 |
Aug 13 04:34:20 PM PDT 24 |
222578691 ps |
| T892 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.2709317550 |
|
|
Aug 13 04:34:28 PM PDT 24 |
Aug 13 04:48:21 PM PDT 24 |
57769984517 ps |
| T893 |
/workspace/coverage/default/38.sram_ctrl_executable.2945485950 |
|
|
Aug 13 04:35:19 PM PDT 24 |
Aug 13 04:38:03 PM PDT 24 |
12243414957 ps |
| T894 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.3693489537 |
|
|
Aug 13 04:34:42 PM PDT 24 |
Aug 13 04:34:43 PM PDT 24 |
80311420 ps |
| T895 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3009674217 |
|
|
Aug 13 04:35:04 PM PDT 24 |
Aug 13 04:45:17 PM PDT 24 |
2619383212 ps |
| T896 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1329979951 |
|
|
Aug 13 04:33:48 PM PDT 24 |
Aug 13 04:33:49 PM PDT 24 |
92349591 ps |
| T897 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.254303977 |
|
|
Aug 13 04:34:51 PM PDT 24 |
Aug 13 04:38:58 PM PDT 24 |
22988655590 ps |
| T898 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2340865264 |
|
|
Aug 13 04:34:47 PM PDT 24 |
Aug 13 04:35:49 PM PDT 24 |
434647998 ps |
| T899 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1425238523 |
|
|
Aug 13 04:34:35 PM PDT 24 |
Aug 13 04:35:20 PM PDT 24 |
436297583 ps |
| T900 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.557316933 |
|
|
Aug 13 04:34:46 PM PDT 24 |
Aug 13 04:36:46 PM PDT 24 |
809171478 ps |
| T901 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.472715302 |
|
|
Aug 13 04:35:18 PM PDT 24 |
Aug 13 04:36:50 PM PDT 24 |
1481685099 ps |
| T902 |
/workspace/coverage/default/44.sram_ctrl_smoke.1524365479 |
|
|
Aug 13 04:35:27 PM PDT 24 |
Aug 13 04:36:09 PM PDT 24 |
401745258 ps |
| T903 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.2413118742 |
|
|
Aug 13 04:34:32 PM PDT 24 |
Aug 13 04:35:27 PM PDT 24 |
739012724 ps |
| T904 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.4270053431 |
|
|
Aug 13 04:34:38 PM PDT 24 |
Aug 13 04:34:46 PM PDT 24 |
1407564359 ps |
| T905 |
/workspace/coverage/default/32.sram_ctrl_bijection.4173630904 |
|
|
Aug 13 04:35:06 PM PDT 24 |
Aug 13 04:35:50 PM PDT 24 |
915687371 ps |
| T906 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1526175684 |
|
|
Aug 13 04:35:29 PM PDT 24 |
Aug 13 04:35:31 PM PDT 24 |
871387073 ps |
| T907 |
/workspace/coverage/default/16.sram_ctrl_regwen.1388168486 |
|
|
Aug 13 04:34:17 PM PDT 24 |
Aug 13 04:57:33 PM PDT 24 |
17763477218 ps |
| T908 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3040291491 |
|
|
Aug 13 04:35:27 PM PDT 24 |
Aug 13 04:35:28 PM PDT 24 |
25799358 ps |
| T909 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1581175213 |
|
|
Aug 13 04:35:16 PM PDT 24 |
Aug 13 04:35:17 PM PDT 24 |
38049650 ps |
| T910 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2709529015 |
|
|
Aug 13 04:33:45 PM PDT 24 |
Aug 13 04:39:15 PM PDT 24 |
50063074995 ps |
| T911 |
/workspace/coverage/default/21.sram_ctrl_regwen.3547535781 |
|
|
Aug 13 04:34:37 PM PDT 24 |
Aug 13 04:38:45 PM PDT 24 |
6461693242 ps |
| T912 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.15195445 |
|
|
Aug 13 04:35:11 PM PDT 24 |
Aug 13 04:41:30 PM PDT 24 |
16386227072 ps |
| T913 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.921489624 |
|
|
Aug 13 04:34:22 PM PDT 24 |
Aug 13 04:38:13 PM PDT 24 |
2347619074 ps |
| T914 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3315906418 |
|
|
Aug 13 04:33:32 PM PDT 24 |
Aug 13 04:35:10 PM PDT 24 |
765153519 ps |
| T915 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.302172577 |
|
|
Aug 13 04:34:20 PM PDT 24 |
Aug 13 04:34:23 PM PDT 24 |
160463990 ps |
| T916 |
/workspace/coverage/default/7.sram_ctrl_smoke.1243527786 |
|
|
Aug 13 04:33:45 PM PDT 24 |
Aug 13 04:33:56 PM PDT 24 |
1733541570 ps |
| T917 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3606539107 |
|
|
Aug 13 04:35:57 PM PDT 24 |
Aug 13 04:35:58 PM PDT 24 |
117999646 ps |
| T918 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.1888951725 |
|
|
Aug 13 04:34:35 PM PDT 24 |
Aug 13 04:34:36 PM PDT 24 |
69078426 ps |
| T919 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1436333125 |
|
|
Aug 13 04:35:10 PM PDT 24 |
Aug 13 04:35:12 PM PDT 24 |
371767007 ps |
| T920 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1153991195 |
|
|
Aug 13 04:34:39 PM PDT 24 |
Aug 13 04:36:05 PM PDT 24 |
1121384792 ps |
| T921 |
/workspace/coverage/default/16.sram_ctrl_smoke.1541258104 |
|
|
Aug 13 04:34:31 PM PDT 24 |
Aug 13 04:35:11 PM PDT 24 |
406858051 ps |
| T922 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3456734683 |
|
|
Aug 13 04:34:26 PM PDT 24 |
Aug 13 04:34:30 PM PDT 24 |
196864829 ps |
| T923 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.2128892313 |
|
|
Aug 13 04:34:18 PM PDT 24 |
Aug 13 04:47:09 PM PDT 24 |
2362839573 ps |
| T924 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3619674914 |
|
|
Aug 13 04:35:04 PM PDT 24 |
Aug 13 04:35:05 PM PDT 24 |
199922028 ps |
| T925 |
/workspace/coverage/default/28.sram_ctrl_partial_access.2213122199 |
|
|
Aug 13 04:34:41 PM PDT 24 |
Aug 13 04:34:54 PM PDT 24 |
1571930620 ps |
| T926 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1791057102 |
|
|
Aug 13 04:34:45 PM PDT 24 |
Aug 13 04:34:48 PM PDT 24 |
110446500 ps |
| T927 |
/workspace/coverage/default/43.sram_ctrl_smoke.4156431207 |
|
|
Aug 13 04:35:30 PM PDT 24 |
Aug 13 04:35:45 PM PDT 24 |
2693992928 ps |
| T928 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.3239171274 |
|
|
Aug 13 04:34:24 PM PDT 24 |
Aug 13 04:34:30 PM PDT 24 |
190527709 ps |
| T929 |
/workspace/coverage/default/32.sram_ctrl_smoke.1503198869 |
|
|
Aug 13 04:35:00 PM PDT 24 |
Aug 13 04:35:11 PM PDT 24 |
727212585 ps |
| T930 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3806509750 |
|
|
Aug 13 04:34:33 PM PDT 24 |
Aug 13 04:53:32 PM PDT 24 |
22143877519 ps |
| T931 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.655076182 |
|
|
Aug 13 04:34:34 PM PDT 24 |
Aug 13 04:39:55 PM PDT 24 |
6857811687 ps |
| T66 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2117389167 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:42 PM PDT 24 |
421946427 ps |
| T60 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3517016946 |
|
|
Aug 13 05:22:27 PM PDT 24 |
Aug 13 05:22:29 PM PDT 24 |
2063499973 ps |
| T67 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.593820834 |
|
|
Aug 13 05:22:46 PM PDT 24 |
Aug 13 05:22:48 PM PDT 24 |
268624885 ps |
| T84 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2699859464 |
|
|
Aug 13 05:22:37 PM PDT 24 |
Aug 13 05:22:37 PM PDT 24 |
33536628 ps |
| T932 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.333757757 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:41 PM PDT 24 |
520958952 ps |
| T933 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2488162994 |
|
|
Aug 13 05:22:33 PM PDT 24 |
Aug 13 05:22:35 PM PDT 24 |
77013889 ps |
| T934 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4123159498 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:42 PM PDT 24 |
799515838 ps |
| T935 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2003129329 |
|
|
Aug 13 05:22:47 PM PDT 24 |
Aug 13 05:22:48 PM PDT 24 |
56302085 ps |
| T936 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4111473281 |
|
|
Aug 13 05:22:36 PM PDT 24 |
Aug 13 05:22:38 PM PDT 24 |
37122836 ps |
| T937 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.116706714 |
|
|
Aug 13 05:22:27 PM PDT 24 |
Aug 13 05:22:28 PM PDT 24 |
98525932 ps |
| T111 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2347936278 |
|
|
Aug 13 05:22:34 PM PDT 24 |
Aug 13 05:22:34 PM PDT 24 |
17320433 ps |
| T118 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3220488805 |
|
|
Aug 13 05:22:49 PM PDT 24 |
Aug 13 05:22:50 PM PDT 24 |
39670446 ps |
| T938 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2627180804 |
|
|
Aug 13 05:22:21 PM PDT 24 |
Aug 13 05:22:23 PM PDT 24 |
29197555 ps |
| T85 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.545839001 |
|
|
Aug 13 05:22:59 PM PDT 24 |
Aug 13 05:23:00 PM PDT 24 |
58550993 ps |
| T939 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3374573839 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:40 PM PDT 24 |
29474455 ps |
| T86 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.758566267 |
|
|
Aug 13 05:22:56 PM PDT 24 |
Aug 13 05:22:57 PM PDT 24 |
33246404 ps |
| T112 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1811015357 |
|
|
Aug 13 05:22:47 PM PDT 24 |
Aug 13 05:22:48 PM PDT 24 |
16946601 ps |
| T87 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3616958762 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:40 PM PDT 24 |
489451797 ps |
| T119 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.793596581 |
|
|
Aug 13 05:22:40 PM PDT 24 |
Aug 13 05:22:41 PM PDT 24 |
67276598 ps |
| T940 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.963325552 |
|
|
Aug 13 05:22:40 PM PDT 24 |
Aug 13 05:22:41 PM PDT 24 |
39098376 ps |
| T88 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2735304135 |
|
|
Aug 13 05:22:56 PM PDT 24 |
Aug 13 05:22:58 PM PDT 24 |
207567282 ps |
| T941 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3657831634 |
|
|
Aug 13 05:22:31 PM PDT 24 |
Aug 13 05:22:33 PM PDT 24 |
72116366 ps |
| T113 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1994195879 |
|
|
Aug 13 05:22:48 PM PDT 24 |
Aug 13 05:22:49 PM PDT 24 |
19814128 ps |
| T114 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2429875100 |
|
|
Aug 13 05:22:42 PM PDT 24 |
Aug 13 05:22:43 PM PDT 24 |
47978168 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2421249048 |
|
|
Aug 13 05:22:33 PM PDT 24 |
Aug 13 05:22:36 PM PDT 24 |
170135371 ps |
| T89 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.14737221 |
|
|
Aug 13 05:22:51 PM PDT 24 |
Aug 13 05:22:53 PM PDT 24 |
116409377 ps |
| T61 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1190458675 |
|
|
Aug 13 05:22:44 PM PDT 24 |
Aug 13 05:22:45 PM PDT 24 |
589650296 ps |
| T62 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.379306585 |
|
|
Aug 13 05:22:43 PM PDT 24 |
Aug 13 05:22:45 PM PDT 24 |
369771190 ps |
| T943 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.272479151 |
|
|
Aug 13 05:22:37 PM PDT 24 |
Aug 13 05:22:40 PM PDT 24 |
130575167 ps |
| T130 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3851992152 |
|
|
Aug 13 05:22:25 PM PDT 24 |
Aug 13 05:22:27 PM PDT 24 |
104609894 ps |
| T131 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2901561288 |
|
|
Aug 13 05:22:42 PM PDT 24 |
Aug 13 05:22:44 PM PDT 24 |
124832124 ps |
| T90 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1305129938 |
|
|
Aug 13 05:22:29 PM PDT 24 |
Aug 13 05:22:30 PM PDT 24 |
11970883 ps |
| T944 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2431305830 |
|
|
Aug 13 05:22:47 PM PDT 24 |
Aug 13 05:22:50 PM PDT 24 |
67425247 ps |
| T91 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2898341614 |
|
|
Aug 13 05:22:59 PM PDT 24 |
Aug 13 05:23:00 PM PDT 24 |
27937202 ps |
| T134 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1237879391 |
|
|
Aug 13 05:22:35 PM PDT 24 |
Aug 13 05:22:37 PM PDT 24 |
741786416 ps |
| T945 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4282365846 |
|
|
Aug 13 05:22:22 PM PDT 24 |
Aug 13 05:22:24 PM PDT 24 |
32179294 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1392288343 |
|
|
Aug 13 05:22:56 PM PDT 24 |
Aug 13 05:22:57 PM PDT 24 |
48557360 ps |
| T946 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3838577092 |
|
|
Aug 13 05:22:35 PM PDT 24 |
Aug 13 05:22:37 PM PDT 24 |
225637099 ps |
| T947 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2369672877 |
|
|
Aug 13 05:22:34 PM PDT 24 |
Aug 13 05:22:35 PM PDT 24 |
19377659 ps |
| T948 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.721444739 |
|
|
Aug 13 05:22:56 PM PDT 24 |
Aug 13 05:22:56 PM PDT 24 |
28995299 ps |
| T136 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.232790625 |
|
|
Aug 13 05:22:29 PM PDT 24 |
Aug 13 05:22:37 PM PDT 24 |
296658224 ps |
| T137 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.979959929 |
|
|
Aug 13 05:23:00 PM PDT 24 |
Aug 13 05:23:02 PM PDT 24 |
332943692 ps |
| T949 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3532453234 |
|
|
Aug 13 05:22:35 PM PDT 24 |
Aug 13 05:22:36 PM PDT 24 |
50948546 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2592381033 |
|
|
Aug 13 05:22:53 PM PDT 24 |
Aug 13 05:22:54 PM PDT 24 |
78476433 ps |
| T951 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1827223554 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:38 PM PDT 24 |
18186706 ps |
| T952 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3281313848 |
|
|
Aug 13 05:22:36 PM PDT 24 |
Aug 13 05:22:37 PM PDT 24 |
38654266 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.99338022 |
|
|
Aug 13 05:22:27 PM PDT 24 |
Aug 13 05:22:29 PM PDT 24 |
42393971 ps |
| T954 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1702116437 |
|
|
Aug 13 05:22:30 PM PDT 24 |
Aug 13 05:22:34 PM PDT 24 |
403803595 ps |
| T955 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1683889823 |
|
|
Aug 13 05:22:27 PM PDT 24 |
Aug 13 05:22:31 PM PDT 24 |
435120744 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.138457528 |
|
|
Aug 13 05:22:40 PM PDT 24 |
Aug 13 05:22:41 PM PDT 24 |
20630386 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2325128498 |
|
|
Aug 13 05:22:34 PM PDT 24 |
Aug 13 05:22:35 PM PDT 24 |
182227881 ps |
| T958 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3275525593 |
|
|
Aug 13 05:22:41 PM PDT 24 |
Aug 13 05:22:41 PM PDT 24 |
18237973 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.174539448 |
|
|
Aug 13 05:22:41 PM PDT 24 |
Aug 13 05:22:43 PM PDT 24 |
41540534 ps |
| T960 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2716510424 |
|
|
Aug 13 05:22:32 PM PDT 24 |
Aug 13 05:22:34 PM PDT 24 |
210821080 ps |
| T135 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2065584756 |
|
|
Aug 13 05:22:42 PM PDT 24 |
Aug 13 05:22:45 PM PDT 24 |
459792332 ps |
| T961 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2783737063 |
|
|
Aug 13 05:22:45 PM PDT 24 |
Aug 13 05:22:46 PM PDT 24 |
17031948 ps |
| T138 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3590213041 |
|
|
Aug 13 05:22:19 PM PDT 24 |
Aug 13 05:22:20 PM PDT 24 |
183228920 ps |
| T962 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.194473860 |
|
|
Aug 13 05:22:44 PM PDT 24 |
Aug 13 05:22:45 PM PDT 24 |
29477839 ps |
| T94 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3266394375 |
|
|
Aug 13 05:22:20 PM PDT 24 |
Aug 13 05:22:21 PM PDT 24 |
14636694 ps |
| T95 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1728843324 |
|
|
Aug 13 05:22:44 PM PDT 24 |
Aug 13 05:22:47 PM PDT 24 |
893471050 ps |
| T96 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.722407969 |
|
|
Aug 13 05:22:36 PM PDT 24 |
Aug 13 05:22:38 PM PDT 24 |
1834068564 ps |
| T963 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1369404372 |
|
|
Aug 13 05:22:51 PM PDT 24 |
Aug 13 05:22:55 PM PDT 24 |
1972938344 ps |
| T141 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3276313491 |
|
|
Aug 13 05:22:43 PM PDT 24 |
Aug 13 05:22:45 PM PDT 24 |
1036876151 ps |
| T964 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2387542536 |
|
|
Aug 13 05:22:31 PM PDT 24 |
Aug 13 05:22:33 PM PDT 24 |
158739357 ps |
| T965 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1400325456 |
|
|
Aug 13 05:22:22 PM PDT 24 |
Aug 13 05:22:24 PM PDT 24 |
23702830 ps |
| T966 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3924956060 |
|
|
Aug 13 05:22:52 PM PDT 24 |
Aug 13 05:22:53 PM PDT 24 |
33094130 ps |
| T967 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4272899781 |
|
|
Aug 13 05:22:31 PM PDT 24 |
Aug 13 05:22:34 PM PDT 24 |
40188988 ps |
| T132 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2431925349 |
|
|
Aug 13 05:22:23 PM PDT 24 |
Aug 13 05:22:26 PM PDT 24 |
171017389 ps |
| T142 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1332946250 |
|
|
Aug 13 05:22:36 PM PDT 24 |
Aug 13 05:22:39 PM PDT 24 |
182159484 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1533071992 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:39 PM PDT 24 |
55683665 ps |
| T969 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2128358839 |
|
|
Aug 13 05:22:40 PM PDT 24 |
Aug 13 05:22:45 PM PDT 24 |
862282545 ps |
| T97 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4275177187 |
|
|
Aug 13 05:22:33 PM PDT 24 |
Aug 13 05:22:35 PM PDT 24 |
458914274 ps |
| T970 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2311999037 |
|
|
Aug 13 05:22:48 PM PDT 24 |
Aug 13 05:22:49 PM PDT 24 |
20438600 ps |
| T971 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1236767799 |
|
|
Aug 13 05:22:49 PM PDT 24 |
Aug 13 05:22:50 PM PDT 24 |
39391780 ps |
| T98 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.773127973 |
|
|
Aug 13 05:22:48 PM PDT 24 |
Aug 13 05:22:51 PM PDT 24 |
464609127 ps |
| T972 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2059138901 |
|
|
Aug 13 05:22:49 PM PDT 24 |
Aug 13 05:22:50 PM PDT 24 |
100786760 ps |
| T973 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1062478941 |
|
|
Aug 13 05:22:28 PM PDT 24 |
Aug 13 05:22:29 PM PDT 24 |
64865728 ps |
| T99 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.180093634 |
|
|
Aug 13 05:22:16 PM PDT 24 |
Aug 13 05:22:19 PM PDT 24 |
1625427151 ps |
| T100 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3916677194 |
|
|
Aug 13 05:22:28 PM PDT 24 |
Aug 13 05:22:29 PM PDT 24 |
23930895 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4066565011 |
|
|
Aug 13 05:22:42 PM PDT 24 |
Aug 13 05:22:44 PM PDT 24 |
87734132 ps |
| T139 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.831183685 |
|
|
Aug 13 05:22:40 PM PDT 24 |
Aug 13 05:22:41 PM PDT 24 |
79463483 ps |
| T107 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2977154788 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:41 PM PDT 24 |
454621003 ps |
| T975 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2528021102 |
|
|
Aug 13 05:22:57 PM PDT 24 |
Aug 13 05:22:58 PM PDT 24 |
85990176 ps |
| T976 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2456707142 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:40 PM PDT 24 |
60021002 ps |
| T977 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1982600177 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:43 PM PDT 24 |
812428229 ps |
| T978 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3887876165 |
|
|
Aug 13 05:22:42 PM PDT 24 |
Aug 13 05:22:45 PM PDT 24 |
140882675 ps |
| T979 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.889660398 |
|
|
Aug 13 05:22:38 PM PDT 24 |
Aug 13 05:22:39 PM PDT 24 |
59564267 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3760996711 |
|
|
Aug 13 05:22:33 PM PDT 24 |
Aug 13 05:22:34 PM PDT 24 |
11537548 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3920792018 |
|
|
Aug 13 05:22:42 PM PDT 24 |
Aug 13 05:22:46 PM PDT 24 |
48566037 ps |
| T108 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4080456596 |
|
|
Aug 13 05:22:30 PM PDT 24 |
Aug 13 05:22:34 PM PDT 24 |
452993296 ps |
| T133 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2220858227 |
|
|
Aug 13 05:22:27 PM PDT 24 |
Aug 13 05:22:29 PM PDT 24 |
138904243 ps |
| T109 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1155016433 |
|
|
Aug 13 05:22:49 PM PDT 24 |
Aug 13 05:22:52 PM PDT 24 |
899190958 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1570940451 |
|
|
Aug 13 05:22:53 PM PDT 24 |
Aug 13 05:22:54 PM PDT 24 |
23094012 ps |
| T983 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4212440404 |
|
|
Aug 13 05:22:35 PM PDT 24 |
Aug 13 05:22:37 PM PDT 24 |
37578489 ps |
| T984 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1504514483 |
|
|
Aug 13 05:22:48 PM PDT 24 |
Aug 13 05:22:51 PM PDT 24 |
36077374 ps |
| T985 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3207261115 |
|
|
Aug 13 05:22:26 PM PDT 24 |
Aug 13 05:22:30 PM PDT 24 |
426989949 ps |
| T986 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.788789053 |
|
|
Aug 13 05:22:43 PM PDT 24 |
Aug 13 05:22:45 PM PDT 24 |
693192036 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.763108161 |
|
|
Aug 13 05:22:43 PM PDT 24 |
Aug 13 05:22:45 PM PDT 24 |
113337495 ps |
| T110 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3464917184 |
|
|
Aug 13 05:22:32 PM PDT 24 |
Aug 13 05:22:35 PM PDT 24 |
248951761 ps |
| T988 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1627359865 |
|
|
Aug 13 05:22:26 PM PDT 24 |
Aug 13 05:22:28 PM PDT 24 |
29899819 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2317885984 |
|
|
Aug 13 05:22:35 PM PDT 24 |
Aug 13 05:22:36 PM PDT 24 |
18406819 ps |
| T990 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1794074213 |
|
|
Aug 13 05:22:47 PM PDT 24 |
Aug 13 05:22:48 PM PDT 24 |
361254660 ps |
| T991 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2395486753 |
|
|
Aug 13 05:22:40 PM PDT 24 |
Aug 13 05:22:42 PM PDT 24 |
31492009 ps |
| T992 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3752027413 |
|
|
Aug 13 05:22:35 PM PDT 24 |
Aug 13 05:22:36 PM PDT 24 |
65738338 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2856799701 |
|
|
Aug 13 05:22:43 PM PDT 24 |
Aug 13 05:22:45 PM PDT 24 |
95475128 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3254747618 |
|
|
Aug 13 05:22:40 PM PDT 24 |
Aug 13 05:22:40 PM PDT 24 |
24230084 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3516118673 |
|
|
Aug 13 05:22:50 PM PDT 24 |
Aug 13 05:22:51 PM PDT 24 |
71566855 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3324237278 |
|
|
Aug 13 05:22:25 PM PDT 24 |
Aug 13 05:22:26 PM PDT 24 |
97320618 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2526974912 |
|
|
Aug 13 05:22:36 PM PDT 24 |
Aug 13 05:22:37 PM PDT 24 |
35654306 ps |
| T998 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3051559236 |
|
|
Aug 13 05:22:42 PM PDT 24 |
Aug 13 05:22:44 PM PDT 24 |
461876782 ps |
| T999 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3996400524 |
|
|
Aug 13 05:22:42 PM PDT 24 |
Aug 13 05:22:43 PM PDT 24 |
30584758 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4100373691 |
|
|
Aug 13 05:22:24 PM PDT 24 |
Aug 13 05:22:25 PM PDT 24 |
47784046 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.592291164 |
|
|
Aug 13 05:22:41 PM PDT 24 |
Aug 13 05:22:42 PM PDT 24 |
149066622 ps |